2 * Copyright (c) 2007 Ben Dooks
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
7 * PWM driver for Samsung SoCs
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/export.h>
17 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pwm.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/time.h>
28 /* For struct samsung_timer_variant and samsung_pwm_lock. */
29 #include <clocksource/samsung_pwm.h>
31 #define REG_TCFG0 0x00
32 #define REG_TCFG1 0x04
35 #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
36 #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
38 #define TCFG0_PRESCALER_MASK 0xff
39 #define TCFG0_PRESCALER1_SHIFT 8
41 #define TCFG1_MUX_MASK 0xf
42 #define TCFG1_SHIFT(chan) (4 * (chan))
45 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
46 * bits (one channel) after channel 0, so channels have different numbering
47 * when accessing TCON register. See to_tcon_channel() function.
49 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
50 * in its set of bits is 2 as opposed to 3 for other channels.
52 #define TCON_START(chan) BIT(4 * (chan) + 0)
53 #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
54 #define TCON_INVERT(chan) BIT(4 * (chan) + 2)
55 #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
56 #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
57 #define TCON_AUTORELOAD(chan) \
58 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
61 * struct samsung_pwm_channel - private data of PWM channel
62 * @period_ns: current period in nanoseconds programmed to the hardware
63 * @duty_ns: current duty time in nanoseconds programmed to the hardware
64 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
66 struct samsung_pwm_channel
{
73 * struct samsung_pwm_chip - private data of PWM chip
74 * @chip: generic PWM chip
75 * @variant: local copy of hardware variant data
76 * @inverter_mask: inverter status for all channels - one bit per channel
77 * @base: base address of mapped PWM registers
78 * @base_clk: base clock used to drive the timers
79 * @tclk0: external clock 0 (can be ERR_PTR if not present)
80 * @tclk1: external clock 1 (can be ERR_PTR if not present)
82 struct samsung_pwm_chip
{
84 struct samsung_pwm_variant variant
;
93 #ifndef CONFIG_CLKSRC_SAMSUNG_PWM
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
96 * and some registers need access synchronization. If both drivers are
97 * compiled in, the spinlock is defined in the clocksource driver,
98 * otherwise following definition is used.
100 * Currently we do not need any more complex synchronization method
101 * because all the supported SoCs contain only one instance of the PWM
102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.
105 static DEFINE_SPINLOCK(samsung_pwm_lock
);
109 struct samsung_pwm_chip
*to_samsung_pwm_chip(struct pwm_chip
*chip
)
111 return container_of(chip
, struct samsung_pwm_chip
, chip
);
114 static inline unsigned int to_tcon_channel(unsigned int channel
)
116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
117 return (channel
== 0) ? 0 : (channel
+ 1);
120 static void pwm_samsung_set_divisor(struct samsung_pwm_chip
*pwm
,
121 unsigned int channel
, u8 divisor
)
123 u8 shift
= TCFG1_SHIFT(channel
);
128 bits
= (fls(divisor
) - 1) - pwm
->variant
.div_base
;
130 spin_lock_irqsave(&samsung_pwm_lock
, flags
);
132 reg
= readl(pwm
->base
+ REG_TCFG1
);
133 reg
&= ~(TCFG1_MUX_MASK
<< shift
);
134 reg
|= bits
<< shift
;
135 writel(reg
, pwm
->base
+ REG_TCFG1
);
137 spin_unlock_irqrestore(&samsung_pwm_lock
, flags
);
140 static int pwm_samsung_is_tdiv(struct samsung_pwm_chip
*chip
, unsigned int chan
)
142 struct samsung_pwm_variant
*variant
= &chip
->variant
;
145 reg
= readl(chip
->base
+ REG_TCFG1
);
146 reg
>>= TCFG1_SHIFT(chan
);
147 reg
&= TCFG1_MUX_MASK
;
149 return (BIT(reg
) & variant
->tclk_mask
) == 0;
152 static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip
*chip
,
158 rate
= clk_get_rate(chip
->base_clk
);
160 reg
= readl(chip
->base
+ REG_TCFG0
);
162 reg
>>= TCFG0_PRESCALER1_SHIFT
;
163 reg
&= TCFG0_PRESCALER_MASK
;
165 return rate
/ (reg
+ 1);
168 static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip
*chip
,
169 unsigned int chan
, unsigned long freq
)
171 struct samsung_pwm_variant
*variant
= &chip
->variant
;
176 if (!pwm_samsung_is_tdiv(chip
, chan
)) {
177 clk
= (chan
< 2) ? chip
->tclk0
: chip
->tclk1
;
179 rate
= clk_get_rate(clk
);
184 dev_warn(chip
->chip
.dev
,
185 "tclk of PWM %d is inoperational, using tdiv\n", chan
);
188 rate
= pwm_samsung_get_tin_rate(chip
, chan
);
189 dev_dbg(chip
->chip
.dev
, "tin parent at %lu\n", rate
);
192 * Compare minimum PWM frequency that can be achieved with possible
193 * divider settings and choose the lowest divisor that can generate
194 * frequencies lower than requested.
196 for (div
= variant
->div_base
; div
< 4; ++div
)
197 if ((rate
>> (variant
->bits
+ div
)) < freq
)
200 pwm_samsung_set_divisor(chip
, chan
, BIT(div
));
205 static int pwm_samsung_request(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
207 struct samsung_pwm_chip
*our_chip
= to_samsung_pwm_chip(chip
);
208 struct samsung_pwm_channel
*our_chan
;
210 if (!(our_chip
->variant
.output_mask
& BIT(pwm
->hwpwm
))) {
212 "tried to request PWM channel %d without output\n",
217 our_chan
= devm_kzalloc(chip
->dev
, sizeof(*our_chan
), GFP_KERNEL
);
221 pwm_set_chip_data(pwm
, our_chan
);
226 static void pwm_samsung_free(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
228 devm_kfree(chip
->dev
, pwm_get_chip_data(pwm
));
229 pwm_set_chip_data(pwm
, NULL
);
232 static int pwm_samsung_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
234 struct samsung_pwm_chip
*our_chip
= to_samsung_pwm_chip(chip
);
235 unsigned int tcon_chan
= to_tcon_channel(pwm
->hwpwm
);
239 spin_lock_irqsave(&samsung_pwm_lock
, flags
);
241 tcon
= readl(our_chip
->base
+ REG_TCON
);
243 tcon
&= ~TCON_START(tcon_chan
);
244 tcon
|= TCON_MANUALUPDATE(tcon_chan
);
245 writel(tcon
, our_chip
->base
+ REG_TCON
);
247 tcon
&= ~TCON_MANUALUPDATE(tcon_chan
);
248 tcon
|= TCON_START(tcon_chan
) | TCON_AUTORELOAD(tcon_chan
);
249 writel(tcon
, our_chip
->base
+ REG_TCON
);
251 spin_unlock_irqrestore(&samsung_pwm_lock
, flags
);
256 static void pwm_samsung_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
258 struct samsung_pwm_chip
*our_chip
= to_samsung_pwm_chip(chip
);
259 unsigned int tcon_chan
= to_tcon_channel(pwm
->hwpwm
);
263 spin_lock_irqsave(&samsung_pwm_lock
, flags
);
265 tcon
= readl(our_chip
->base
+ REG_TCON
);
266 tcon
&= ~TCON_AUTORELOAD(tcon_chan
);
267 writel(tcon
, our_chip
->base
+ REG_TCON
);
269 spin_unlock_irqrestore(&samsung_pwm_lock
, flags
);
272 static int pwm_samsung_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
273 int duty_ns
, int period_ns
)
275 struct samsung_pwm_chip
*our_chip
= to_samsung_pwm_chip(chip
);
276 struct samsung_pwm_channel
*chan
= pwm_get_chip_data(pwm
);
277 u32 tin_ns
= chan
->tin_ns
, tcnt
, tcmp
;
280 * We currently avoid using 64bit arithmetic by using the
281 * fact that anything faster than 1Hz is easily representable
284 if (period_ns
> NSEC_PER_SEC
)
287 if (period_ns
== chan
->period_ns
&& duty_ns
== chan
->duty_ns
)
290 tcnt
= readl(our_chip
->base
+ REG_TCNTB(pwm
->hwpwm
));
292 /* We need tick count for calculation, not last tick. */
295 /* Check to see if we are changing the clock rate of the PWM. */
296 if (chan
->period_ns
!= period_ns
) {
297 unsigned long tin_rate
;
300 period
= NSEC_PER_SEC
/ period_ns
;
302 dev_dbg(our_chip
->chip
.dev
, "duty_ns=%d, period_ns=%d (%u)\n",
303 duty_ns
, period_ns
, period
);
305 tin_rate
= pwm_samsung_calc_tin(our_chip
, pwm
->hwpwm
, period
);
307 dev_dbg(our_chip
->chip
.dev
, "tin_rate=%lu\n", tin_rate
);
309 tin_ns
= NSEC_PER_SEC
/ tin_rate
;
310 tcnt
= period_ns
/ tin_ns
;
313 /* Period is too short. */
317 /* Note that counters count down. */
318 tcmp
= duty_ns
/ tin_ns
;
320 /* 0% duty is not available */
326 /* Decrement to get tick numbers, instead of tick counts. */
328 /* -1UL will give 100% duty. */
331 dev_dbg(our_chip
->chip
.dev
,
332 "tin_ns=%u, tcmp=%u/%u\n", tin_ns
, tcmp
, tcnt
);
334 /* Update PWM registers. */
335 writel(tcnt
, our_chip
->base
+ REG_TCNTB(pwm
->hwpwm
));
336 writel(tcmp
, our_chip
->base
+ REG_TCMPB(pwm
->hwpwm
));
338 if (test_bit(PWMF_ENABLED
, &pwm
->flags
))
339 pwm_samsung_enable(chip
, pwm
);
341 chan
->period_ns
= period_ns
;
342 chan
->tin_ns
= tin_ns
;
343 chan
->duty_ns
= duty_ns
;
348 static void pwm_samsung_set_invert(struct samsung_pwm_chip
*chip
,
349 unsigned int channel
, bool invert
)
351 unsigned int tcon_chan
= to_tcon_channel(channel
);
355 spin_lock_irqsave(&samsung_pwm_lock
, flags
);
357 tcon
= readl(chip
->base
+ REG_TCON
);
360 chip
->inverter_mask
|= BIT(channel
);
361 tcon
|= TCON_INVERT(tcon_chan
);
363 chip
->inverter_mask
&= ~BIT(channel
);
364 tcon
&= ~TCON_INVERT(tcon_chan
);
367 writel(tcon
, chip
->base
+ REG_TCON
);
369 spin_unlock_irqrestore(&samsung_pwm_lock
, flags
);
372 static int pwm_samsung_set_polarity(struct pwm_chip
*chip
,
373 struct pwm_device
*pwm
,
374 enum pwm_polarity polarity
)
376 struct samsung_pwm_chip
*our_chip
= to_samsung_pwm_chip(chip
);
377 bool invert
= (polarity
== PWM_POLARITY_NORMAL
);
379 /* Inverted means normal in the hardware. */
380 pwm_samsung_set_invert(our_chip
, pwm
->hwpwm
, invert
);
385 static const struct pwm_ops pwm_samsung_ops
= {
386 .request
= pwm_samsung_request
,
387 .free
= pwm_samsung_free
,
388 .enable
= pwm_samsung_enable
,
389 .disable
= pwm_samsung_disable
,
390 .config
= pwm_samsung_config
,
391 .set_polarity
= pwm_samsung_set_polarity
,
392 .owner
= THIS_MODULE
,
396 static const struct samsung_pwm_variant s3c24xx_variant
= {
399 .has_tint_cstat
= false,
403 static const struct samsung_pwm_variant s3c64xx_variant
= {
406 .has_tint_cstat
= true,
407 .tclk_mask
= BIT(7) | BIT(6) | BIT(5),
410 static const struct samsung_pwm_variant s5p64x0_variant
= {
413 .has_tint_cstat
= true,
417 static const struct samsung_pwm_variant s5pc100_variant
= {
420 .has_tint_cstat
= true,
424 static const struct of_device_id samsung_pwm_matches
[] = {
425 { .compatible
= "samsung,s3c2410-pwm", .data
= &s3c24xx_variant
},
426 { .compatible
= "samsung,s3c6400-pwm", .data
= &s3c64xx_variant
},
427 { .compatible
= "samsung,s5p6440-pwm", .data
= &s5p64x0_variant
},
428 { .compatible
= "samsung,s5pc100-pwm", .data
= &s5pc100_variant
},
429 { .compatible
= "samsung,exynos4210-pwm", .data
= &s5p64x0_variant
},
433 static int pwm_samsung_parse_dt(struct samsung_pwm_chip
*chip
)
435 struct device_node
*np
= chip
->chip
.dev
->of_node
;
436 const struct of_device_id
*match
;
437 struct property
*prop
;
441 match
= of_match_node(samsung_pwm_matches
, np
);
445 memcpy(&chip
->variant
, match
->data
, sizeof(chip
->variant
));
447 of_property_for_each_u32(np
, "samsung,pwm-outputs", prop
, cur
, val
) {
448 if (val
>= SAMSUNG_PWM_NUM
) {
449 dev_err(chip
->chip
.dev
,
450 "%s: invalid channel index in samsung,pwm-outputs property\n",
454 chip
->variant
.output_mask
|= BIT(val
);
460 static int pwm_samsung_parse_dt(struct samsung_pwm_chip
*chip
)
466 static int pwm_samsung_probe(struct platform_device
*pdev
)
468 struct device
*dev
= &pdev
->dev
;
469 struct samsung_pwm_chip
*chip
;
470 struct resource
*res
;
474 chip
= devm_kzalloc(&pdev
->dev
, sizeof(*chip
), GFP_KERNEL
);
478 chip
->chip
.dev
= &pdev
->dev
;
479 chip
->chip
.ops
= &pwm_samsung_ops
;
480 chip
->chip
.base
= -1;
481 chip
->chip
.npwm
= SAMSUNG_PWM_NUM
;
482 chip
->inverter_mask
= BIT(SAMSUNG_PWM_NUM
) - 1;
484 if (IS_ENABLED(CONFIG_OF
) && pdev
->dev
.of_node
) {
485 ret
= pwm_samsung_parse_dt(chip
);
489 chip
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
490 chip
->chip
.of_pwm_n_cells
= 3;
492 if (!pdev
->dev
.platform_data
) {
493 dev_err(&pdev
->dev
, "no platform data specified\n");
497 memcpy(&chip
->variant
, pdev
->dev
.platform_data
,
498 sizeof(chip
->variant
));
501 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
502 chip
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
503 if (IS_ERR(chip
->base
))
504 return PTR_ERR(chip
->base
);
506 chip
->base_clk
= devm_clk_get(&pdev
->dev
, "timers");
507 if (IS_ERR(chip
->base_clk
)) {
508 dev_err(dev
, "failed to get timer base clk\n");
509 return PTR_ERR(chip
->base_clk
);
512 ret
= clk_prepare_enable(chip
->base_clk
);
514 dev_err(dev
, "failed to enable base clock\n");
518 for (chan
= 0; chan
< SAMSUNG_PWM_NUM
; ++chan
)
519 if (chip
->variant
.output_mask
& BIT(chan
))
520 pwm_samsung_set_invert(chip
, chan
, true);
522 /* Following clocks are optional. */
523 chip
->tclk0
= devm_clk_get(&pdev
->dev
, "pwm-tclk0");
524 chip
->tclk1
= devm_clk_get(&pdev
->dev
, "pwm-tclk1");
526 platform_set_drvdata(pdev
, chip
);
528 ret
= pwmchip_add(&chip
->chip
);
530 dev_err(dev
, "failed to register PWM chip\n");
531 clk_disable_unprepare(chip
->base_clk
);
535 dev_dbg(dev
, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
536 clk_get_rate(chip
->base_clk
),
537 !IS_ERR(chip
->tclk0
) ? clk_get_rate(chip
->tclk0
) : 0,
538 !IS_ERR(chip
->tclk1
) ? clk_get_rate(chip
->tclk1
) : 0);
543 static int pwm_samsung_remove(struct platform_device
*pdev
)
545 struct samsung_pwm_chip
*chip
= platform_get_drvdata(pdev
);
548 ret
= pwmchip_remove(&chip
->chip
);
552 clk_disable_unprepare(chip
->base_clk
);
557 #ifdef CONFIG_PM_SLEEP
558 static int pwm_samsung_suspend(struct device
*dev
)
560 struct samsung_pwm_chip
*chip
= dev_get_drvdata(dev
);
564 * No one preserves these values during suspend so reset them.
565 * Otherwise driver leaves PWM unconfigured if same values are
566 * passed to pwm_config() next time.
568 for (i
= 0; i
< SAMSUNG_PWM_NUM
; ++i
) {
569 struct pwm_device
*pwm
= &chip
->chip
.pwms
[i
];
570 struct samsung_pwm_channel
*chan
= pwm_get_chip_data(pwm
);
582 static int pwm_samsung_resume(struct device
*dev
)
584 struct samsung_pwm_chip
*chip
= dev_get_drvdata(dev
);
588 * Inverter setting must be preserved across suspend/resume
589 * as nobody really seems to configure it more than once.
591 for (chan
= 0; chan
< SAMSUNG_PWM_NUM
; ++chan
) {
592 if (chip
->variant
.output_mask
& BIT(chan
))
593 pwm_samsung_set_invert(chip
, chan
,
594 chip
->inverter_mask
& BIT(chan
));
601 static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops
, pwm_samsung_suspend
,
604 static struct platform_driver pwm_samsung_driver
= {
606 .name
= "samsung-pwm",
607 .owner
= THIS_MODULE
,
608 .pm
= &pwm_samsung_pm_ops
,
609 .of_match_table
= of_match_ptr(samsung_pwm_matches
),
611 .probe
= pwm_samsung_probe
,
612 .remove
= pwm_samsung_remove
,
614 module_platform_driver(pwm_samsung_driver
);
616 MODULE_LICENSE("GPL");
617 MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
618 MODULE_ALIAS("platform:samsung-pwm");