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rtc: ac100: Add clk output support
[deliverable/linux.git] / drivers / rtc / rtc-ac100.c
1 /*
2 * RTC Driver for X-Powers AC100
3 *
4 * Copyright (c) 2016 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18 #include <linux/bcd.h>
19 #include <linux/clk-provider.h>
20 #include <linux/device.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/ac100.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/of.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/rtc.h>
30 #include <linux/types.h>
31
32 /* Control register */
33 #define AC100_RTC_CTRL_24HOUR BIT(0)
34
35 /* Clock output register bits */
36 #define AC100_CLKOUT_PRE_DIV_SHIFT 5
37 #define AC100_CLKOUT_PRE_DIV_WIDTH 3
38 #define AC100_CLKOUT_MUX_SHIFT 4
39 #define AC100_CLKOUT_MUX_WIDTH 1
40 #define AC100_CLKOUT_DIV_SHIFT 1
41 #define AC100_CLKOUT_DIV_WIDTH 3
42 #define AC100_CLKOUT_EN BIT(0)
43
44 /* RTC */
45 #define AC100_RTC_SEC_MASK GENMASK(6, 0)
46 #define AC100_RTC_MIN_MASK GENMASK(6, 0)
47 #define AC100_RTC_HOU_MASK GENMASK(5, 0)
48 #define AC100_RTC_WEE_MASK GENMASK(2, 0)
49 #define AC100_RTC_DAY_MASK GENMASK(5, 0)
50 #define AC100_RTC_MON_MASK GENMASK(4, 0)
51 #define AC100_RTC_YEA_MASK GENMASK(7, 0)
52 #define AC100_RTC_YEA_LEAP BIT(15)
53 #define AC100_RTC_UPD_TRIGGER BIT(15)
54
55 /* Alarm (wall clock) */
56 #define AC100_ALM_INT_ENABLE BIT(0)
57
58 #define AC100_ALM_SEC_MASK GENMASK(6, 0)
59 #define AC100_ALM_MIN_MASK GENMASK(6, 0)
60 #define AC100_ALM_HOU_MASK GENMASK(5, 0)
61 #define AC100_ALM_WEE_MASK GENMASK(2, 0)
62 #define AC100_ALM_DAY_MASK GENMASK(5, 0)
63 #define AC100_ALM_MON_MASK GENMASK(4, 0)
64 #define AC100_ALM_YEA_MASK GENMASK(7, 0)
65 #define AC100_ALM_ENABLE_FLAG BIT(15)
66 #define AC100_ALM_UPD_TRIGGER BIT(15)
67
68 /*
69 * The year parameter passed to the driver is usually an offset relative to
70 * the year 1900. This macro is used to convert this offset to another one
71 * relative to the minimum year allowed by the hardware.
72 *
73 * The year range is 1970 - 2069. This range is selected to match Allwinner's
74 * driver.
75 */
76 #define AC100_YEAR_MIN 1970
77 #define AC100_YEAR_MAX 2069
78 #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
79
80 struct ac100_clkout {
81 struct clk_hw hw;
82 struct regmap *regmap;
83 u8 offset;
84 };
85
86 #define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
87
88 #define AC100_RTC_32K_NAME "ac100-rtc-32k"
89 #define AC100_RTC_32K_RATE 32768
90 #define AC100_CLKOUT_NUM 3
91
92 static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
93 "ac100-cko1-rtc",
94 "ac100-cko2-rtc",
95 "ac100-cko3-rtc",
96 };
97
98 struct ac100_rtc_dev {
99 struct rtc_device *rtc;
100 struct device *dev;
101 struct regmap *regmap;
102 int irq;
103 unsigned long alarm;
104
105 struct clk_hw *rtc_32k_clk;
106 struct ac100_clkout clks[AC100_CLKOUT_NUM];
107 struct clk_hw_onecell_data *clk_data;
108 };
109
110 /**
111 * Clock controls for 3 clock output pins
112 */
113
114 static const struct clk_div_table ac100_clkout_prediv[] = {
115 { .val = 0, .div = 1 },
116 { .val = 1, .div = 2 },
117 { .val = 2, .div = 4 },
118 { .val = 3, .div = 8 },
119 { .val = 4, .div = 16 },
120 { .val = 5, .div = 32 },
121 { .val = 6, .div = 64 },
122 { .val = 7, .div = 122 },
123 { },
124 };
125
126 /* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
127 static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
128 unsigned long prate)
129 {
130 struct ac100_clkout *clk = to_ac100_clkout(hw);
131 unsigned int reg, div;
132
133 regmap_read(clk->regmap, clk->offset, &reg);
134
135 /* Handle pre-divider first */
136 if (prate != AC100_RTC_32K_RATE) {
137 div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
138 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
139 prate = divider_recalc_rate(hw, prate, div,
140 ac100_clkout_prediv, 0);
141 }
142
143 div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
144 (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
145 return divider_recalc_rate(hw, prate, div, NULL,
146 CLK_DIVIDER_POWER_OF_TWO);
147 }
148
149 static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
150 unsigned long prate)
151 {
152 unsigned long best_rate = 0, tmp_rate, tmp_prate;
153 int i;
154
155 if (prate == AC100_RTC_32K_RATE)
156 return divider_round_rate(hw, rate, &prate, NULL,
157 AC100_CLKOUT_DIV_WIDTH,
158 CLK_DIVIDER_POWER_OF_TWO);
159
160 for (i = 0; ac100_clkout_prediv[i].div; i++) {
161 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
162 tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
163 AC100_CLKOUT_DIV_WIDTH,
164 CLK_DIVIDER_POWER_OF_TWO);
165
166 if (tmp_rate > rate)
167 continue;
168 if (rate - tmp_rate < best_rate - tmp_rate)
169 best_rate = tmp_rate;
170 }
171
172 return best_rate;
173 }
174
175 static int ac100_clkout_determine_rate(struct clk_hw *hw,
176 struct clk_rate_request *req)
177 {
178 struct clk_hw *best_parent;
179 unsigned long best = 0;
180 int i, num_parents = clk_hw_get_num_parents(hw);
181
182 for (i = 0; i < num_parents; i++) {
183 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
184 unsigned long tmp, prate = clk_hw_get_rate(parent);
185
186 tmp = ac100_clkout_round_rate(hw, req->rate, prate);
187
188 if (tmp > req->rate)
189 continue;
190 if (req->rate - tmp < req->rate - best) {
191 best = tmp;
192 best_parent = parent;
193 }
194 }
195
196 if (!best)
197 return -EINVAL;
198
199 req->best_parent_hw = best_parent;
200 req->best_parent_rate = best;
201 req->rate = best;
202
203 return 0;
204 }
205
206 static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
207 unsigned long prate)
208 {
209 struct ac100_clkout *clk = to_ac100_clkout(hw);
210 int div = 0, pre_div = 0;
211
212 do {
213 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
214 prate, NULL, AC100_CLKOUT_DIV_WIDTH,
215 CLK_DIVIDER_POWER_OF_TWO);
216 if (div >= 0)
217 break;
218 } while (prate != AC100_RTC_32K_RATE &&
219 ac100_clkout_prediv[++pre_div].div);
220
221 if (div < 0)
222 return div;
223
224 pre_div = ac100_clkout_prediv[pre_div].val;
225
226 regmap_update_bits(clk->regmap, clk->offset,
227 ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
228 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
229 (div - 1) << AC100_CLKOUT_DIV_SHIFT |
230 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
231
232 return 0;
233 }
234
235 static int ac100_clkout_prepare(struct clk_hw *hw)
236 {
237 struct ac100_clkout *clk = to_ac100_clkout(hw);
238
239 return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
240 AC100_CLKOUT_EN);
241 }
242
243 static void ac100_clkout_unprepare(struct clk_hw *hw)
244 {
245 struct ac100_clkout *clk = to_ac100_clkout(hw);
246
247 regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
248 }
249
250 static int ac100_clkout_is_prepared(struct clk_hw *hw)
251 {
252 struct ac100_clkout *clk = to_ac100_clkout(hw);
253 unsigned int reg;
254
255 regmap_read(clk->regmap, clk->offset, &reg);
256
257 return reg & AC100_CLKOUT_EN;
258 }
259
260 static u8 ac100_clkout_get_parent(struct clk_hw *hw)
261 {
262 struct ac100_clkout *clk = to_ac100_clkout(hw);
263 unsigned int reg;
264
265 regmap_read(clk->regmap, clk->offset, &reg);
266
267 return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
268 }
269
270 static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
271 {
272 struct ac100_clkout *clk = to_ac100_clkout(hw);
273
274 return regmap_update_bits(clk->regmap, clk->offset,
275 BIT(AC100_CLKOUT_MUX_SHIFT),
276 index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
277 }
278
279 static const struct clk_ops ac100_clkout_ops = {
280 .prepare = ac100_clkout_prepare,
281 .unprepare = ac100_clkout_unprepare,
282 .is_prepared = ac100_clkout_is_prepared,
283 .recalc_rate = ac100_clkout_recalc_rate,
284 .determine_rate = ac100_clkout_determine_rate,
285 .get_parent = ac100_clkout_get_parent,
286 .set_parent = ac100_clkout_set_parent,
287 .set_rate = ac100_clkout_set_rate,
288 };
289
290 static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
291 {
292 struct device_node *np = chip->dev->of_node;
293 const char *parents[2] = {AC100_RTC_32K_NAME};
294 int i, ret;
295
296 chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +
297 sizeof(*chip->clk_data->hws) *
298 AC100_CLKOUT_NUM,
299 GFP_KERNEL);
300 if (!chip->clk_data)
301 return -ENOMEM;
302
303 chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
304 AC100_RTC_32K_NAME,
305 NULL, 0,
306 AC100_RTC_32K_RATE);
307 if (IS_ERR(chip->rtc_32k_clk)) {
308 ret = PTR_ERR(chip->rtc_32k_clk);
309 dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
310 ret);
311 return ret;
312 }
313
314 parents[1] = of_clk_get_parent_name(np, 0);
315 if (!parents[1]) {
316 dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
317 return -EINVAL;
318 }
319
320 for (i = 0; i < AC100_CLKOUT_NUM; i++) {
321 struct ac100_clkout *clk = &chip->clks[i];
322 struct clk_init_data init = {
323 .name = ac100_clkout_names[i],
324 .ops = &ac100_clkout_ops,
325 .parent_names = parents,
326 .num_parents = ARRAY_SIZE(parents),
327 .flags = 0,
328 };
329
330 clk->regmap = chip->regmap;
331 clk->offset = AC100_CLKOUT_CTRL1 + i;
332 clk->hw.init = &init;
333
334 ret = devm_clk_hw_register(chip->dev, &clk->hw);
335 if (ret) {
336 dev_err(chip->dev, "Failed to register clk '%s': %d\n",
337 init.name, ret);
338 goto err_unregister_rtc_32k;
339 }
340
341 chip->clk_data->hws[i] = &clk->hw;
342 }
343
344 chip->clk_data->num = i;
345 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
346 if (ret)
347 goto err_unregister_rtc_32k;
348
349 return 0;
350
351 err_unregister_rtc_32k:
352 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
353
354 return ret;
355 }
356
357 static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
358 {
359 of_clk_del_provider(chip->dev->of_node);
360 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
361 }
362
363 /**
364 * RTC related bits
365 */
366 static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
367 {
368 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
369 struct regmap *regmap = chip->regmap;
370 u16 reg[7];
371 int ret;
372
373 ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
374 if (ret)
375 return ret;
376
377 rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
378 rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
379 rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
380 rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
381 rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
382 rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
383 rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
384 AC100_YEAR_OFF;
385
386 return rtc_valid_tm(rtc_tm);
387 }
388
389 static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
390 {
391 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
392 struct regmap *regmap = chip->regmap;
393 int year;
394 u16 reg[8];
395
396 /* our RTC has a limited year range... */
397 year = rtc_tm->tm_year - AC100_YEAR_OFF;
398 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
399 dev_err(dev, "rtc only supports year in range %d - %d\n",
400 AC100_YEAR_MIN, AC100_YEAR_MAX);
401 return -EINVAL;
402 }
403
404 /* convert to BCD */
405 reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
406 reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
407 reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
408 reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
409 reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
410 reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
411 reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
412 /* trigger write */
413 reg[7] = AC100_RTC_UPD_TRIGGER;
414
415 /* Is it a leap year? */
416 if (is_leap_year(year + AC100_YEAR_OFF + 1900))
417 reg[6] |= AC100_RTC_YEA_LEAP;
418
419 return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
420 }
421
422 static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
423 {
424 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
425 struct regmap *regmap = chip->regmap;
426 unsigned int val;
427
428 val = en ? AC100_ALM_INT_ENABLE : 0;
429
430 return regmap_write(regmap, AC100_ALM_INT_ENA, val);
431 }
432
433 static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
434 {
435 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
436 struct regmap *regmap = chip->regmap;
437 struct rtc_time *alrm_tm = &alrm->time;
438 u16 reg[7];
439 unsigned int val;
440 int ret;
441
442 ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
443 if (ret)
444 return ret;
445
446 alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
447
448 ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
449 if (ret)
450 return ret;
451
452 alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
453 alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
454 alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
455 alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
456 alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
457 alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
458 alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
459 AC100_YEAR_OFF;
460
461 return 0;
462 }
463
464 static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
465 {
466 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
467 struct regmap *regmap = chip->regmap;
468 struct rtc_time *alrm_tm = &alrm->time;
469 u16 reg[8];
470 int year;
471 int ret;
472
473 /* our alarm has a limited year range... */
474 year = alrm_tm->tm_year - AC100_YEAR_OFF;
475 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
476 dev_err(dev, "alarm only supports year in range %d - %d\n",
477 AC100_YEAR_MIN, AC100_YEAR_MAX);
478 return -EINVAL;
479 }
480
481 /* convert to BCD */
482 reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) |
483 AC100_ALM_ENABLE_FLAG;
484 reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) |
485 AC100_ALM_ENABLE_FLAG;
486 reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
487 AC100_ALM_ENABLE_FLAG;
488 /* Do not enable weekday alarm */
489 reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
490 reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
491 AC100_ALM_ENABLE_FLAG;
492 reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) |
493 AC100_ALM_ENABLE_FLAG;
494 reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
495 AC100_ALM_ENABLE_FLAG;
496 /* trigger write */
497 reg[7] = AC100_ALM_UPD_TRIGGER;
498
499 ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
500 if (ret)
501 return ret;
502
503 return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
504 }
505
506 static irqreturn_t ac100_rtc_irq(int irq, void *data)
507 {
508 struct ac100_rtc_dev *chip = data;
509 struct regmap *regmap = chip->regmap;
510 unsigned int val = 0;
511 int ret;
512
513 mutex_lock(&chip->rtc->ops_lock);
514
515 /* read status */
516 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
517 if (ret)
518 goto out;
519
520 if (val & AC100_ALM_INT_ENABLE) {
521 /* signal rtc framework */
522 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
523
524 /* clear status */
525 ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
526 if (ret)
527 goto out;
528
529 /* disable interrupt */
530 ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
531 if (ret)
532 goto out;
533 }
534
535 out:
536 mutex_unlock(&chip->rtc->ops_lock);
537 return IRQ_HANDLED;
538 }
539
540 static const struct rtc_class_ops ac100_rtc_ops = {
541 .read_time = ac100_rtc_get_time,
542 .set_time = ac100_rtc_set_time,
543 .read_alarm = ac100_rtc_get_alarm,
544 .set_alarm = ac100_rtc_set_alarm,
545 .alarm_irq_enable = ac100_rtc_alarm_irq_enable,
546 };
547
548 static int ac100_rtc_probe(struct platform_device *pdev)
549 {
550 struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
551 struct ac100_rtc_dev *chip;
552 int ret;
553
554 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
555 platform_set_drvdata(pdev, chip);
556 chip->dev = &pdev->dev;
557 chip->regmap = ac100->regmap;
558
559 chip->irq = platform_get_irq(pdev, 0);
560 if (chip->irq < 0) {
561 dev_err(&pdev->dev, "No IRQ resource\n");
562 return chip->irq;
563 }
564
565 ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
566 ac100_rtc_irq,
567 IRQF_SHARED | IRQF_ONESHOT,
568 dev_name(&pdev->dev), chip);
569 if (ret) {
570 dev_err(&pdev->dev, "Could not request IRQ\n");
571 return ret;
572 }
573
574 /* always use 24 hour mode */
575 regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
576 AC100_RTC_CTRL_24HOUR);
577
578 /* disable counter alarm interrupt */
579 regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
580
581 /* clear counter alarm pending interrupts */
582 regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
583
584 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-ac100",
585 &ac100_rtc_ops, THIS_MODULE);
586 if (IS_ERR(chip->rtc)) {
587 dev_err(&pdev->dev, "unable to register device\n");
588 return PTR_ERR(chip->rtc);
589 }
590
591 ret = ac100_rtc_register_clks(chip);
592 if (ret)
593 return ret;
594
595 dev_info(&pdev->dev, "RTC enabled\n");
596
597 return 0;
598 }
599
600 static int ac100_rtc_remove(struct platform_device *pdev)
601 {
602 struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);
603
604 ac100_rtc_unregister_clks(chip);
605
606 return 0;
607 }
608
609 static const struct of_device_id ac100_rtc_match[] = {
610 { .compatible = "x-powers,ac100-rtc" },
611 { },
612 };
613 MODULE_DEVICE_TABLE(of, ac100_rtc_match);
614
615 static struct platform_driver ac100_rtc_driver = {
616 .probe = ac100_rtc_probe,
617 .remove = ac100_rtc_remove,
618 .driver = {
619 .name = "ac100-rtc",
620 .of_match_table = of_match_ptr(ac100_rtc_match),
621 },
622 };
623 module_platform_driver(ac100_rtc_driver);
624
625 MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
626 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
627 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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