2 * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
4 * Copyright (C) 2008 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/bcd.h>
14 #include <linux/rtc.h>
15 #include <linux/workqueue.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/ds1305.h>
22 * Registers ... mask DS1305_WRITE into register address to write,
23 * otherwise you're reading it. All non-bitmask values are BCD.
25 #define DS1305_WRITE 0x80
28 /* RTC date/time ... the main special cases are that we:
29 * - Need fancy "hours" encoding in 12hour mode
30 * - Don't rely on the "day-of-week" field (or tm_wday)
31 * - Are a 21st-century clock (2000 <= year < 2100)
33 #define DS1305_RTC_LEN 7 /* bytes for RTC regs */
35 #define DS1305_SEC 0x00 /* register addresses */
36 #define DS1305_MIN 0x01
37 #define DS1305_HOUR 0x02
38 # define DS1305_HR_12 0x40 /* set == 12 hr mode */
39 # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
40 #define DS1305_WDAY 0x03
41 #define DS1305_MDAY 0x04
42 #define DS1305_MON 0x05
43 #define DS1305_YEAR 0x06
46 /* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
47 * DS1305_ALM_DISABLE disables a match field (some combos are bad).
49 * NOTE that since we don't use WDAY, we limit ourselves to alarms
50 * only one day into the future (vs potentially up to a week).
52 * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
53 * don't currently support them. We'd either need to do it only when
54 * no alarm is pending (not the standard model), or to use the second
55 * alarm (implying that this is a DS1305 not DS1306, *and* that either
56 * it's wired up a second IRQ we know, or that INTCN is set)
58 #define DS1305_ALM_LEN 4 /* bytes for ALM regs */
59 #define DS1305_ALM_DISABLE 0x80
61 #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
62 #define DS1305_ALM1(r) (0x0b + (r))
65 /* three control registers */
66 #define DS1305_CONTROL_LEN 3 /* bytes of control regs */
68 #define DS1305_CONTROL 0x0f /* register addresses */
69 # define DS1305_nEOSC 0x80 /* low enables oscillator */
70 # define DS1305_WP 0x40 /* write protect */
71 # define DS1305_INTCN 0x04 /* clear == only int0 used */
72 # define DS1306_1HZ 0x04 /* enable 1Hz output */
73 # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
74 # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
75 #define DS1305_STATUS 0x10
76 /* status has just AEIx bits, mirrored as IRQFx */
77 #define DS1305_TRICKLE 0x11
78 /* trickle bits are defined in <linux/spi/ds1305.h> */
80 /* a bunch of NVRAM */
81 #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
83 #define DS1305_NVRAM 0x20 /* register addresses */
87 struct spi_device
*spi
;
88 struct rtc_device
*rtc
;
90 struct work_struct work
;
93 #define FLAG_EXITING 0
96 u8 ctrl
[DS1305_CONTROL_LEN
];
100 /*----------------------------------------------------------------------*/
103 * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
104 * software (like a bootloader) which may require it.
107 static unsigned bcd2hour(u8 bcd
)
109 if (bcd
& DS1305_HR_12
) {
112 bcd
&= ~DS1305_HR_12
;
113 if (bcd
& DS1305_HR_PM
) {
115 bcd
&= ~DS1305_HR_PM
;
117 hour
+= bcd2bin(bcd
);
123 static u8
hour2bcd(bool hr12
, int hour
)
128 return DS1305_HR_12
| bin2bcd(hour
);
130 return DS1305_HR_12
| DS1305_HR_PM
| bin2bcd(hour
);
132 return bin2bcd(hour
);
135 /*----------------------------------------------------------------------*/
138 * Interface to RTC framework
141 #ifdef CONFIG_RTC_INTF_DEV
144 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
146 static int ds1305_ioctl(struct device
*dev
, unsigned cmd
, unsigned long arg
)
148 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
150 int status
= -ENOIOCTLCMD
;
152 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
153 buf
[1] = ds1305
->ctrl
[0];
158 if (!(buf
[1] & DS1305_AEI0
))
160 buf
[1] &= ~DS1305_AEI0
;
165 if (ds1305
->ctrl
[0] & DS1305_AEI0
)
167 buf
[1] |= DS1305_AEI0
;
171 status
= spi_write_then_read(ds1305
->spi
, buf
, sizeof buf
,
174 ds1305
->ctrl
[0] = buf
[1];
182 #define ds1305_ioctl NULL
186 * Get/set of date and time is pretty normal.
189 static int ds1305_get_time(struct device
*dev
, struct rtc_time
*time
)
191 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
192 u8 addr
= DS1305_SEC
;
193 u8 buf
[DS1305_RTC_LEN
];
196 /* Use write-then-read to get all the date/time registers
197 * since dma from stack is nonportable
199 status
= spi_write_then_read(ds1305
->spi
, &addr
, sizeof addr
,
204 dev_vdbg(dev
, "%s: %02x %02x %02x, %02x %02x %02x %02x\n",
205 "read", buf
[0], buf
[1], buf
[2], buf
[3],
206 buf
[4], buf
[5], buf
[6]);
208 /* Decode the registers */
209 time
->tm_sec
= bcd2bin(buf
[DS1305_SEC
]);
210 time
->tm_min
= bcd2bin(buf
[DS1305_MIN
]);
211 time
->tm_hour
= bcd2hour(buf
[DS1305_HOUR
]);
212 time
->tm_wday
= buf
[DS1305_WDAY
] - 1;
213 time
->tm_mday
= bcd2bin(buf
[DS1305_MDAY
]);
214 time
->tm_mon
= bcd2bin(buf
[DS1305_MON
]) - 1;
215 time
->tm_year
= bcd2bin(buf
[DS1305_YEAR
]) + 100;
217 dev_vdbg(dev
, "%s secs=%d, mins=%d, "
218 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
219 "read", time
->tm_sec
, time
->tm_min
,
220 time
->tm_hour
, time
->tm_mday
,
221 time
->tm_mon
, time
->tm_year
, time
->tm_wday
);
223 /* Time may not be set */
224 return rtc_valid_tm(time
);
227 static int ds1305_set_time(struct device
*dev
, struct rtc_time
*time
)
229 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
230 u8 buf
[1 + DS1305_RTC_LEN
];
233 dev_vdbg(dev
, "%s secs=%d, mins=%d, "
234 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
235 "write", time
->tm_sec
, time
->tm_min
,
236 time
->tm_hour
, time
->tm_mday
,
237 time
->tm_mon
, time
->tm_year
, time
->tm_wday
);
239 /* Write registers starting at the first time/date address. */
240 *bp
++ = DS1305_WRITE
| DS1305_SEC
;
242 *bp
++ = bin2bcd(time
->tm_sec
);
243 *bp
++ = bin2bcd(time
->tm_min
);
244 *bp
++ = hour2bcd(ds1305
->hr12
, time
->tm_hour
);
245 *bp
++ = (time
->tm_wday
< 7) ? (time
->tm_wday
+ 1) : 1;
246 *bp
++ = bin2bcd(time
->tm_mday
);
247 *bp
++ = bin2bcd(time
->tm_mon
+ 1);
248 *bp
++ = bin2bcd(time
->tm_year
- 100);
250 dev_dbg(dev
, "%s: %02x %02x %02x, %02x %02x %02x %02x\n",
251 "write", buf
[1], buf
[2], buf
[3],
252 buf
[4], buf
[5], buf
[6], buf
[7]);
254 /* use write-then-read since dma from stack is nonportable */
255 return spi_write_then_read(ds1305
->spi
, buf
, sizeof buf
,
260 * Get/set of alarm is a bit funky:
262 * - First there's the inherent raciness of getting the (partitioned)
263 * status of an alarm that could trigger while we're reading parts
266 * - Second there's its limited range (we could increase it a bit by
267 * relying on WDAY), which means it will easily roll over.
269 * - Third there's the choice of two alarms and alarm signals.
270 * Here we use ALM0 and expect that nINT0 (open drain) is used;
271 * that's the only real option for DS1306 runtime alarms, and is
274 * - Fourth, there's also ALM1, and a second interrupt signal:
275 * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
276 * + On DS1306 ALM1 only uses INT1 (an active high pulse)
277 * and it won't work when VCC1 is active.
279 * So to be most general, we should probably set both alarms to the
280 * same value, letting ALM1 be the wakeup event source on DS1306
281 * and handling several wiring options on DS1305.
283 * - Fifth, we support the polled mode (as well as possible; why not?)
284 * even when no interrupt line is wired to an IRQ.
288 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
290 static int ds1305_get_alarm(struct device
*dev
, struct rtc_wkalrm
*alm
)
292 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
293 struct spi_device
*spi
= ds1305
->spi
;
296 u8 buf
[DS1305_ALM_LEN
];
298 /* Refresh control register cache BEFORE reading ALM0 registers,
299 * since reading alarm registers acks any pending IRQ. That
300 * makes returning "pending" status a bit of a lie, but that bit
301 * of EFI status is at best fragile anyway (given IRQ handlers).
303 addr
= DS1305_CONTROL
;
304 status
= spi_write_then_read(spi
, &addr
, sizeof addr
,
305 ds1305
->ctrl
, sizeof ds1305
->ctrl
);
309 alm
->enabled
= !!(ds1305
->ctrl
[0] & DS1305_AEI0
);
310 alm
->pending
= !!(ds1305
->ctrl
[1] & DS1305_AEI0
);
312 /* get and check ALM0 registers */
313 addr
= DS1305_ALM0(DS1305_SEC
);
314 status
= spi_write_then_read(spi
, &addr
, sizeof addr
,
319 dev_vdbg(dev
, "%s: %02x %02x %02x %02x\n",
320 "alm0 read", buf
[DS1305_SEC
], buf
[DS1305_MIN
],
321 buf
[DS1305_HOUR
], buf
[DS1305_WDAY
]);
323 if ((DS1305_ALM_DISABLE
& buf
[DS1305_SEC
])
324 || (DS1305_ALM_DISABLE
& buf
[DS1305_MIN
])
325 || (DS1305_ALM_DISABLE
& buf
[DS1305_HOUR
]))
328 /* Stuff these values into alm->time and let RTC framework code
329 * fill in the rest ... and also handle rollover to tomorrow when
332 alm
->time
.tm_sec
= bcd2bin(buf
[DS1305_SEC
]);
333 alm
->time
.tm_min
= bcd2bin(buf
[DS1305_MIN
]);
334 alm
->time
.tm_hour
= bcd2hour(buf
[DS1305_HOUR
]);
335 alm
->time
.tm_mday
= -1;
336 alm
->time
.tm_mon
= -1;
337 alm
->time
.tm_year
= -1;
338 /* next three fields are unused by Linux */
339 alm
->time
.tm_wday
= -1;
340 alm
->time
.tm_mday
= -1;
341 alm
->time
.tm_isdst
= -1;
347 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
349 static int ds1305_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alm
)
351 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
352 struct spi_device
*spi
= ds1305
->spi
;
353 unsigned long now
, later
;
356 u8 buf
[1 + DS1305_ALM_LEN
];
358 /* convert desired alarm to time_t */
359 status
= rtc_tm_to_time(&alm
->time
, &later
);
363 /* Read current time as time_t */
364 status
= ds1305_get_time(dev
, &tm
);
367 status
= rtc_tm_to_time(&tm
, &now
);
371 /* make sure alarm fires within the next 24 hours */
374 if ((later
- now
) > 24 * 60 * 60)
377 /* disable alarm if needed */
378 if (ds1305
->ctrl
[0] & DS1305_AEI0
) {
379 ds1305
->ctrl
[0] &= ~DS1305_AEI0
;
381 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
382 buf
[1] = ds1305
->ctrl
[0];
383 status
= spi_write_then_read(ds1305
->spi
, buf
, 2, NULL
, 0);
389 buf
[0] = DS1305_WRITE
| DS1305_ALM0(DS1305_SEC
);
390 buf
[1 + DS1305_SEC
] = bin2bcd(alm
->time
.tm_sec
);
391 buf
[1 + DS1305_MIN
] = bin2bcd(alm
->time
.tm_min
);
392 buf
[1 + DS1305_HOUR
] = hour2bcd(ds1305
->hr12
, alm
->time
.tm_hour
);
393 buf
[1 + DS1305_WDAY
] = DS1305_ALM_DISABLE
;
395 dev_dbg(dev
, "%s: %02x %02x %02x %02x\n",
396 "alm0 write", buf
[1 + DS1305_SEC
], buf
[1 + DS1305_MIN
],
397 buf
[1 + DS1305_HOUR
], buf
[1 + DS1305_WDAY
]);
399 status
= spi_write_then_read(spi
, buf
, sizeof buf
, NULL
, 0);
403 /* enable alarm if requested */
405 ds1305
->ctrl
[0] |= DS1305_AEI0
;
407 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
408 buf
[1] = ds1305
->ctrl
[0];
409 status
= spi_write_then_read(ds1305
->spi
, buf
, 2, NULL
, 0);
415 #ifdef CONFIG_PROC_FS
417 static int ds1305_proc(struct device
*dev
, struct seq_file
*seq
)
419 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
421 char *resistors
= "";
423 /* ctrl[2] is treated as read-only; no locking needed */
424 if ((ds1305
->ctrl
[2] & 0xf0) == DS1305_TRICKLE_MAGIC
) {
425 switch (ds1305
->ctrl
[2] & 0x0c) {
426 case DS1305_TRICKLE_DS2
:
427 diodes
= "2 diodes, ";
429 case DS1305_TRICKLE_DS1
:
430 diodes
= "1 diode, ";
435 switch (ds1305
->ctrl
[2] & 0x03) {
436 case DS1305_TRICKLE_2K
:
437 resistors
= "2k Ohm";
439 case DS1305_TRICKLE_4K
:
440 resistors
= "4k Ohm";
442 case DS1305_TRICKLE_8K
:
443 resistors
= "8k Ohm";
452 return seq_printf(seq
,
453 "trickle_charge\t: %s%s\n",
458 #define ds1305_proc NULL
461 static const struct rtc_class_ops ds1305_ops
= {
462 .ioctl
= ds1305_ioctl
,
463 .read_time
= ds1305_get_time
,
464 .set_time
= ds1305_set_time
,
465 .read_alarm
= ds1305_get_alarm
,
466 .set_alarm
= ds1305_set_alarm
,
470 static void ds1305_work(struct work_struct
*work
)
472 struct ds1305
*ds1305
= container_of(work
, struct ds1305
, work
);
473 struct mutex
*lock
= &ds1305
->rtc
->ops_lock
;
474 struct spi_device
*spi
= ds1305
->spi
;
478 /* lock to protect ds1305->ctrl */
481 /* Disable the IRQ, and clear its status ... for now, we "know"
482 * that if more than one alarm is active, they're in sync.
483 * Note that reading ALM data registers also clears IRQ status.
485 ds1305
->ctrl
[0] &= ~(DS1305_AEI1
| DS1305_AEI0
);
488 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
489 buf
[1] = ds1305
->ctrl
[0];
492 status
= spi_write_then_read(spi
, buf
, sizeof buf
,
495 dev_dbg(&spi
->dev
, "clear irq --> %d\n", status
);
499 if (!test_bit(FLAG_EXITING
, &ds1305
->flags
))
500 enable_irq(spi
->irq
);
502 rtc_update_irq(ds1305
->rtc
, 1, RTC_AF
| RTC_IRQF
);
506 * This "real" IRQ handler hands off to a workqueue mostly to allow
507 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
508 * I/O requests in IRQ context (to clear the IRQ status).
510 static irqreturn_t
ds1305_irq(int irq
, void *p
)
512 struct ds1305
*ds1305
= p
;
515 schedule_work(&ds1305
->work
);
519 /*----------------------------------------------------------------------*/
522 * Interface for NVRAM
525 static void msg_init(struct spi_message
*m
, struct spi_transfer
*x
,
526 u8
*addr
, size_t count
, char *tx
, char *rx
)
529 memset(x
, 0, 2 * sizeof(*x
));
533 spi_message_add_tail(x
, m
);
540 spi_message_add_tail(x
, m
);
544 ds1305_nvram_read(struct kobject
*kobj
, struct bin_attribute
*attr
,
545 char *buf
, loff_t off
, size_t count
)
547 struct spi_device
*spi
;
549 struct spi_message m
;
550 struct spi_transfer x
[2];
553 spi
= container_of(kobj
, struct spi_device
, dev
.kobj
);
555 if (unlikely(off
>= DS1305_NVRAM_LEN
))
557 if (count
>= DS1305_NVRAM_LEN
)
558 count
= DS1305_NVRAM_LEN
;
559 if ((off
+ count
) > DS1305_NVRAM_LEN
)
560 count
= DS1305_NVRAM_LEN
- off
;
561 if (unlikely(!count
))
564 addr
= DS1305_NVRAM
+ off
;
565 msg_init(&m
, x
, &addr
, count
, NULL
, buf
);
567 status
= spi_sync(spi
, &m
);
569 dev_err(&spi
->dev
, "nvram %s error %d\n", "read", status
);
570 return (status
< 0) ? status
: count
;
574 ds1305_nvram_write(struct kobject
*kobj
, struct bin_attribute
*attr
,
575 char *buf
, loff_t off
, size_t count
)
577 struct spi_device
*spi
;
579 struct spi_message m
;
580 struct spi_transfer x
[2];
583 spi
= container_of(kobj
, struct spi_device
, dev
.kobj
);
585 if (unlikely(off
>= DS1305_NVRAM_LEN
))
587 if (count
>= DS1305_NVRAM_LEN
)
588 count
= DS1305_NVRAM_LEN
;
589 if ((off
+ count
) > DS1305_NVRAM_LEN
)
590 count
= DS1305_NVRAM_LEN
- off
;
591 if (unlikely(!count
))
594 addr
= (DS1305_WRITE
| DS1305_NVRAM
) + off
;
595 msg_init(&m
, x
, &addr
, count
, buf
, NULL
);
597 status
= spi_sync(spi
, &m
);
599 dev_err(&spi
->dev
, "nvram %s error %d\n", "write", status
);
600 return (status
< 0) ? status
: count
;
603 static struct bin_attribute nvram
= {
604 .attr
.name
= "nvram",
605 .attr
.mode
= S_IRUGO
| S_IWUSR
,
606 .read
= ds1305_nvram_read
,
607 .write
= ds1305_nvram_write
,
608 .size
= DS1305_NVRAM_LEN
,
611 /*----------------------------------------------------------------------*/
614 * Interface to SPI stack
617 static int __devinit
ds1305_probe(struct spi_device
*spi
)
619 struct ds1305
*ds1305
;
620 struct rtc_device
*rtc
;
623 struct ds1305_platform_data
*pdata
= spi
->dev
.platform_data
;
624 bool write_ctrl
= false;
626 /* Sanity check board setup data. This may be hooked up
627 * in 3wire mode, but we don't care. Note that unless
628 * there's an inverter in place, this needs SPI_CS_HIGH!
630 if ((spi
->bits_per_word
&& spi
->bits_per_word
!= 8)
631 || (spi
->max_speed_hz
> 2000000)
632 || !(spi
->mode
& SPI_CPHA
))
635 /* set up driver data */
636 ds1305
= kzalloc(sizeof *ds1305
, GFP_KERNEL
);
640 spi_set_drvdata(spi
, ds1305
);
642 /* read and cache control registers */
643 addr
= DS1305_CONTROL
;
644 status
= spi_write_then_read(spi
, &addr
, sizeof addr
,
645 ds1305
->ctrl
, sizeof ds1305
->ctrl
);
647 dev_dbg(&spi
->dev
, "can't %s, %d\n",
652 dev_dbg(&spi
->dev
, "ctrl %s: %02x %02x %02x\n",
653 "read", ds1305
->ctrl
[0],
654 ds1305
->ctrl
[1], ds1305
->ctrl
[2]);
656 /* Sanity check register values ... partially compensating for the
657 * fact that SPI has no device handshake. A pullup on MISO would
658 * make these tests fail; but not all systems will have one. If
659 * some register is neither 0x00 nor 0xff, a chip is likely there.
661 if ((ds1305
->ctrl
[0] & 0x38) != 0 || (ds1305
->ctrl
[1] & 0xfc) != 0) {
662 dev_dbg(&spi
->dev
, "RTC chip is not present\n");
666 if (ds1305
->ctrl
[2] == 0)
667 dev_dbg(&spi
->dev
, "chip may not be present\n");
669 /* enable writes if needed ... if we were paranoid it would
670 * make sense to enable them only when absolutely necessary.
672 if (ds1305
->ctrl
[0] & DS1305_WP
) {
675 ds1305
->ctrl
[0] &= ~DS1305_WP
;
677 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
678 buf
[1] = ds1305
->ctrl
[0];
679 status
= spi_write_then_read(spi
, buf
, sizeof buf
, NULL
, 0);
681 dev_dbg(&spi
->dev
, "clear WP --> %d\n", status
);
686 /* on DS1305, maybe start oscillator; like most low power
687 * oscillators, it may take a second to stabilize
689 if (ds1305
->ctrl
[0] & DS1305_nEOSC
) {
690 ds1305
->ctrl
[0] &= ~DS1305_nEOSC
;
692 dev_warn(&spi
->dev
, "SET TIME!\n");
695 /* ack any pending IRQs */
696 if (ds1305
->ctrl
[1]) {
701 /* this may need one-time (re)init */
703 /* maybe enable trickle charge */
704 if (((ds1305
->ctrl
[2] & 0xf0) != DS1305_TRICKLE_MAGIC
)) {
705 ds1305
->ctrl
[2] = DS1305_TRICKLE_MAGIC
710 /* on DS1306, configure 1 Hz signal */
711 if (pdata
->is_ds1306
) {
713 if (!(ds1305
->ctrl
[0] & DS1306_1HZ
)) {
714 ds1305
->ctrl
[0] |= DS1306_1HZ
;
718 if (ds1305
->ctrl
[0] & DS1306_1HZ
) {
719 ds1305
->ctrl
[0] &= ~DS1306_1HZ
;
729 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
730 buf
[1] = ds1305
->ctrl
[0];
731 buf
[2] = ds1305
->ctrl
[1];
732 buf
[3] = ds1305
->ctrl
[2];
733 status
= spi_write_then_read(spi
, buf
, sizeof buf
, NULL
, 0);
735 dev_dbg(&spi
->dev
, "can't %s, %d\n",
740 dev_dbg(&spi
->dev
, "ctrl %s: %02x %02x %02x\n",
741 "write", ds1305
->ctrl
[0],
742 ds1305
->ctrl
[1], ds1305
->ctrl
[2]);
745 /* see if non-Linux software set up AM/PM mode */
747 status
= spi_write_then_read(spi
, &addr
, sizeof addr
,
748 &value
, sizeof value
);
750 dev_dbg(&spi
->dev
, "read HOUR --> %d\n", status
);
754 ds1305
->hr12
= (DS1305_HR_12
& value
) != 0;
756 dev_dbg(&spi
->dev
, "AM/PM\n");
758 /* register RTC ... from here on, ds1305->ctrl needs locking */
759 rtc
= rtc_device_register("ds1305", &spi
->dev
,
760 &ds1305_ops
, THIS_MODULE
);
762 status
= PTR_ERR(rtc
);
763 dev_dbg(&spi
->dev
, "register rtc --> %d\n", status
);
768 /* Maybe set up alarm IRQ; be ready to handle it triggering right
769 * away. NOTE that we don't share this. The signal is active low,
770 * and we can't ack it before a SPI message delay. We temporarily
771 * disable the IRQ until it's acked, which lets us work with more
772 * IRQ trigger modes (not all IRQ controllers can do falling edge).
775 INIT_WORK(&ds1305
->work
, ds1305_work
);
776 status
= request_irq(spi
->irq
, ds1305_irq
,
777 0, dev_name(&rtc
->dev
), ds1305
);
779 dev_dbg(&spi
->dev
, "request_irq %d --> %d\n",
786 status
= sysfs_create_bin_file(&spi
->dev
.kobj
, &nvram
);
788 dev_dbg(&spi
->dev
, "register nvram --> %d\n", status
);
795 free_irq(spi
->irq
, ds1305
);
797 rtc_device_unregister(rtc
);
803 static int __devexit
ds1305_remove(struct spi_device
*spi
)
805 struct ds1305
*ds1305
= spi_get_drvdata(spi
);
807 sysfs_remove_bin_file(&spi
->dev
.kobj
, &nvram
);
809 /* carefully shut down irq and workqueue, if present */
811 set_bit(FLAG_EXITING
, &ds1305
->flags
);
812 free_irq(spi
->irq
, ds1305
);
813 flush_scheduled_work();
816 rtc_device_unregister(ds1305
->rtc
);
817 spi_set_drvdata(spi
, NULL
);
822 static struct spi_driver ds1305_driver
= {
823 .driver
.name
= "rtc-ds1305",
824 .driver
.owner
= THIS_MODULE
,
825 .probe
= ds1305_probe
,
826 .remove
= __devexit_p(ds1305_remove
),
827 /* REVISIT add suspend/resume */
830 static int __init
ds1305_init(void)
832 return spi_register_driver(&ds1305_driver
);
834 module_init(ds1305_init
);
836 static void __exit
ds1305_exit(void)
838 spi_unregister_driver(&ds1305_driver
);
840 module_exit(ds1305_exit
);
842 MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
843 MODULE_LICENSE("GPL");
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