projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[deliverable/linux.git] / drivers / s390 / crypto / z90main.c
1 /*
2 * linux/drivers/s390/crypto/z90main.c
3 *
4 * z90crypt 1.3.2
5 *
6 * Copyright (C) 2001, 2004 IBM Corporation
7 * Author(s): Robert Burroughs (burrough@us.ibm.com)
8 * Eric Rossman (edrossma@us.ibm.com)
9 *
10 * Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <asm/uaccess.h> // copy_(from|to)_user
28 #include <linux/compat.h>
29 #include <linux/compiler.h>
30 #include <linux/delay.h> // mdelay
31 #include <linux/init.h>
32 #include <linux/interrupt.h> // for tasklets
33 #include <linux/ioctl32.h>
34 #include <linux/miscdevice.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kobject_uevent.h>
38 #include <linux/proc_fs.h>
39 #include <linux/syscalls.h>
40 #include "z90crypt.h"
41 #include "z90common.h"
42
43 #define VERSION_Z90MAIN_C "$Revision: 1.62 $"
44
45 static char z90main_version[] __initdata =
46 "z90main.o (" VERSION_Z90MAIN_C "/"
47 VERSION_Z90COMMON_H "/" VERSION_Z90CRYPT_H ")";
48
49 extern char z90hardware_version[];
50
51 /**
52 * Defaults that may be modified.
53 */
54
55 /**
56 * You can specify a different minor at compile time.
57 */
58 #ifndef Z90CRYPT_MINOR
59 #define Z90CRYPT_MINOR MISC_DYNAMIC_MINOR
60 #endif
61
62 /**
63 * You can specify a different domain at compile time or on the insmod
64 * command line.
65 */
66 #ifndef DOMAIN_INDEX
67 #define DOMAIN_INDEX -1
68 #endif
69
70 /**
71 * This is the name under which the device is registered in /proc/modules.
72 */
73 #define REG_NAME "z90crypt"
74
75 /**
76 * Cleanup should run every CLEANUPTIME seconds and should clean up requests
77 * older than CLEANUPTIME seconds in the past.
78 */
79 #ifndef CLEANUPTIME
80 #define CLEANUPTIME 15
81 #endif
82
83 /**
84 * Config should run every CONFIGTIME seconds
85 */
86 #ifndef CONFIGTIME
87 #define CONFIGTIME 30
88 #endif
89
90 /**
91 * The first execution of the config task should take place
92 * immediately after initialization
93 */
94 #ifndef INITIAL_CONFIGTIME
95 #define INITIAL_CONFIGTIME 1
96 #endif
97
98 /**
99 * Reader should run every READERTIME milliseconds
100 * With the 100Hz patch for s390, z90crypt can lock the system solid while
101 * under heavy load. We'll try to avoid that.
102 */
103 #ifndef READERTIME
104 #if HZ > 1000
105 #define READERTIME 2
106 #else
107 #define READERTIME 10
108 #endif
109 #endif
110
111 /**
112 * turn long device array index into device pointer
113 */
114 #define LONG2DEVPTR(ndx) (z90crypt.device_p[(ndx)])
115
116 /**
117 * turn short device array index into long device array index
118 */
119 #define SHRT2LONG(ndx) (z90crypt.overall_device_x.device_index[(ndx)])
120
121 /**
122 * turn short device array index into device pointer
123 */
124 #define SHRT2DEVPTR(ndx) LONG2DEVPTR(SHRT2LONG(ndx))
125
126 /**
127 * Status for a work-element
128 */
129 #define STAT_DEFAULT 0x00 // request has not been processed
130
131 #define STAT_ROUTED 0x80 // bit 7: requests get routed to specific device
132 // else, device is determined each write
133 #define STAT_FAILED 0x40 // bit 6: this bit is set if the request failed
134 // before being sent to the hardware.
135 #define STAT_WRITTEN 0x30 // bits 5-4: work to be done, not sent to device
136 // 0x20 // UNUSED state
137 #define STAT_READPEND 0x10 // bits 5-4: work done, we're returning data now
138 #define STAT_NOWORK 0x00 // bits off: no work on any queue
139 #define STAT_RDWRMASK 0x30 // mask for bits 5-4
140
141 /**
142 * Macros to check the status RDWRMASK
143 */
144 #define CHK_RDWRMASK(statbyte) ((statbyte) & STAT_RDWRMASK)
145 #define SET_RDWRMASK(statbyte, newval) \
146 {(statbyte) &= ~STAT_RDWRMASK; (statbyte) |= newval;}
147
148 /**
149 * Audit Trail. Progress of a Work element
150 * audit[0]: Unless noted otherwise, these bits are all set by the process
151 */
152 #define FP_COPYFROM 0x80 // Caller's buffer has been copied to work element
153 #define FP_BUFFREQ 0x40 // Low Level buffer requested
154 #define FP_BUFFGOT 0x20 // Low Level buffer obtained
155 #define FP_SENT 0x10 // Work element sent to a crypto device
156 // (may be set by process or by reader task)
157 #define FP_PENDING 0x08 // Work element placed on pending queue
158 // (may be set by process or by reader task)
159 #define FP_REQUEST 0x04 // Work element placed on request queue
160 #define FP_ASLEEP 0x02 // Work element about to sleep
161 #define FP_AWAKE 0x01 // Work element has been awakened
162
163 /**
164 * audit[1]: These bits are set by the reader task and/or the cleanup task
165 */
166 #define FP_NOTPENDING 0x80 // Work element removed from pending queue
167 #define FP_AWAKENING 0x40 // Caller about to be awakened
168 #define FP_TIMEDOUT 0x20 // Caller timed out
169 #define FP_RESPSIZESET 0x10 // Response size copied to work element
170 #define FP_RESPADDRCOPIED 0x08 // Response address copied to work element
171 #define FP_RESPBUFFCOPIED 0x04 // Response buffer copied to work element
172 #define FP_REMREQUEST 0x02 // Work element removed from request queue
173 #define FP_SIGNALED 0x01 // Work element was awakened by a signal
174
175 /**
176 * audit[2]: unused
177 */
178
179 /**
180 * state of the file handle in private_data.status
181 */
182 #define STAT_OPEN 0
183 #define STAT_CLOSED 1
184
185 /**
186 * PID() expands to the process ID of the current process
187 */
188 #define PID() (current->pid)
189
190 /**
191 * Selected Constants. The number of APs and the number of devices
192 */
193 #ifndef Z90CRYPT_NUM_APS
194 #define Z90CRYPT_NUM_APS 64
195 #endif
196 #ifndef Z90CRYPT_NUM_DEVS
197 #define Z90CRYPT_NUM_DEVS Z90CRYPT_NUM_APS
198 #endif
199
200 /**
201 * Buffer size for receiving responses. The maximum Response Size
202 * is actually the maximum request size, since in an error condition
203 * the request itself may be returned unchanged.
204 */
205 #define MAX_RESPONSE_SIZE 0x0000077C
206
207 /**
208 * A count and status-byte mask
209 */
210 struct status {
211 int st_count; // # of enabled devices
212 int disabled_count; // # of disabled devices
213 int user_disabled_count; // # of devices disabled via proc fs
214 unsigned char st_mask[Z90CRYPT_NUM_APS]; // current status mask
215 };
216
217 /**
218 * The array of device indexes is a mechanism for fast indexing into
219 * a long (and sparse) array. For instance, if APs 3, 9 and 47 are
220 * installed, z90CDeviceIndex[0] is 3, z90CDeviceIndex[1] is 9, and
221 * z90CDeviceIndex[2] is 47.
222 */
223 struct device_x {
224 int device_index[Z90CRYPT_NUM_DEVS];
225 };
226
227 /**
228 * All devices are arranged in a single array: 64 APs
229 */
230 struct device {
231 int dev_type; // PCICA, PCICC, PCIXCC_MCL2,
232 // PCIXCC_MCL3, CEX2C
233 enum devstat dev_stat; // current device status
234 int dev_self_x; // Index in array
235 int disabled; // Set when device is in error
236 int user_disabled; // Set when device is disabled by user
237 int dev_q_depth; // q depth
238 unsigned char * dev_resp_p; // Response buffer address
239 int dev_resp_l; // Response Buffer length
240 int dev_caller_count; // Number of callers
241 int dev_total_req_cnt; // # requests for device since load
242 struct list_head dev_caller_list; // List of callers
243 };
244
245 /**
246 * There's a struct status and a struct device_x for each device type.
247 */
248 struct hdware_block {
249 struct status hdware_mask;
250 struct status type_mask[Z90CRYPT_NUM_TYPES];
251 struct device_x type_x_addr[Z90CRYPT_NUM_TYPES];
252 unsigned char device_type_array[Z90CRYPT_NUM_APS];
253 };
254
255 /**
256 * z90crypt is the topmost data structure in the hierarchy.
257 */
258 struct z90crypt {
259 int max_count; // Nr of possible crypto devices
260 struct status mask;
261 int q_depth_array[Z90CRYPT_NUM_DEVS];
262 int dev_type_array[Z90CRYPT_NUM_DEVS];
263 struct device_x overall_device_x; // array device indexes
264 struct device * device_p[Z90CRYPT_NUM_DEVS];
265 int terminating;
266 int domain_established;// TRUE: domain has been found
267 int cdx; // Crypto Domain Index
268 int len; // Length of this data structure
269 struct hdware_block *hdware_info;
270 };
271
272 /**
273 * An array of these structures is pointed to from dev_caller
274 * The length of the array depends on the device type. For APs,
275 * there are 8.
276 *
277 * The caller buffer is allocated to the user at OPEN. At WRITE,
278 * it contains the request; at READ, the response. The function
279 * send_to_crypto_device converts the request to device-dependent
280 * form and use the caller's OPEN-allocated buffer for the response.
281 *
282 * For the contents of caller_dev_dep_req and caller_dev_dep_req_p
283 * because that points to it, see the discussion in z90hardware.c.
284 * Search for "extended request message block".
285 */
286 struct caller {
287 int caller_buf_l; // length of original request
288 unsigned char * caller_buf_p; // Original request on WRITE
289 int caller_dev_dep_req_l; // len device dependent request
290 unsigned char * caller_dev_dep_req_p; // Device dependent form
291 unsigned char caller_id[8]; // caller-supplied message id
292 struct list_head caller_liste;
293 unsigned char caller_dev_dep_req[MAX_RESPONSE_SIZE];
294 };
295
296 /**
297 * Function prototypes from z90hardware.c
298 */
299 enum hdstat query_online(int, int, int, int *, int *);
300 enum devstat reset_device(int, int, int);
301 enum devstat send_to_AP(int, int, int, unsigned char *);
302 enum devstat receive_from_AP(int, int, int, unsigned char *, unsigned char *);
303 int convert_request(unsigned char *, int, short, int, int, int *,
304 unsigned char *);
305 int convert_response(unsigned char *, unsigned char *, int *, unsigned char *);
306
307 /**
308 * Low level function prototypes
309 */
310 static int create_z90crypt(int *);
311 static int refresh_z90crypt(int *);
312 static int find_crypto_devices(struct status *);
313 static int create_crypto_device(int);
314 static int destroy_crypto_device(int);
315 static void destroy_z90crypt(void);
316 static int refresh_index_array(struct status *, struct device_x *);
317 static int probe_device_type(struct device *);
318 static int probe_PCIXCC_type(struct device *);
319
320 /**
321 * proc fs definitions
322 */
323 static struct proc_dir_entry *z90crypt_entry;
324
325 /**
326 * data structures
327 */
328
329 /**
330 * work_element.opener points back to this structure
331 */
332 struct priv_data {
333 pid_t opener_pid;
334 unsigned char status; // 0: open 1: closed
335 };
336
337 /**
338 * A work element is allocated for each request
339 */
340 struct work_element {
341 struct priv_data *priv_data;
342 pid_t pid;
343 int devindex; // index of device processing this w_e
344 // (If request did not specify device,
345 // -1 until placed onto a queue)
346 int devtype;
347 struct list_head liste; // used for requestq and pendingq
348 char buffer[128]; // local copy of user request
349 int buff_size; // size of the buffer for the request
350 char resp_buff[RESPBUFFSIZE];
351 int resp_buff_size;
352 char __user * resp_addr; // address of response in user space
353 unsigned int funccode; // function code of request
354 wait_queue_head_t waitq;
355 unsigned long requestsent; // time at which the request was sent
356 atomic_t alarmrung; // wake-up signal
357 unsigned char caller_id[8]; // pid + counter, for this w_e
358 unsigned char status[1]; // bits to mark status of the request
359 unsigned char audit[3]; // record of work element's progress
360 unsigned char * requestptr; // address of request buffer
361 int retcode; // return code of request
362 };
363
364 /**
365 * High level function prototypes
366 */
367 static int z90crypt_open(struct inode *, struct file *);
368 static int z90crypt_release(struct inode *, struct file *);
369 static ssize_t z90crypt_read(struct file *, char __user *, size_t, loff_t *);
370 static ssize_t z90crypt_write(struct file *, const char __user *,
371 size_t, loff_t *);
372 static long z90crypt_unlocked_ioctl(struct file *, unsigned int, unsigned long);
373 static long z90crypt_compat_ioctl(struct file *, unsigned int, unsigned long);
374
375 static void z90crypt_reader_task(unsigned long);
376 static void z90crypt_schedule_reader_task(unsigned long);
377 static void z90crypt_config_task(unsigned long);
378 static void z90crypt_cleanup_task(unsigned long);
379
380 static int z90crypt_status(char *, char **, off_t, int, int *, void *);
381 static int z90crypt_status_write(struct file *, const char __user *,
382 unsigned long, void *);
383
384 /**
385 * Storage allocated at initialization and used throughout the life of
386 * this insmod
387 */
388 static int domain = DOMAIN_INDEX;
389 static struct z90crypt z90crypt;
390 static int quiesce_z90crypt;
391 static spinlock_t queuespinlock;
392 static struct list_head request_list;
393 static int requestq_count;
394 static struct list_head pending_list;
395 static int pendingq_count;
396
397 static struct tasklet_struct reader_tasklet;
398 static struct timer_list reader_timer;
399 static struct timer_list config_timer;
400 static struct timer_list cleanup_timer;
401 static atomic_t total_open;
402 static atomic_t z90crypt_step;
403
404 static struct file_operations z90crypt_fops = {
405 .owner = THIS_MODULE,
406 .read = z90crypt_read,
407 .write = z90crypt_write,
408 .unlocked_ioctl = z90crypt_unlocked_ioctl,
409 #ifdef CONFIG_COMPAT
410 .compat_ioctl = z90crypt_compat_ioctl,
411 #endif
412 .open = z90crypt_open,
413 .release = z90crypt_release
414 };
415
416 static struct miscdevice z90crypt_misc_device = {
417 .minor = Z90CRYPT_MINOR,
418 .name = DEV_NAME,
419 .fops = &z90crypt_fops,
420 .devfs_name = DEV_NAME
421 };
422
423 /**
424 * Documentation values.
425 */
426 MODULE_AUTHOR("zSeries Linux Crypto Team: Robert H. Burroughs, Eric D. Rossman"
427 "and Jochen Roehrig");
428 MODULE_DESCRIPTION("zSeries Linux Cryptographic Coprocessor device driver, "
429 "Copyright 2001, 2004 IBM Corporation");
430 MODULE_LICENSE("GPL");
431 module_param(domain, int, 0);
432 MODULE_PARM_DESC(domain, "domain index for device");
433
434 #ifdef CONFIG_COMPAT
435 /**
436 * ioctl32 conversion routines
437 */
438 struct ica_rsa_modexpo_32 { // For 32-bit callers
439 compat_uptr_t inputdata;
440 unsigned int inputdatalength;
441 compat_uptr_t outputdata;
442 unsigned int outputdatalength;
443 compat_uptr_t b_key;
444 compat_uptr_t n_modulus;
445 };
446
447 static long
448 trans_modexpo32(struct file *filp, unsigned int cmd, unsigned long arg)
449 {
450 struct ica_rsa_modexpo_32 __user *mex32u = compat_ptr(arg);
451 struct ica_rsa_modexpo_32 mex32k;
452 struct ica_rsa_modexpo __user *mex64;
453 long ret = 0;
454 unsigned int i;
455
456 if (!access_ok(VERIFY_WRITE, mex32u, sizeof(struct ica_rsa_modexpo_32)))
457 return -EFAULT;
458 mex64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo));
459 if (!access_ok(VERIFY_WRITE, mex64, sizeof(struct ica_rsa_modexpo)))
460 return -EFAULT;
461 if (copy_from_user(&mex32k, mex32u, sizeof(struct ica_rsa_modexpo_32)))
462 return -EFAULT;
463 if (__put_user(compat_ptr(mex32k.inputdata), &mex64->inputdata) ||
464 __put_user(mex32k.inputdatalength, &mex64->inputdatalength) ||
465 __put_user(compat_ptr(mex32k.outputdata), &mex64->outputdata) ||
466 __put_user(mex32k.outputdatalength, &mex64->outputdatalength) ||
467 __put_user(compat_ptr(mex32k.b_key), &mex64->b_key) ||
468 __put_user(compat_ptr(mex32k.n_modulus), &mex64->n_modulus))
469 return -EFAULT;
470 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)mex64);
471 if (!ret)
472 if (__get_user(i, &mex64->outputdatalength) ||
473 __put_user(i, &mex32u->outputdatalength))
474 ret = -EFAULT;
475 return ret;
476 }
477
478 struct ica_rsa_modexpo_crt_32 { // For 32-bit callers
479 compat_uptr_t inputdata;
480 unsigned int inputdatalength;
481 compat_uptr_t outputdata;
482 unsigned int outputdatalength;
483 compat_uptr_t bp_key;
484 compat_uptr_t bq_key;
485 compat_uptr_t np_prime;
486 compat_uptr_t nq_prime;
487 compat_uptr_t u_mult_inv;
488 };
489
490 static long
491 trans_modexpo_crt32(struct file *filp, unsigned int cmd, unsigned long arg)
492 {
493 struct ica_rsa_modexpo_crt_32 __user *crt32u = compat_ptr(arg);
494 struct ica_rsa_modexpo_crt_32 crt32k;
495 struct ica_rsa_modexpo_crt __user *crt64;
496 long ret = 0;
497 unsigned int i;
498
499 if (!access_ok(VERIFY_WRITE, crt32u,
500 sizeof(struct ica_rsa_modexpo_crt_32)))
501 return -EFAULT;
502 crt64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo_crt));
503 if (!access_ok(VERIFY_WRITE, crt64, sizeof(struct ica_rsa_modexpo_crt)))
504 return -EFAULT;
505 if (copy_from_user(&crt32k, crt32u,
506 sizeof(struct ica_rsa_modexpo_crt_32)))
507 return -EFAULT;
508 if (__put_user(compat_ptr(crt32k.inputdata), &crt64->inputdata) ||
509 __put_user(crt32k.inputdatalength, &crt64->inputdatalength) ||
510 __put_user(compat_ptr(crt32k.outputdata), &crt64->outputdata) ||
511 __put_user(crt32k.outputdatalength, &crt64->outputdatalength) ||
512 __put_user(compat_ptr(crt32k.bp_key), &crt64->bp_key) ||
513 __put_user(compat_ptr(crt32k.bq_key), &crt64->bq_key) ||
514 __put_user(compat_ptr(crt32k.np_prime), &crt64->np_prime) ||
515 __put_user(compat_ptr(crt32k.nq_prime), &crt64->nq_prime) ||
516 __put_user(compat_ptr(crt32k.u_mult_inv), &crt64->u_mult_inv))
517 return -EFAULT;
518 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)crt64);
519 if (!ret)
520 if (__get_user(i, &crt64->outputdatalength) ||
521 __put_user(i, &crt32u->outputdatalength))
522 ret = -EFAULT;
523 return ret;
524 }
525
526 static long
527 z90crypt_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
528 {
529 switch (cmd) {
530 case ICAZ90STATUS:
531 case Z90QUIESCE:
532 case Z90STAT_TOTALCOUNT:
533 case Z90STAT_PCICACOUNT:
534 case Z90STAT_PCICCCOUNT:
535 case Z90STAT_PCIXCCCOUNT:
536 case Z90STAT_PCIXCCMCL2COUNT:
537 case Z90STAT_PCIXCCMCL3COUNT:
538 case Z90STAT_CEX2CCOUNT:
539 case Z90STAT_REQUESTQ_COUNT:
540 case Z90STAT_PENDINGQ_COUNT:
541 case Z90STAT_TOTALOPEN_COUNT:
542 case Z90STAT_DOMAIN_INDEX:
543 case Z90STAT_STATUS_MASK:
544 case Z90STAT_QDEPTH_MASK:
545 case Z90STAT_PERDEV_REQCNT:
546 return z90crypt_unlocked_ioctl(filp, cmd, arg);
547 case ICARSAMODEXPO:
548 return trans_modexpo32(filp, cmd, arg);
549 case ICARSACRT:
550 return trans_modexpo_crt32(filp, cmd, arg);
551 default:
552 return -ENOIOCTLCMD;
553 }
554 }
555 #endif
556
557 /**
558 * The module initialization code.
559 */
560 static int __init
561 z90crypt_init_module(void)
562 {
563 int result, nresult;
564 struct proc_dir_entry *entry;
565
566 PDEBUG("PID %d\n", PID());
567
568 if ((domain < -1) || (domain > 15)) {
569 PRINTKW("Invalid param: domain = %d. Not loading.\n", domain);
570 return -EINVAL;
571 }
572
573 /* Register as misc device with given minor (or get a dynamic one). */
574 result = misc_register(&z90crypt_misc_device);
575 if (result < 0) {
576 PRINTKW(KERN_ERR "misc_register (minor %d) failed with %d\n",
577 z90crypt_misc_device.minor, result);
578 return result;
579 }
580
581 PDEBUG("Registered " DEV_NAME " with result %d\n", result);
582
583 result = create_z90crypt(&domain);
584 if (result != 0) {
585 PRINTKW("create_z90crypt (domain index %d) failed with %d.\n",
586 domain, result);
587 result = -ENOMEM;
588 goto init_module_cleanup;
589 }
590
591 if (result == 0) {
592 PRINTKN("Version %d.%d.%d loaded, built on %s %s\n",
593 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT,
594 __DATE__, __TIME__);
595 PRINTKN("%s\n", z90main_version);
596 PRINTKN("%s\n", z90hardware_version);
597 PDEBUG("create_z90crypt (domain index %d) successful.\n",
598 domain);
599 } else
600 PRINTK("No devices at startup\n");
601
602 /* Initialize globals. */
603 spin_lock_init(&queuespinlock);
604
605 INIT_LIST_HEAD(&pending_list);
606 pendingq_count = 0;
607
608 INIT_LIST_HEAD(&request_list);
609 requestq_count = 0;
610
611 quiesce_z90crypt = 0;
612
613 atomic_set(&total_open, 0);
614 atomic_set(&z90crypt_step, 0);
615
616 /* Set up the cleanup task. */
617 init_timer(&cleanup_timer);
618 cleanup_timer.function = z90crypt_cleanup_task;
619 cleanup_timer.data = 0;
620 cleanup_timer.expires = jiffies + (CLEANUPTIME * HZ);
621 add_timer(&cleanup_timer);
622
623 /* Set up the proc file system */
624 entry = create_proc_entry("driver/z90crypt", 0644, 0);
625 if (entry) {
626 entry->nlink = 1;
627 entry->data = 0;
628 entry->read_proc = z90crypt_status;
629 entry->write_proc = z90crypt_status_write;
630 }
631 else
632 PRINTK("Couldn't create z90crypt proc entry\n");
633 z90crypt_entry = entry;
634
635 /* Set up the configuration task. */
636 init_timer(&config_timer);
637 config_timer.function = z90crypt_config_task;
638 config_timer.data = 0;
639 config_timer.expires = jiffies + (INITIAL_CONFIGTIME * HZ);
640 add_timer(&config_timer);
641
642 /* Set up the reader task */
643 tasklet_init(&reader_tasklet, z90crypt_reader_task, 0);
644 init_timer(&reader_timer);
645 reader_timer.function = z90crypt_schedule_reader_task;
646 reader_timer.data = 0;
647 reader_timer.expires = jiffies + (READERTIME * HZ / 1000);
648 add_timer(&reader_timer);
649
650 return 0; // success
651
652 init_module_cleanup:
653 if ((nresult = misc_deregister(&z90crypt_misc_device)))
654 PRINTK("misc_deregister failed with %d.\n", nresult);
655 else
656 PDEBUG("misc_deregister successful.\n");
657
658 return result; // failure
659 }
660
661 /**
662 * The module termination code
663 */
664 static void __exit
665 z90crypt_cleanup_module(void)
666 {
667 int nresult;
668
669 PDEBUG("PID %d\n", PID());
670
671 remove_proc_entry("driver/z90crypt", 0);
672
673 if ((nresult = misc_deregister(&z90crypt_misc_device)))
674 PRINTK("misc_deregister failed with %d.\n", nresult);
675 else
676 PDEBUG("misc_deregister successful.\n");
677
678 /* Remove the tasks */
679 tasklet_kill(&reader_tasklet);
680 del_timer(&reader_timer);
681 del_timer(&config_timer);
682 del_timer(&cleanup_timer);
683
684 destroy_z90crypt();
685
686 PRINTKN("Unloaded.\n");
687 }
688
689 /**
690 * Functions running under a process id
691 *
692 * The I/O functions:
693 * z90crypt_open
694 * z90crypt_release
695 * z90crypt_read
696 * z90crypt_write
697 * z90crypt_unlocked_ioctl
698 * z90crypt_status
699 * z90crypt_status_write
700 * disable_card
701 * enable_card
702 *
703 * Helper functions:
704 * z90crypt_rsa
705 * z90crypt_prepare
706 * z90crypt_send
707 * z90crypt_process_results
708 *
709 */
710 static int
711 z90crypt_open(struct inode *inode, struct file *filp)
712 {
713 struct priv_data *private_data_p;
714
715 if (quiesce_z90crypt)
716 return -EQUIESCE;
717
718 private_data_p = kmalloc(sizeof(struct priv_data), GFP_KERNEL);
719 if (!private_data_p) {
720 PRINTK("Memory allocate failed\n");
721 return -ENOMEM;
722 }
723
724 memset((void *)private_data_p, 0, sizeof(struct priv_data));
725 private_data_p->status = STAT_OPEN;
726 private_data_p->opener_pid = PID();
727 filp->private_data = private_data_p;
728 atomic_inc(&total_open);
729
730 return 0;
731 }
732
733 static int
734 z90crypt_release(struct inode *inode, struct file *filp)
735 {
736 struct priv_data *private_data_p = filp->private_data;
737
738 PDEBUG("PID %d (filp %p)\n", PID(), filp);
739
740 private_data_p->status = STAT_CLOSED;
741 memset(private_data_p, 0, sizeof(struct priv_data));
742 kfree(private_data_p);
743 atomic_dec(&total_open);
744
745 return 0;
746 }
747
748 /*
749 * there are two read functions, of which compile options will choose one
750 * without USE_GET_RANDOM_BYTES
751 * => read() always returns -EPERM;
752 * otherwise
753 * => read() uses get_random_bytes() kernel function
754 */
755 #ifndef USE_GET_RANDOM_BYTES
756 /**
757 * z90crypt_read will not be supported beyond z90crypt 1.3.1
758 */
759 static ssize_t
760 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
761 {
762 PDEBUG("filp %p (PID %d)\n", filp, PID());
763 return -EPERM;
764 }
765 #else // we want to use get_random_bytes
766 /**
767 * read() just returns a string of random bytes. Since we have no way
768 * to generate these cryptographically, we just execute get_random_bytes
769 * for the length specified.
770 */
771 #include <linux/random.h>
772 static ssize_t
773 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
774 {
775 unsigned char *temp_buff;
776
777 PDEBUG("filp %p (PID %d)\n", filp, PID());
778
779 if (quiesce_z90crypt)
780 return -EQUIESCE;
781 if (count < 0) {
782 PRINTK("Requested random byte count negative: %ld\n", count);
783 return -EINVAL;
784 }
785 if (count > RESPBUFFSIZE) {
786 PDEBUG("count[%d] > RESPBUFFSIZE", count);
787 return -EINVAL;
788 }
789 if (count == 0)
790 return 0;
791 temp_buff = kmalloc(RESPBUFFSIZE, GFP_KERNEL);
792 if (!temp_buff) {
793 PRINTK("Memory allocate failed\n");
794 return -ENOMEM;
795 }
796 get_random_bytes(temp_buff, count);
797
798 if (copy_to_user(buf, temp_buff, count) != 0) {
799 kfree(temp_buff);
800 return -EFAULT;
801 }
802 kfree(temp_buff);
803 return count;
804 }
805 #endif
806
807 /**
808 * Write is is not allowed
809 */
810 static ssize_t
811 z90crypt_write(struct file *filp, const char __user *buf, size_t count, loff_t *f_pos)
812 {
813 PDEBUG("filp %p (PID %d)\n", filp, PID());
814 return -EPERM;
815 }
816
817 /**
818 * New status functions
819 */
820 static inline int
821 get_status_totalcount(void)
822 {
823 return z90crypt.hdware_info->hdware_mask.st_count;
824 }
825
826 static inline int
827 get_status_PCICAcount(void)
828 {
829 return z90crypt.hdware_info->type_mask[PCICA].st_count;
830 }
831
832 static inline int
833 get_status_PCICCcount(void)
834 {
835 return z90crypt.hdware_info->type_mask[PCICC].st_count;
836 }
837
838 static inline int
839 get_status_PCIXCCcount(void)
840 {
841 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count +
842 z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
843 }
844
845 static inline int
846 get_status_PCIXCCMCL2count(void)
847 {
848 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count;
849 }
850
851 static inline int
852 get_status_PCIXCCMCL3count(void)
853 {
854 return z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
855 }
856
857 static inline int
858 get_status_CEX2Ccount(void)
859 {
860 return z90crypt.hdware_info->type_mask[CEX2C].st_count;
861 }
862
863 static inline int
864 get_status_requestq_count(void)
865 {
866 return requestq_count;
867 }
868
869 static inline int
870 get_status_pendingq_count(void)
871 {
872 return pendingq_count;
873 }
874
875 static inline int
876 get_status_totalopen_count(void)
877 {
878 return atomic_read(&total_open);
879 }
880
881 static inline int
882 get_status_domain_index(void)
883 {
884 return z90crypt.cdx;
885 }
886
887 static inline unsigned char *
888 get_status_status_mask(unsigned char status[Z90CRYPT_NUM_APS])
889 {
890 int i, ix;
891
892 memcpy(status, z90crypt.hdware_info->device_type_array,
893 Z90CRYPT_NUM_APS);
894
895 for (i = 0; i < get_status_totalcount(); i++) {
896 ix = SHRT2LONG(i);
897 if (LONG2DEVPTR(ix)->user_disabled)
898 status[ix] = 0x0d;
899 }
900
901 return status;
902 }
903
904 static inline unsigned char *
905 get_status_qdepth_mask(unsigned char qdepth[Z90CRYPT_NUM_APS])
906 {
907 int i, ix;
908
909 memset(qdepth, 0, Z90CRYPT_NUM_APS);
910
911 for (i = 0; i < get_status_totalcount(); i++) {
912 ix = SHRT2LONG(i);
913 qdepth[ix] = LONG2DEVPTR(ix)->dev_caller_count;
914 }
915
916 return qdepth;
917 }
918
919 static inline unsigned int *
920 get_status_perdevice_reqcnt(unsigned int reqcnt[Z90CRYPT_NUM_APS])
921 {
922 int i, ix;
923
924 memset(reqcnt, 0, Z90CRYPT_NUM_APS * sizeof(int));
925
926 for (i = 0; i < get_status_totalcount(); i++) {
927 ix = SHRT2LONG(i);
928 reqcnt[ix] = LONG2DEVPTR(ix)->dev_total_req_cnt;
929 }
930
931 return reqcnt;
932 }
933
934 static inline void
935 init_work_element(struct work_element *we_p,
936 struct priv_data *priv_data, pid_t pid)
937 {
938 int step;
939
940 we_p->requestptr = (unsigned char *)we_p + sizeof(struct work_element);
941 /* Come up with a unique id for this caller. */
942 step = atomic_inc_return(&z90crypt_step);
943 memcpy(we_p->caller_id+0, (void *) &pid, sizeof(pid));
944 memcpy(we_p->caller_id+4, (void *) &step, sizeof(step));
945 we_p->pid = pid;
946 we_p->priv_data = priv_data;
947 we_p->status[0] = STAT_DEFAULT;
948 we_p->audit[0] = 0x00;
949 we_p->audit[1] = 0x00;
950 we_p->audit[2] = 0x00;
951 we_p->resp_buff_size = 0;
952 we_p->retcode = 0;
953 we_p->devindex = -1;
954 we_p->devtype = -1;
955 atomic_set(&we_p->alarmrung, 0);
956 init_waitqueue_head(&we_p->waitq);
957 INIT_LIST_HEAD(&(we_p->liste));
958 }
959
960 static inline int
961 allocate_work_element(struct work_element **we_pp,
962 struct priv_data *priv_data_p, pid_t pid)
963 {
964 struct work_element *we_p;
965
966 we_p = (struct work_element *) get_zeroed_page(GFP_KERNEL);
967 if (!we_p)
968 return -ENOMEM;
969 init_work_element(we_p, priv_data_p, pid);
970 *we_pp = we_p;
971 return 0;
972 }
973
974 static inline void
975 remove_device(struct device *device_p)
976 {
977 if (!device_p || (device_p->disabled != 0))
978 return;
979 device_p->disabled = 1;
980 z90crypt.hdware_info->type_mask[device_p->dev_type].disabled_count++;
981 z90crypt.hdware_info->hdware_mask.disabled_count++;
982 }
983
984 /**
985 * Bitlength limits for each card
986 *
987 * There are new MCLs which allow more bitlengths. See the table for details.
988 * The MCL must be applied and the newer bitlengths enabled for these to work.
989 *
990 * Card Type Old limit New limit
991 * PCICA ??-2048 same (the lower limit is less than 128 bit...)
992 * PCICC 512-1024 512-2048
993 * PCIXCC_MCL2 512-2048 ----- (applying any GA LIC will make an MCL3 card)
994 * PCIXCC_MCL3 ----- 128-2048
995 * CEX2C 512-2048 128-2048
996 *
997 * ext_bitlens (extended bitlengths) is a global, since you should not apply an
998 * MCL to just one card in a machine. We assume, at first, that all cards have
999 * these capabilities.
1000 */
1001 int ext_bitlens = 1; // This is global
1002 #define PCIXCC_MIN_MOD_SIZE 16 // 128 bits
1003 #define OLD_PCIXCC_MIN_MOD_SIZE 64 // 512 bits
1004 #define PCICC_MIN_MOD_SIZE 64 // 512 bits
1005 #define OLD_PCICC_MAX_MOD_SIZE 128 // 1024 bits
1006 #define MAX_MOD_SIZE 256 // 2048 bits
1007
1008 static inline int
1009 select_device_type(int *dev_type_p, int bytelength)
1010 {
1011 static int count = 0;
1012 int PCICA_avail, PCIXCC_MCL3_avail, CEX2C_avail, index_to_use;
1013 struct status *stat;
1014 if ((*dev_type_p != PCICC) && (*dev_type_p != PCICA) &&
1015 (*dev_type_p != PCIXCC_MCL2) && (*dev_type_p != PCIXCC_MCL3) &&
1016 (*dev_type_p != CEX2C) && (*dev_type_p != ANYDEV))
1017 return -1;
1018 if (*dev_type_p != ANYDEV) {
1019 stat = &z90crypt.hdware_info->type_mask[*dev_type_p];
1020 if (stat->st_count >
1021 (stat->disabled_count + stat->user_disabled_count))
1022 return 0;
1023 return -1;
1024 }
1025
1026 /* Assumption: PCICA, PCIXCC_MCL3, and CEX2C are all similar in speed */
1027 stat = &z90crypt.hdware_info->type_mask[PCICA];
1028 PCICA_avail = stat->st_count -
1029 (stat->disabled_count + stat->user_disabled_count);
1030 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL3];
1031 PCIXCC_MCL3_avail = stat->st_count -
1032 (stat->disabled_count + stat->user_disabled_count);
1033 stat = &z90crypt.hdware_info->type_mask[CEX2C];
1034 CEX2C_avail = stat->st_count -
1035 (stat->disabled_count + stat->user_disabled_count);
1036 if (PCICA_avail || PCIXCC_MCL3_avail || CEX2C_avail) {
1037 /**
1038 * bitlength is a factor, PCICA is the most capable, even with
1039 * the new MCL for PCIXCC.
1040 */
1041 if ((bytelength < PCIXCC_MIN_MOD_SIZE) ||
1042 (!ext_bitlens && (bytelength < OLD_PCIXCC_MIN_MOD_SIZE))) {
1043 if (!PCICA_avail)
1044 return -1;
1045 else {
1046 *dev_type_p = PCICA;
1047 return 0;
1048 }
1049 }
1050
1051 index_to_use = count % (PCICA_avail + PCIXCC_MCL3_avail +
1052 CEX2C_avail);
1053 if (index_to_use < PCICA_avail)
1054 *dev_type_p = PCICA;
1055 else if (index_to_use < (PCICA_avail + PCIXCC_MCL3_avail))
1056 *dev_type_p = PCIXCC_MCL3;
1057 else
1058 *dev_type_p = CEX2C;
1059 count++;
1060 return 0;
1061 }
1062
1063 /* Less than OLD_PCIXCC_MIN_MOD_SIZE cannot go to a PCIXCC_MCL2 */
1064 if (bytelength < OLD_PCIXCC_MIN_MOD_SIZE)
1065 return -1;
1066 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL2];
1067 if (stat->st_count >
1068 (stat->disabled_count + stat->user_disabled_count)) {
1069 *dev_type_p = PCIXCC_MCL2;
1070 return 0;
1071 }
1072
1073 /**
1074 * Less than PCICC_MIN_MOD_SIZE or more than OLD_PCICC_MAX_MOD_SIZE
1075 * (if we don't have the MCL applied and the newer bitlengths enabled)
1076 * cannot go to a PCICC
1077 */
1078 if ((bytelength < PCICC_MIN_MOD_SIZE) ||
1079 (!ext_bitlens && (bytelength > OLD_PCICC_MAX_MOD_SIZE))) {
1080 return -1;
1081 }
1082 stat = &z90crypt.hdware_info->type_mask[PCICC];
1083 if (stat->st_count >
1084 (stat->disabled_count + stat->user_disabled_count)) {
1085 *dev_type_p = PCICC;
1086 return 0;
1087 }
1088
1089 return -1;
1090 }
1091
1092 /**
1093 * Try the selected number, then the selected type (can be ANYDEV)
1094 */
1095 static inline int
1096 select_device(int *dev_type_p, int *device_nr_p, int bytelength)
1097 {
1098 int i, indx, devTp, low_count, low_indx;
1099 struct device_x *index_p;
1100 struct device *dev_ptr;
1101
1102 PDEBUG("device type = %d, index = %d\n", *dev_type_p, *device_nr_p);
1103 if ((*device_nr_p >= 0) && (*device_nr_p < Z90CRYPT_NUM_DEVS)) {
1104 PDEBUG("trying index = %d\n", *device_nr_p);
1105 dev_ptr = z90crypt.device_p[*device_nr_p];
1106
1107 if (dev_ptr &&
1108 (dev_ptr->dev_stat != DEV_GONE) &&
1109 (dev_ptr->disabled == 0) &&
1110 (dev_ptr->user_disabled == 0)) {
1111 PDEBUG("selected by number, index = %d\n",
1112 *device_nr_p);
1113 *dev_type_p = dev_ptr->dev_type;
1114 return *device_nr_p;
1115 }
1116 }
1117 *device_nr_p = -1;
1118 PDEBUG("trying type = %d\n", *dev_type_p);
1119 devTp = *dev_type_p;
1120 if (select_device_type(&devTp, bytelength) == -1) {
1121 PDEBUG("failed to select by type\n");
1122 return -1;
1123 }
1124 PDEBUG("selected type = %d\n", devTp);
1125 index_p = &z90crypt.hdware_info->type_x_addr[devTp];
1126 low_count = 0x0000FFFF;
1127 low_indx = -1;
1128 for (i = 0; i < z90crypt.hdware_info->type_mask[devTp].st_count; i++) {
1129 indx = index_p->device_index[i];
1130 dev_ptr = z90crypt.device_p[indx];
1131 if (dev_ptr &&
1132 (dev_ptr->dev_stat != DEV_GONE) &&
1133 (dev_ptr->disabled == 0) &&
1134 (dev_ptr->user_disabled == 0) &&
1135 (devTp == dev_ptr->dev_type) &&
1136 (low_count > dev_ptr->dev_caller_count)) {
1137 low_count = dev_ptr->dev_caller_count;
1138 low_indx = indx;
1139 }
1140 }
1141 *device_nr_p = low_indx;
1142 return low_indx;
1143 }
1144
1145 static inline int
1146 send_to_crypto_device(struct work_element *we_p)
1147 {
1148 struct caller *caller_p;
1149 struct device *device_p;
1150 int dev_nr;
1151 int bytelen = ((struct ica_rsa_modexpo *)we_p->buffer)->inputdatalength;
1152
1153 if (!we_p->requestptr)
1154 return SEN_FATAL_ERROR;
1155 caller_p = (struct caller *)we_p->requestptr;
1156 dev_nr = we_p->devindex;
1157 if (select_device(&we_p->devtype, &dev_nr, bytelen) == -1) {
1158 if (z90crypt.hdware_info->hdware_mask.st_count != 0)
1159 return SEN_RETRY;
1160 else
1161 return SEN_NOT_AVAIL;
1162 }
1163 we_p->devindex = dev_nr;
1164 device_p = z90crypt.device_p[dev_nr];
1165 if (!device_p)
1166 return SEN_NOT_AVAIL;
1167 if (device_p->dev_type != we_p->devtype)
1168 return SEN_RETRY;
1169 if (device_p->dev_caller_count >= device_p->dev_q_depth)
1170 return SEN_QUEUE_FULL;
1171 PDEBUG("device number prior to send: %d\n", dev_nr);
1172 switch (send_to_AP(dev_nr, z90crypt.cdx,
1173 caller_p->caller_dev_dep_req_l,
1174 caller_p->caller_dev_dep_req_p)) {
1175 case DEV_SEN_EXCEPTION:
1176 PRINTKC("Exception during send to device %d\n", dev_nr);
1177 z90crypt.terminating = 1;
1178 return SEN_FATAL_ERROR;
1179 case DEV_GONE:
1180 PRINTK("Device %d not available\n", dev_nr);
1181 remove_device(device_p);
1182 return SEN_NOT_AVAIL;
1183 case DEV_EMPTY:
1184 return SEN_NOT_AVAIL;
1185 case DEV_NO_WORK:
1186 return SEN_FATAL_ERROR;
1187 case DEV_BAD_MESSAGE:
1188 return SEN_USER_ERROR;
1189 case DEV_QUEUE_FULL:
1190 return SEN_QUEUE_FULL;
1191 default:
1192 case DEV_ONLINE:
1193 break;
1194 }
1195 list_add_tail(&(caller_p->caller_liste), &(device_p->dev_caller_list));
1196 device_p->dev_caller_count++;
1197 return 0;
1198 }
1199
1200 /**
1201 * Send puts the user's work on one of two queues:
1202 * the pending queue if the send was successful
1203 * the request queue if the send failed because device full or busy
1204 */
1205 static inline int
1206 z90crypt_send(struct work_element *we_p, const char *buf)
1207 {
1208 int rv;
1209
1210 PDEBUG("PID %d\n", PID());
1211
1212 if (CHK_RDWRMASK(we_p->status[0]) != STAT_NOWORK) {
1213 PDEBUG("PID %d tried to send more work but has outstanding "
1214 "work.\n", PID());
1215 return -EWORKPEND;
1216 }
1217 we_p->devindex = -1; // Reset device number
1218 spin_lock_irq(&queuespinlock);
1219 rv = send_to_crypto_device(we_p);
1220 switch (rv) {
1221 case 0:
1222 we_p->requestsent = jiffies;
1223 we_p->audit[0] |= FP_SENT;
1224 list_add_tail(&we_p->liste, &pending_list);
1225 ++pendingq_count;
1226 we_p->audit[0] |= FP_PENDING;
1227 break;
1228 case SEN_BUSY:
1229 case SEN_QUEUE_FULL:
1230 rv = 0;
1231 we_p->devindex = -1; // any device will do
1232 we_p->requestsent = jiffies;
1233 list_add_tail(&we_p->liste, &request_list);
1234 ++requestq_count;
1235 we_p->audit[0] |= FP_REQUEST;
1236 break;
1237 case SEN_RETRY:
1238 rv = -ERESTARTSYS;
1239 break;
1240 case SEN_NOT_AVAIL:
1241 PRINTK("*** No devices available.\n");
1242 rv = we_p->retcode = -ENODEV;
1243 we_p->status[0] |= STAT_FAILED;
1244 break;
1245 case REC_OPERAND_INV:
1246 case REC_OPERAND_SIZE:
1247 case REC_EVEN_MOD:
1248 case REC_INVALID_PAD:
1249 rv = we_p->retcode = -EINVAL;
1250 we_p->status[0] |= STAT_FAILED;
1251 break;
1252 default:
1253 we_p->retcode = rv;
1254 we_p->status[0] |= STAT_FAILED;
1255 break;
1256 }
1257 if (rv != -ERESTARTSYS)
1258 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1259 spin_unlock_irq(&queuespinlock);
1260 if (rv == 0)
1261 tasklet_schedule(&reader_tasklet);
1262 return rv;
1263 }
1264
1265 /**
1266 * process_results copies the user's work from kernel space.
1267 */
1268 static inline int
1269 z90crypt_process_results(struct work_element *we_p, char __user *buf)
1270 {
1271 int rv;
1272
1273 PDEBUG("we_p %p (PID %d)\n", we_p, PID());
1274
1275 LONG2DEVPTR(we_p->devindex)->dev_total_req_cnt++;
1276 SET_RDWRMASK(we_p->status[0], STAT_READPEND);
1277
1278 rv = 0;
1279 if (!we_p->buffer) {
1280 PRINTK("we_p %p PID %d in STAT_READPEND: buffer NULL.\n",
1281 we_p, PID());
1282 rv = -ENOBUFF;
1283 }
1284
1285 if (!rv)
1286 if ((rv = copy_to_user(buf, we_p->buffer, we_p->buff_size))) {
1287 PDEBUG("copy_to_user failed: rv = %d\n", rv);
1288 rv = -EFAULT;
1289 }
1290
1291 if (!rv)
1292 rv = we_p->retcode;
1293 if (!rv)
1294 if (we_p->resp_buff_size
1295 && copy_to_user(we_p->resp_addr, we_p->resp_buff,
1296 we_p->resp_buff_size))
1297 rv = -EFAULT;
1298
1299 SET_RDWRMASK(we_p->status[0], STAT_NOWORK);
1300 return rv;
1301 }
1302
1303 static unsigned char NULL_psmid[8] =
1304 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
1305
1306 /**
1307 * Used in device configuration functions
1308 */
1309 #define MAX_RESET 90
1310
1311 /**
1312 * This is used only for PCICC support
1313 */
1314 static inline int
1315 is_PKCS11_padded(unsigned char *buffer, int length)
1316 {
1317 int i;
1318 if ((buffer[0] != 0x00) || (buffer[1] != 0x01))
1319 return 0;
1320 for (i = 2; i < length; i++)
1321 if (buffer[i] != 0xFF)
1322 break;
1323 if ((i < 10) || (i == length))
1324 return 0;
1325 if (buffer[i] != 0x00)
1326 return 0;
1327 return 1;
1328 }
1329
1330 /**
1331 * This is used only for PCICC support
1332 */
1333 static inline int
1334 is_PKCS12_padded(unsigned char *buffer, int length)
1335 {
1336 int i;
1337 if ((buffer[0] != 0x00) || (buffer[1] != 0x02))
1338 return 0;
1339 for (i = 2; i < length; i++)
1340 if (buffer[i] == 0x00)
1341 break;
1342 if ((i < 10) || (i == length))
1343 return 0;
1344 if (buffer[i] != 0x00)
1345 return 0;
1346 return 1;
1347 }
1348
1349 /**
1350 * builds struct caller and converts message from generic format to
1351 * device-dependent format
1352 * func is ICARSAMODEXPO or ICARSACRT
1353 * function is PCI_FUNC_KEY_ENCRYPT or PCI_FUNC_KEY_DECRYPT
1354 */
1355 static inline int
1356 build_caller(struct work_element *we_p, short function)
1357 {
1358 int rv;
1359 struct caller *caller_p = (struct caller *)we_p->requestptr;
1360
1361 if ((we_p->devtype != PCICC) && (we_p->devtype != PCICA) &&
1362 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1363 (we_p->devtype != CEX2C))
1364 return SEN_NOT_AVAIL;
1365
1366 memcpy(caller_p->caller_id, we_p->caller_id,
1367 sizeof(caller_p->caller_id));
1368 caller_p->caller_dev_dep_req_p = caller_p->caller_dev_dep_req;
1369 caller_p->caller_dev_dep_req_l = MAX_RESPONSE_SIZE;
1370 caller_p->caller_buf_p = we_p->buffer;
1371 INIT_LIST_HEAD(&(caller_p->caller_liste));
1372
1373 rv = convert_request(we_p->buffer, we_p->funccode, function,
1374 z90crypt.cdx, we_p->devtype,
1375 &caller_p->caller_dev_dep_req_l,
1376 caller_p->caller_dev_dep_req_p);
1377 if (rv) {
1378 if (rv == SEN_NOT_AVAIL)
1379 PDEBUG("request can't be processed on hdwr avail\n");
1380 else
1381 PRINTK("Error from convert_request: %d\n", rv);
1382 }
1383 else
1384 memcpy(&(caller_p->caller_dev_dep_req_p[4]), we_p->caller_id,8);
1385 return rv;
1386 }
1387
1388 static inline void
1389 unbuild_caller(struct device *device_p, struct caller *caller_p)
1390 {
1391 if (!caller_p)
1392 return;
1393 if (caller_p->caller_liste.next && caller_p->caller_liste.prev)
1394 if (!list_empty(&caller_p->caller_liste)) {
1395 list_del_init(&caller_p->caller_liste);
1396 device_p->dev_caller_count--;
1397 }
1398 memset(caller_p->caller_id, 0, sizeof(caller_p->caller_id));
1399 }
1400
1401 static inline int
1402 get_crypto_request_buffer(struct work_element *we_p)
1403 {
1404 struct ica_rsa_modexpo *mex_p;
1405 struct ica_rsa_modexpo_crt *crt_p;
1406 unsigned char *temp_buffer;
1407 short function;
1408 int rv;
1409
1410 mex_p = (struct ica_rsa_modexpo *) we_p->buffer;
1411 crt_p = (struct ica_rsa_modexpo_crt *) we_p->buffer;
1412
1413 PDEBUG("device type input = %d\n", we_p->devtype);
1414
1415 if (z90crypt.terminating)
1416 return REC_NO_RESPONSE;
1417 if (memcmp(we_p->caller_id, NULL_psmid, 8) == 0) {
1418 PRINTK("psmid zeroes\n");
1419 return SEN_FATAL_ERROR;
1420 }
1421 if (!we_p->buffer) {
1422 PRINTK("buffer pointer NULL\n");
1423 return SEN_USER_ERROR;
1424 }
1425 if (!we_p->requestptr) {
1426 PRINTK("caller pointer NULL\n");
1427 return SEN_USER_ERROR;
1428 }
1429
1430 if ((we_p->devtype != PCICA) && (we_p->devtype != PCICC) &&
1431 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1432 (we_p->devtype != CEX2C) && (we_p->devtype != ANYDEV)) {
1433 PRINTK("invalid device type\n");
1434 return SEN_USER_ERROR;
1435 }
1436
1437 if ((mex_p->inputdatalength < 1) ||
1438 (mex_p->inputdatalength > MAX_MOD_SIZE)) {
1439 PRINTK("inputdatalength[%d] is not valid\n",
1440 mex_p->inputdatalength);
1441 return SEN_USER_ERROR;
1442 }
1443
1444 if (mex_p->outputdatalength < mex_p->inputdatalength) {
1445 PRINTK("outputdatalength[%d] < inputdatalength[%d]\n",
1446 mex_p->outputdatalength, mex_p->inputdatalength);
1447 return SEN_USER_ERROR;
1448 }
1449
1450 if (!mex_p->inputdata || !mex_p->outputdata) {
1451 PRINTK("inputdata[%p] or outputdata[%p] is NULL\n",
1452 mex_p->outputdata, mex_p->inputdata);
1453 return SEN_USER_ERROR;
1454 }
1455
1456 /**
1457 * As long as outputdatalength is big enough, we can set the
1458 * outputdatalength equal to the inputdatalength, since that is the
1459 * number of bytes we will copy in any case
1460 */
1461 mex_p->outputdatalength = mex_p->inputdatalength;
1462
1463 rv = 0;
1464 switch (we_p->funccode) {
1465 case ICARSAMODEXPO:
1466 if (!mex_p->b_key || !mex_p->n_modulus)
1467 rv = SEN_USER_ERROR;
1468 break;
1469 case ICARSACRT:
1470 if (!IS_EVEN(crt_p->inputdatalength)) {
1471 PRINTK("inputdatalength[%d] is odd, CRT form\n",
1472 crt_p->inputdatalength);
1473 rv = SEN_USER_ERROR;
1474 break;
1475 }
1476 if (!crt_p->bp_key ||
1477 !crt_p->bq_key ||
1478 !crt_p->np_prime ||
1479 !crt_p->nq_prime ||
1480 !crt_p->u_mult_inv) {
1481 PRINTK("CRT form, bad data: %p/%p/%p/%p/%p\n",
1482 crt_p->bp_key, crt_p->bq_key,
1483 crt_p->np_prime, crt_p->nq_prime,
1484 crt_p->u_mult_inv);
1485 rv = SEN_USER_ERROR;
1486 }
1487 break;
1488 default:
1489 PRINTK("bad func = %d\n", we_p->funccode);
1490 rv = SEN_USER_ERROR;
1491 break;
1492 }
1493 if (rv != 0)
1494 return rv;
1495
1496 if (select_device_type(&we_p->devtype, mex_p->inputdatalength) < 0)
1497 return SEN_NOT_AVAIL;
1498
1499 temp_buffer = (unsigned char *)we_p + sizeof(struct work_element) +
1500 sizeof(struct caller);
1501 if (copy_from_user(temp_buffer, mex_p->inputdata,
1502 mex_p->inputdatalength) != 0)
1503 return SEN_RELEASED;
1504
1505 function = PCI_FUNC_KEY_ENCRYPT;
1506 switch (we_p->devtype) {
1507 /* PCICA does everything with a simple RSA mod-expo operation */
1508 case PCICA:
1509 function = PCI_FUNC_KEY_ENCRYPT;
1510 break;
1511 /**
1512 * PCIXCC_MCL2 does all Mod-Expo form with a simple RSA mod-expo
1513 * operation, and all CRT forms with a PKCS-1.2 format decrypt.
1514 * PCIXCC_MCL3 and CEX2C do all Mod-Expo and CRT forms with a simple RSA
1515 * mod-expo operation
1516 */
1517 case PCIXCC_MCL2:
1518 if (we_p->funccode == ICARSAMODEXPO)
1519 function = PCI_FUNC_KEY_ENCRYPT;
1520 else
1521 function = PCI_FUNC_KEY_DECRYPT;
1522 break;
1523 case PCIXCC_MCL3:
1524 case CEX2C:
1525 if (we_p->funccode == ICARSAMODEXPO)
1526 function = PCI_FUNC_KEY_ENCRYPT;
1527 else
1528 function = PCI_FUNC_KEY_DECRYPT;
1529 break;
1530 /**
1531 * PCICC does everything as a PKCS-1.2 format request
1532 */
1533 case PCICC:
1534 /* PCICC cannot handle input that is is PKCS#1.1 padded */
1535 if (is_PKCS11_padded(temp_buffer, mex_p->inputdatalength)) {
1536 return SEN_NOT_AVAIL;
1537 }
1538 if (we_p->funccode == ICARSAMODEXPO) {
1539 if (is_PKCS12_padded(temp_buffer,
1540 mex_p->inputdatalength))
1541 function = PCI_FUNC_KEY_ENCRYPT;
1542 else
1543 function = PCI_FUNC_KEY_DECRYPT;
1544 } else
1545 /* all CRT forms are decrypts */
1546 function = PCI_FUNC_KEY_DECRYPT;
1547 break;
1548 }
1549 PDEBUG("function: %04x\n", function);
1550 rv = build_caller(we_p, function);
1551 PDEBUG("rv from build_caller = %d\n", rv);
1552 return rv;
1553 }
1554
1555 static inline int
1556 z90crypt_prepare(struct work_element *we_p, unsigned int funccode,
1557 const char __user *buffer)
1558 {
1559 int rv;
1560
1561 we_p->devindex = -1;
1562 if (funccode == ICARSAMODEXPO)
1563 we_p->buff_size = sizeof(struct ica_rsa_modexpo);
1564 else
1565 we_p->buff_size = sizeof(struct ica_rsa_modexpo_crt);
1566
1567 if (copy_from_user(we_p->buffer, buffer, we_p->buff_size))
1568 return -EFAULT;
1569
1570 we_p->audit[0] |= FP_COPYFROM;
1571 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1572 we_p->funccode = funccode;
1573 we_p->devtype = -1;
1574 we_p->audit[0] |= FP_BUFFREQ;
1575 rv = get_crypto_request_buffer(we_p);
1576 switch (rv) {
1577 case 0:
1578 we_p->audit[0] |= FP_BUFFGOT;
1579 break;
1580 case SEN_USER_ERROR:
1581 rv = -EINVAL;
1582 break;
1583 case SEN_QUEUE_FULL:
1584 rv = 0;
1585 break;
1586 case SEN_RELEASED:
1587 rv = -EFAULT;
1588 break;
1589 case REC_NO_RESPONSE:
1590 rv = -ENODEV;
1591 break;
1592 case SEN_NOT_AVAIL:
1593 case EGETBUFF:
1594 rv = -EGETBUFF;
1595 break;
1596 default:
1597 PRINTK("rv = %d\n", rv);
1598 rv = -EGETBUFF;
1599 break;
1600 }
1601 if (CHK_RDWRMASK(we_p->status[0]) == STAT_WRITTEN)
1602 SET_RDWRMASK(we_p->status[0], STAT_DEFAULT);
1603 return rv;
1604 }
1605
1606 static inline void
1607 purge_work_element(struct work_element *we_p)
1608 {
1609 struct list_head *lptr;
1610
1611 spin_lock_irq(&queuespinlock);
1612 list_for_each(lptr, &request_list) {
1613 if (lptr == &we_p->liste) {
1614 list_del_init(lptr);
1615 requestq_count--;
1616 break;
1617 }
1618 }
1619 list_for_each(lptr, &pending_list) {
1620 if (lptr == &we_p->liste) {
1621 list_del_init(lptr);
1622 pendingq_count--;
1623 break;
1624 }
1625 }
1626 spin_unlock_irq(&queuespinlock);
1627 }
1628
1629 /**
1630 * Build the request and send it.
1631 */
1632 static inline int
1633 z90crypt_rsa(struct priv_data *private_data_p, pid_t pid,
1634 unsigned int cmd, unsigned long arg)
1635 {
1636 struct work_element *we_p;
1637 int rv;
1638
1639 if ((rv = allocate_work_element(&we_p, private_data_p, pid))) {
1640 PDEBUG("PID %d: allocate_work_element returned ENOMEM\n", pid);
1641 return rv;
1642 }
1643 if ((rv = z90crypt_prepare(we_p, cmd, (const char __user *)arg)))
1644 PDEBUG("PID %d: rv = %d from z90crypt_prepare\n", pid, rv);
1645 if (!rv)
1646 if ((rv = z90crypt_send(we_p, (const char *)arg)))
1647 PDEBUG("PID %d: rv %d from z90crypt_send.\n", pid, rv);
1648 if (!rv) {
1649 we_p->audit[0] |= FP_ASLEEP;
1650 wait_event(we_p->waitq, atomic_read(&we_p->alarmrung));
1651 we_p->audit[0] |= FP_AWAKE;
1652 rv = we_p->retcode;
1653 }
1654 if (!rv)
1655 rv = z90crypt_process_results(we_p, (char __user *)arg);
1656
1657 if ((we_p->status[0] & STAT_FAILED)) {
1658 switch (rv) {
1659 /**
1660 * EINVAL *after* receive is almost always a padding error or
1661 * length error issued by a coprocessor (not an accelerator).
1662 * We convert this return value to -EGETBUFF which should
1663 * trigger a fallback to software.
1664 */
1665 case -EINVAL:
1666 if (we_p->devtype != PCICA)
1667 rv = -EGETBUFF;
1668 break;
1669 case -ETIMEOUT:
1670 if (z90crypt.mask.st_count > 0)
1671 rv = -ERESTARTSYS; // retry with another
1672 else
1673 rv = -ENODEV; // no cards left
1674 /* fall through to clean up request queue */
1675 case -ERESTARTSYS:
1676 case -ERELEASED:
1677 switch (CHK_RDWRMASK(we_p->status[0])) {
1678 case STAT_WRITTEN:
1679 purge_work_element(we_p);
1680 break;
1681 case STAT_READPEND:
1682 case STAT_NOWORK:
1683 default:
1684 break;
1685 }
1686 break;
1687 default:
1688 we_p->status[0] ^= STAT_FAILED;
1689 break;
1690 }
1691 }
1692 free_page((long)we_p);
1693 return rv;
1694 }
1695
1696 /**
1697 * This function is a little long, but it's really just one large switch
1698 * statement.
1699 */
1700 static long
1701 z90crypt_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1702 {
1703 struct priv_data *private_data_p = filp->private_data;
1704 unsigned char *status;
1705 unsigned char *qdepth;
1706 unsigned int *reqcnt;
1707 struct ica_z90_status *pstat;
1708 int ret, i, loopLim, tempstat;
1709 static int deprecated_msg_count1 = 0;
1710 static int deprecated_msg_count2 = 0;
1711
1712 PDEBUG("filp %p (PID %d), cmd 0x%08X\n", filp, PID(), cmd);
1713 PDEBUG("cmd 0x%08X: dir %s, size 0x%04X, type 0x%02X, nr 0x%02X\n",
1714 cmd,
1715 !_IOC_DIR(cmd) ? "NO"
1716 : ((_IOC_DIR(cmd) == (_IOC_READ|_IOC_WRITE)) ? "RW"
1717 : ((_IOC_DIR(cmd) == _IOC_READ) ? "RD"
1718 : "WR")),
1719 _IOC_SIZE(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd));
1720
1721 if (_IOC_TYPE(cmd) != Z90_IOCTL_MAGIC) {
1722 PRINTK("cmd 0x%08X contains bad magic\n", cmd);
1723 return -ENOTTY;
1724 }
1725
1726 ret = 0;
1727 switch (cmd) {
1728 case ICARSAMODEXPO:
1729 case ICARSACRT:
1730 if (quiesce_z90crypt) {
1731 ret = -EQUIESCE;
1732 break;
1733 }
1734 ret = -ENODEV; // Default if no devices
1735 loopLim = z90crypt.hdware_info->hdware_mask.st_count -
1736 (z90crypt.hdware_info->hdware_mask.disabled_count +
1737 z90crypt.hdware_info->hdware_mask.user_disabled_count);
1738 for (i = 0; i < loopLim; i++) {
1739 ret = z90crypt_rsa(private_data_p, PID(), cmd, arg);
1740 if (ret != -ERESTARTSYS)
1741 break;
1742 }
1743 if (ret == -ERESTARTSYS)
1744 ret = -ENODEV;
1745 break;
1746
1747 case Z90STAT_TOTALCOUNT:
1748 tempstat = get_status_totalcount();
1749 if (copy_to_user((int __user *)arg, &tempstat,sizeof(int)) != 0)
1750 ret = -EFAULT;
1751 break;
1752
1753 case Z90STAT_PCICACOUNT:
1754 tempstat = get_status_PCICAcount();
1755 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1756 ret = -EFAULT;
1757 break;
1758
1759 case Z90STAT_PCICCCOUNT:
1760 tempstat = get_status_PCICCcount();
1761 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1762 ret = -EFAULT;
1763 break;
1764
1765 case Z90STAT_PCIXCCMCL2COUNT:
1766 tempstat = get_status_PCIXCCMCL2count();
1767 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1768 ret = -EFAULT;
1769 break;
1770
1771 case Z90STAT_PCIXCCMCL3COUNT:
1772 tempstat = get_status_PCIXCCMCL3count();
1773 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1774 ret = -EFAULT;
1775 break;
1776
1777 case Z90STAT_CEX2CCOUNT:
1778 tempstat = get_status_CEX2Ccount();
1779 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1780 ret = -EFAULT;
1781 break;
1782
1783 case Z90STAT_REQUESTQ_COUNT:
1784 tempstat = get_status_requestq_count();
1785 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1786 ret = -EFAULT;
1787 break;
1788
1789 case Z90STAT_PENDINGQ_COUNT:
1790 tempstat = get_status_pendingq_count();
1791 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1792 ret = -EFAULT;
1793 break;
1794
1795 case Z90STAT_TOTALOPEN_COUNT:
1796 tempstat = get_status_totalopen_count();
1797 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1798 ret = -EFAULT;
1799 break;
1800
1801 case Z90STAT_DOMAIN_INDEX:
1802 tempstat = get_status_domain_index();
1803 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1804 ret = -EFAULT;
1805 break;
1806
1807 case Z90STAT_STATUS_MASK:
1808 status = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1809 if (!status) {
1810 PRINTK("kmalloc for status failed!\n");
1811 ret = -ENOMEM;
1812 break;
1813 }
1814 get_status_status_mask(status);
1815 if (copy_to_user((char __user *) arg, status, Z90CRYPT_NUM_APS)
1816 != 0)
1817 ret = -EFAULT;
1818 kfree(status);
1819 break;
1820
1821 case Z90STAT_QDEPTH_MASK:
1822 qdepth = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1823 if (!qdepth) {
1824 PRINTK("kmalloc for qdepth failed!\n");
1825 ret = -ENOMEM;
1826 break;
1827 }
1828 get_status_qdepth_mask(qdepth);
1829 if (copy_to_user((char __user *) arg, qdepth, Z90CRYPT_NUM_APS) != 0)
1830 ret = -EFAULT;
1831 kfree(qdepth);
1832 break;
1833
1834 case Z90STAT_PERDEV_REQCNT:
1835 reqcnt = kmalloc(sizeof(int) * Z90CRYPT_NUM_APS, GFP_KERNEL);
1836 if (!reqcnt) {
1837 PRINTK("kmalloc for reqcnt failed!\n");
1838 ret = -ENOMEM;
1839 break;
1840 }
1841 get_status_perdevice_reqcnt(reqcnt);
1842 if (copy_to_user((char __user *) arg, reqcnt,
1843 Z90CRYPT_NUM_APS * sizeof(int)) != 0)
1844 ret = -EFAULT;
1845 kfree(reqcnt);
1846 break;
1847
1848 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1849 case ICAZ90STATUS:
1850 if (deprecated_msg_count1 < 20) {
1851 PRINTK("deprecated call to ioctl (ICAZ90STATUS)!\n");
1852 deprecated_msg_count1++;
1853 if (deprecated_msg_count1 == 20)
1854 PRINTK("No longer issuing messages related to "
1855 "deprecated call to ICAZ90STATUS.\n");
1856 }
1857
1858 pstat = kmalloc(sizeof(struct ica_z90_status), GFP_KERNEL);
1859 if (!pstat) {
1860 PRINTK("kmalloc for pstat failed!\n");
1861 ret = -ENOMEM;
1862 break;
1863 }
1864
1865 pstat->totalcount = get_status_totalcount();
1866 pstat->leedslitecount = get_status_PCICAcount();
1867 pstat->leeds2count = get_status_PCICCcount();
1868 pstat->requestqWaitCount = get_status_requestq_count();
1869 pstat->pendingqWaitCount = get_status_pendingq_count();
1870 pstat->totalOpenCount = get_status_totalopen_count();
1871 pstat->cryptoDomain = get_status_domain_index();
1872 get_status_status_mask(pstat->status);
1873 get_status_qdepth_mask(pstat->qdepth);
1874
1875 if (copy_to_user((struct ica_z90_status __user *) arg, pstat,
1876 sizeof(struct ica_z90_status)) != 0)
1877 ret = -EFAULT;
1878 kfree(pstat);
1879 break;
1880
1881 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1882 case Z90STAT_PCIXCCCOUNT:
1883 if (deprecated_msg_count2 < 20) {
1884 PRINTK("deprecated ioctl (Z90STAT_PCIXCCCOUNT)!\n");
1885 deprecated_msg_count2++;
1886 if (deprecated_msg_count2 == 20)
1887 PRINTK("No longer issuing messages about depre"
1888 "cated ioctl Z90STAT_PCIXCCCOUNT.\n");
1889 }
1890
1891 tempstat = get_status_PCIXCCcount();
1892 if (copy_to_user((int *)arg, &tempstat, sizeof(int)) != 0)
1893 ret = -EFAULT;
1894 break;
1895
1896 case Z90QUIESCE:
1897 if (current->euid != 0) {
1898 PRINTK("QUIESCE fails: euid %d\n",
1899 current->euid);
1900 ret = -EACCES;
1901 } else {
1902 PRINTK("QUIESCE device from PID %d\n", PID());
1903 quiesce_z90crypt = 1;
1904 }
1905 break;
1906
1907 default:
1908 /* user passed an invalid IOCTL number */
1909 PDEBUG("cmd 0x%08X contains invalid ioctl code\n", cmd);
1910 ret = -ENOTTY;
1911 break;
1912 }
1913
1914 return ret;
1915 }
1916
1917 static inline int
1918 sprintcl(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1919 {
1920 int hl, i;
1921
1922 hl = 0;
1923 for (i = 0; i < len; i++)
1924 hl += sprintf(outaddr+hl, "%01x", (unsigned int) addr[i]);
1925 hl += sprintf(outaddr+hl, " ");
1926
1927 return hl;
1928 }
1929
1930 static inline int
1931 sprintrw(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1932 {
1933 int hl, inl, c, cx;
1934
1935 hl = sprintf(outaddr, " ");
1936 inl = 0;
1937 for (c = 0; c < (len / 16); c++) {
1938 hl += sprintcl(outaddr+hl, addr+inl, 16);
1939 inl += 16;
1940 }
1941
1942 cx = len%16;
1943 if (cx) {
1944 hl += sprintcl(outaddr+hl, addr+inl, cx);
1945 inl += cx;
1946 }
1947
1948 hl += sprintf(outaddr+hl, "\n");
1949
1950 return hl;
1951 }
1952
1953 static inline int
1954 sprinthx(unsigned char *title, unsigned char *outaddr,
1955 unsigned char *addr, unsigned int len)
1956 {
1957 int hl, inl, r, rx;
1958
1959 hl = sprintf(outaddr, "\n%s\n", title);
1960 inl = 0;
1961 for (r = 0; r < (len / 64); r++) {
1962 hl += sprintrw(outaddr+hl, addr+inl, 64);
1963 inl += 64;
1964 }
1965 rx = len % 64;
1966 if (rx) {
1967 hl += sprintrw(outaddr+hl, addr+inl, rx);
1968 inl += rx;
1969 }
1970
1971 hl += sprintf(outaddr+hl, "\n");
1972
1973 return hl;
1974 }
1975
1976 static inline int
1977 sprinthx4(unsigned char *title, unsigned char *outaddr,
1978 unsigned int *array, unsigned int len)
1979 {
1980 int hl, r;
1981
1982 hl = sprintf(outaddr, "\n%s\n", title);
1983
1984 for (r = 0; r < len; r++) {
1985 if ((r % 8) == 0)
1986 hl += sprintf(outaddr+hl, " ");
1987 hl += sprintf(outaddr+hl, "%08X ", array[r]);
1988 if ((r % 8) == 7)
1989 hl += sprintf(outaddr+hl, "\n");
1990 }
1991
1992 hl += sprintf(outaddr+hl, "\n");
1993
1994 return hl;
1995 }
1996
1997 static int
1998 z90crypt_status(char *resp_buff, char **start, off_t offset,
1999 int count, int *eof, void *data)
2000 {
2001 unsigned char *workarea;
2002 int len;
2003
2004 /* resp_buff is a page. Use the right half for a work area */
2005 workarea = resp_buff+2000;
2006 len = 0;
2007 len += sprintf(resp_buff+len, "\nz90crypt version: %d.%d.%d\n",
2008 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT);
2009 len += sprintf(resp_buff+len, "Cryptographic domain: %d\n",
2010 get_status_domain_index());
2011 len += sprintf(resp_buff+len, "Total device count: %d\n",
2012 get_status_totalcount());
2013 len += sprintf(resp_buff+len, "PCICA count: %d\n",
2014 get_status_PCICAcount());
2015 len += sprintf(resp_buff+len, "PCICC count: %d\n",
2016 get_status_PCICCcount());
2017 len += sprintf(resp_buff+len, "PCIXCC MCL2 count: %d\n",
2018 get_status_PCIXCCMCL2count());
2019 len += sprintf(resp_buff+len, "PCIXCC MCL3 count: %d\n",
2020 get_status_PCIXCCMCL3count());
2021 len += sprintf(resp_buff+len, "CEX2C count: %d\n",
2022 get_status_CEX2Ccount());
2023 len += sprintf(resp_buff+len, "requestq count: %d\n",
2024 get_status_requestq_count());
2025 len += sprintf(resp_buff+len, "pendingq count: %d\n",
2026 get_status_pendingq_count());
2027 len += sprintf(resp_buff+len, "Total open handles: %d\n\n",
2028 get_status_totalopen_count());
2029 len += sprinthx(
2030 "Online devices: 1: PCICA, 2: PCICC, 3: PCIXCC (MCL2), "
2031 "4: PCIXCC (MCL3), 5: CEX2C",
2032 resp_buff+len,
2033 get_status_status_mask(workarea),
2034 Z90CRYPT_NUM_APS);
2035 len += sprinthx("Waiting work element counts",
2036 resp_buff+len,
2037 get_status_qdepth_mask(workarea),
2038 Z90CRYPT_NUM_APS);
2039 len += sprinthx4(
2040 "Per-device successfully completed request counts",
2041 resp_buff+len,
2042 get_status_perdevice_reqcnt((unsigned int *)workarea),
2043 Z90CRYPT_NUM_APS);
2044 *eof = 1;
2045 memset(workarea, 0, Z90CRYPT_NUM_APS * sizeof(unsigned int));
2046 return len;
2047 }
2048
2049 static inline void
2050 disable_card(int card_index)
2051 {
2052 struct device *devp;
2053
2054 devp = LONG2DEVPTR(card_index);
2055 if (!devp || devp->user_disabled)
2056 return;
2057 devp->user_disabled = 1;
2058 z90crypt.hdware_info->hdware_mask.user_disabled_count++;
2059 if (devp->dev_type == -1)
2060 return;
2061 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count++;
2062 }
2063
2064 static inline void
2065 enable_card(int card_index)
2066 {
2067 struct device *devp;
2068
2069 devp = LONG2DEVPTR(card_index);
2070 if (!devp || !devp->user_disabled)
2071 return;
2072 devp->user_disabled = 0;
2073 z90crypt.hdware_info->hdware_mask.user_disabled_count--;
2074 if (devp->dev_type == -1)
2075 return;
2076 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count--;
2077 }
2078
2079 static int
2080 z90crypt_status_write(struct file *file, const char __user *buffer,
2081 unsigned long count, void *data)
2082 {
2083 int j, eol;
2084 unsigned char *lbuf, *ptr;
2085 unsigned int local_count;
2086
2087 #define LBUFSIZE 1200
2088 lbuf = kmalloc(LBUFSIZE, GFP_KERNEL);
2089 if (!lbuf) {
2090 PRINTK("kmalloc failed!\n");
2091 return 0;
2092 }
2093
2094 if (count <= 0)
2095 return 0;
2096
2097 local_count = UMIN((unsigned int)count, LBUFSIZE-1);
2098
2099 if (copy_from_user(lbuf, buffer, local_count) != 0) {
2100 kfree(lbuf);
2101 return -EFAULT;
2102 }
2103
2104 lbuf[local_count] = '\0';
2105
2106 ptr = strstr(lbuf, "Online devices");
2107 if (ptr == 0) {
2108 PRINTK("Unable to parse data (missing \"Online devices\")\n");
2109 kfree(lbuf);
2110 return count;
2111 }
2112
2113 ptr = strstr(ptr, "\n");
2114 if (ptr == 0) {
2115 PRINTK("Unable to parse data (missing newline after \"Online devices\")\n");
2116 kfree(lbuf);
2117 return count;
2118 }
2119 ptr++;
2120
2121 if (strstr(ptr, "Waiting work element counts") == NULL) {
2122 PRINTK("Unable to parse data (missing \"Waiting work element counts\")\n");
2123 kfree(lbuf);
2124 return count;
2125 }
2126
2127 j = 0;
2128 eol = 0;
2129 while ((j < 64) && (*ptr != '\0')) {
2130 switch (*ptr) {
2131 case '\t':
2132 case ' ':
2133 break;
2134 case '\n':
2135 default:
2136 eol = 1;
2137 break;
2138 case '0': // no device
2139 case '1': // PCICA
2140 case '2': // PCICC
2141 case '3': // PCIXCC_MCL2
2142 case '4': // PCIXCC_MCL3
2143 case '5': // CEX2C
2144 j++;
2145 break;
2146 case 'd':
2147 case 'D':
2148 disable_card(j);
2149 j++;
2150 break;
2151 case 'e':
2152 case 'E':
2153 enable_card(j);
2154 j++;
2155 break;
2156 }
2157 if (eol)
2158 break;
2159 ptr++;
2160 }
2161
2162 kfree(lbuf);
2163 return count;
2164 }
2165
2166 /**
2167 * Functions that run under a timer, with no process id
2168 *
2169 * The task functions:
2170 * z90crypt_reader_task
2171 * helper_send_work
2172 * helper_handle_work_element
2173 * helper_receive_rc
2174 * z90crypt_config_task
2175 * z90crypt_cleanup_task
2176 *
2177 * Helper functions:
2178 * z90crypt_schedule_reader_timer
2179 * z90crypt_schedule_reader_task
2180 * z90crypt_schedule_config_task
2181 * z90crypt_schedule_cleanup_task
2182 */
2183 static inline int
2184 receive_from_crypto_device(int index, unsigned char *psmid, int *buff_len_p,
2185 unsigned char *buff, unsigned char __user **dest_p_p)
2186 {
2187 int dv, rv;
2188 struct device *dev_ptr;
2189 struct caller *caller_p;
2190 struct ica_rsa_modexpo *icaMsg_p;
2191 struct list_head *ptr, *tptr;
2192
2193 memcpy(psmid, NULL_psmid, sizeof(NULL_psmid));
2194
2195 if (z90crypt.terminating)
2196 return REC_FATAL_ERROR;
2197
2198 caller_p = 0;
2199 dev_ptr = z90crypt.device_p[index];
2200 rv = 0;
2201 do {
2202 if (!dev_ptr || dev_ptr->disabled) {
2203 rv = REC_NO_WORK; // a disabled device can't return work
2204 break;
2205 }
2206 if (dev_ptr->dev_self_x != index) {
2207 PRINTKC("Corrupt dev ptr\n");
2208 z90crypt.terminating = 1;
2209 rv = REC_FATAL_ERROR;
2210 break;
2211 }
2212 if (!dev_ptr->dev_resp_l || !dev_ptr->dev_resp_p) {
2213 dv = DEV_REC_EXCEPTION;
2214 PRINTK("dev_resp_l = %d, dev_resp_p = %p\n",
2215 dev_ptr->dev_resp_l, dev_ptr->dev_resp_p);
2216 } else {
2217 PDEBUG("Dequeue called for device %d\n", index);
2218 dv = receive_from_AP(index, z90crypt.cdx,
2219 dev_ptr->dev_resp_l,
2220 dev_ptr->dev_resp_p, psmid);
2221 }
2222 switch (dv) {
2223 case DEV_REC_EXCEPTION:
2224 rv = REC_FATAL_ERROR;
2225 z90crypt.terminating = 1;
2226 PRINTKC("Exception in receive from device %d\n",
2227 index);
2228 break;
2229 case DEV_ONLINE:
2230 rv = 0;
2231 break;
2232 case DEV_EMPTY:
2233 rv = REC_EMPTY;
2234 break;
2235 case DEV_NO_WORK:
2236 rv = REC_NO_WORK;
2237 break;
2238 case DEV_BAD_MESSAGE:
2239 case DEV_GONE:
2240 case REC_HARDWAR_ERR:
2241 default:
2242 rv = REC_NO_RESPONSE;
2243 break;
2244 }
2245 if (rv)
2246 break;
2247 if (dev_ptr->dev_caller_count <= 0) {
2248 rv = REC_USER_GONE;
2249 break;
2250 }
2251
2252 list_for_each_safe(ptr, tptr, &dev_ptr->dev_caller_list) {
2253 caller_p = list_entry(ptr, struct caller, caller_liste);
2254 if (!memcmp(caller_p->caller_id, psmid,
2255 sizeof(caller_p->caller_id))) {
2256 if (!list_empty(&caller_p->caller_liste)) {
2257 list_del_init(ptr);
2258 dev_ptr->dev_caller_count--;
2259 break;
2260 }
2261 }
2262 caller_p = 0;
2263 }
2264 if (!caller_p) {
2265 PRINTKW("Unable to locate PSMID %02X%02X%02X%02X%02X"
2266 "%02X%02X%02X in device list\n",
2267 psmid[0], psmid[1], psmid[2], psmid[3],
2268 psmid[4], psmid[5], psmid[6], psmid[7]);
2269 rv = REC_USER_GONE;
2270 break;
2271 }
2272
2273 PDEBUG("caller_p after successful receive: %p\n", caller_p);
2274 rv = convert_response(dev_ptr->dev_resp_p,
2275 caller_p->caller_buf_p, buff_len_p, buff);
2276 switch (rv) {
2277 case REC_USE_PCICA:
2278 break;
2279 case REC_OPERAND_INV:
2280 case REC_OPERAND_SIZE:
2281 case REC_EVEN_MOD:
2282 case REC_INVALID_PAD:
2283 PDEBUG("device %d: 'user error' %d\n", index, rv);
2284 break;
2285 case WRONG_DEVICE_TYPE:
2286 case REC_HARDWAR_ERR:
2287 case REC_BAD_MESSAGE:
2288 PRINTKW("device %d: hardware error %d\n", index, rv);
2289 rv = REC_NO_RESPONSE;
2290 break;
2291 default:
2292 PDEBUG("device %d: rv = %d\n", index, rv);
2293 break;
2294 }
2295 } while (0);
2296
2297 switch (rv) {
2298 case 0:
2299 PDEBUG("Successful receive from device %d\n", index);
2300 icaMsg_p = (struct ica_rsa_modexpo *)caller_p->caller_buf_p;
2301 *dest_p_p = icaMsg_p->outputdata;
2302 if (*buff_len_p == 0)
2303 PRINTK("Zero *buff_len_p\n");
2304 break;
2305 case REC_NO_RESPONSE:
2306 PRINTKW("Removing device %d from availability\n", index);
2307 remove_device(dev_ptr);
2308 break;
2309 }
2310
2311 if (caller_p)
2312 unbuild_caller(dev_ptr, caller_p);
2313
2314 return rv;
2315 }
2316
2317 static inline void
2318 helper_send_work(int index)
2319 {
2320 struct work_element *rq_p;
2321 int rv;
2322
2323 if (list_empty(&request_list))
2324 return;
2325 requestq_count--;
2326 rq_p = list_entry(request_list.next, struct work_element, liste);
2327 list_del_init(&rq_p->liste);
2328 rq_p->audit[1] |= FP_REMREQUEST;
2329 if (rq_p->devtype == SHRT2DEVPTR(index)->dev_type) {
2330 rq_p->devindex = SHRT2LONG(index);
2331 rv = send_to_crypto_device(rq_p);
2332 if (rv == 0) {
2333 rq_p->requestsent = jiffies;
2334 rq_p->audit[0] |= FP_SENT;
2335 list_add_tail(&rq_p->liste, &pending_list);
2336 ++pendingq_count;
2337 rq_p->audit[0] |= FP_PENDING;
2338 } else {
2339 switch (rv) {
2340 case REC_OPERAND_INV:
2341 case REC_OPERAND_SIZE:
2342 case REC_EVEN_MOD:
2343 case REC_INVALID_PAD:
2344 rq_p->retcode = -EINVAL;
2345 break;
2346 case SEN_NOT_AVAIL:
2347 case SEN_RETRY:
2348 case REC_NO_RESPONSE:
2349 default:
2350 if (z90crypt.mask.st_count > 1)
2351 rq_p->retcode =
2352 -ERESTARTSYS;
2353 else
2354 rq_p->retcode = -ENODEV;
2355 break;
2356 }
2357 rq_p->status[0] |= STAT_FAILED;
2358 rq_p->audit[1] |= FP_AWAKENING;
2359 atomic_set(&rq_p->alarmrung, 1);
2360 wake_up(&rq_p->waitq);
2361 }
2362 } else {
2363 if (z90crypt.mask.st_count > 1)
2364 rq_p->retcode = -ERESTARTSYS;
2365 else
2366 rq_p->retcode = -ENODEV;
2367 rq_p->status[0] |= STAT_FAILED;
2368 rq_p->audit[1] |= FP_AWAKENING;
2369 atomic_set(&rq_p->alarmrung, 1);
2370 wake_up(&rq_p->waitq);
2371 }
2372 }
2373
2374 static inline void
2375 helper_handle_work_element(int index, unsigned char psmid[8], int rc,
2376 int buff_len, unsigned char *buff,
2377 unsigned char __user *resp_addr)
2378 {
2379 struct work_element *pq_p;
2380 struct list_head *lptr, *tptr;
2381
2382 pq_p = 0;
2383 list_for_each_safe(lptr, tptr, &pending_list) {
2384 pq_p = list_entry(lptr, struct work_element, liste);
2385 if (!memcmp(pq_p->caller_id, psmid, sizeof(pq_p->caller_id))) {
2386 list_del_init(lptr);
2387 pendingq_count--;
2388 pq_p->audit[1] |= FP_NOTPENDING;
2389 break;
2390 }
2391 pq_p = 0;
2392 }
2393
2394 if (!pq_p) {
2395 PRINTK("device %d has work but no caller exists on pending Q\n",
2396 SHRT2LONG(index));
2397 return;
2398 }
2399
2400 switch (rc) {
2401 case 0:
2402 pq_p->resp_buff_size = buff_len;
2403 pq_p->audit[1] |= FP_RESPSIZESET;
2404 if (buff_len) {
2405 pq_p->resp_addr = resp_addr;
2406 pq_p->audit[1] |= FP_RESPADDRCOPIED;
2407 memcpy(pq_p->resp_buff, buff, buff_len);
2408 pq_p->audit[1] |= FP_RESPBUFFCOPIED;
2409 }
2410 break;
2411 case REC_OPERAND_INV:
2412 case REC_OPERAND_SIZE:
2413 case REC_EVEN_MOD:
2414 case REC_INVALID_PAD:
2415 PDEBUG("-EINVAL after application error %d\n", rc);
2416 pq_p->retcode = -EINVAL;
2417 pq_p->status[0] |= STAT_FAILED;
2418 break;
2419 case REC_USE_PCICA:
2420 pq_p->retcode = -ERESTARTSYS;
2421 pq_p->status[0] |= STAT_FAILED;
2422 break;
2423 case REC_NO_RESPONSE:
2424 default:
2425 if (z90crypt.mask.st_count > 1)
2426 pq_p->retcode = -ERESTARTSYS;
2427 else
2428 pq_p->retcode = -ENODEV;
2429 pq_p->status[0] |= STAT_FAILED;
2430 break;
2431 }
2432 if ((pq_p->status[0] != STAT_FAILED) || (pq_p->retcode != -ERELEASED)) {
2433 pq_p->audit[1] |= FP_AWAKENING;
2434 atomic_set(&pq_p->alarmrung, 1);
2435 wake_up(&pq_p->waitq);
2436 }
2437 }
2438
2439 /**
2440 * return TRUE if the work element should be removed from the queue
2441 */
2442 static inline int
2443 helper_receive_rc(int index, int *rc_p)
2444 {
2445 switch (*rc_p) {
2446 case 0:
2447 case REC_OPERAND_INV:
2448 case REC_OPERAND_SIZE:
2449 case REC_EVEN_MOD:
2450 case REC_INVALID_PAD:
2451 case REC_USE_PCICA:
2452 break;
2453
2454 case REC_BUSY:
2455 case REC_NO_WORK:
2456 case REC_EMPTY:
2457 case REC_RETRY_DEV:
2458 case REC_FATAL_ERROR:
2459 return 0;
2460
2461 case REC_NO_RESPONSE:
2462 break;
2463
2464 default:
2465 PRINTK("rc %d, device %d converted to REC_NO_RESPONSE\n",
2466 *rc_p, SHRT2LONG(index));
2467 *rc_p = REC_NO_RESPONSE;
2468 break;
2469 }
2470 return 1;
2471 }
2472
2473 static inline void
2474 z90crypt_schedule_reader_timer(void)
2475 {
2476 if (timer_pending(&reader_timer))
2477 return;
2478 if (mod_timer(&reader_timer, jiffies+(READERTIME*HZ/1000)) != 0)
2479 PRINTK("Timer pending while modifying reader timer\n");
2480 }
2481
2482 static void
2483 z90crypt_reader_task(unsigned long ptr)
2484 {
2485 int workavail, index, rc, buff_len;
2486 unsigned char psmid[8];
2487 unsigned char __user *resp_addr;
2488 static unsigned char buff[1024];
2489
2490 /**
2491 * we use workavail = 2 to ensure 2 passes with nothing dequeued before
2492 * exiting the loop. If (pendingq_count+requestq_count) == 0 after the
2493 * loop, there is no work remaining on the queues.
2494 */
2495 resp_addr = 0;
2496 workavail = 2;
2497 buff_len = 0;
2498 while (workavail) {
2499 workavail--;
2500 rc = 0;
2501 spin_lock_irq(&queuespinlock);
2502 memset(buff, 0x00, sizeof(buff));
2503
2504 /* Dequeue once from each device in round robin. */
2505 for (index = 0; index < z90crypt.mask.st_count; index++) {
2506 PDEBUG("About to receive.\n");
2507 rc = receive_from_crypto_device(SHRT2LONG(index),
2508 psmid,
2509 &buff_len,
2510 buff,
2511 &resp_addr);
2512 PDEBUG("Dequeued: rc = %d.\n", rc);
2513
2514 if (helper_receive_rc(index, &rc)) {
2515 if (rc != REC_NO_RESPONSE) {
2516 helper_send_work(index);
2517 workavail = 2;
2518 }
2519
2520 helper_handle_work_element(index, psmid, rc,
2521 buff_len, buff,
2522 resp_addr);
2523 }
2524
2525 if (rc == REC_FATAL_ERROR)
2526 PRINTKW("REC_FATAL_ERROR from device %d!\n",
2527 SHRT2LONG(index));
2528 }
2529 spin_unlock_irq(&queuespinlock);
2530 }
2531
2532 if (pendingq_count + requestq_count)
2533 z90crypt_schedule_reader_timer();
2534 }
2535
2536 static inline void
2537 z90crypt_schedule_config_task(unsigned int expiration)
2538 {
2539 if (timer_pending(&config_timer))
2540 return;
2541 if (mod_timer(&config_timer, jiffies+(expiration*HZ)) != 0)
2542 PRINTK("Timer pending while modifying config timer\n");
2543 }
2544
2545 static void
2546 z90crypt_config_task(unsigned long ptr)
2547 {
2548 int rc;
2549
2550 PDEBUG("jiffies %ld\n", jiffies);
2551
2552 if ((rc = refresh_z90crypt(&z90crypt.cdx)))
2553 PRINTK("Error %d detected in refresh_z90crypt.\n", rc);
2554 /* If return was fatal, don't bother reconfiguring */
2555 if ((rc != TSQ_FATAL_ERROR) && (rc != RSQ_FATAL_ERROR))
2556 z90crypt_schedule_config_task(CONFIGTIME);
2557 }
2558
2559 static inline void
2560 z90crypt_schedule_cleanup_task(void)
2561 {
2562 if (timer_pending(&cleanup_timer))
2563 return;
2564 if (mod_timer(&cleanup_timer, jiffies+(CLEANUPTIME*HZ)) != 0)
2565 PRINTK("Timer pending while modifying cleanup timer\n");
2566 }
2567
2568 static inline void
2569 helper_drain_queues(void)
2570 {
2571 struct work_element *pq_p;
2572 struct list_head *lptr, *tptr;
2573
2574 list_for_each_safe(lptr, tptr, &pending_list) {
2575 pq_p = list_entry(lptr, struct work_element, liste);
2576 pq_p->retcode = -ENODEV;
2577 pq_p->status[0] |= STAT_FAILED;
2578 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2579 (struct caller *)pq_p->requestptr);
2580 list_del_init(lptr);
2581 pendingq_count--;
2582 pq_p->audit[1] |= FP_NOTPENDING;
2583 pq_p->audit[1] |= FP_AWAKENING;
2584 atomic_set(&pq_p->alarmrung, 1);
2585 wake_up(&pq_p->waitq);
2586 }
2587
2588 list_for_each_safe(lptr, tptr, &request_list) {
2589 pq_p = list_entry(lptr, struct work_element, liste);
2590 pq_p->retcode = -ENODEV;
2591 pq_p->status[0] |= STAT_FAILED;
2592 list_del_init(lptr);
2593 requestq_count--;
2594 pq_p->audit[1] |= FP_REMREQUEST;
2595 pq_p->audit[1] |= FP_AWAKENING;
2596 atomic_set(&pq_p->alarmrung, 1);
2597 wake_up(&pq_p->waitq);
2598 }
2599 }
2600
2601 static inline void
2602 helper_timeout_requests(void)
2603 {
2604 struct work_element *pq_p;
2605 struct list_head *lptr, *tptr;
2606 long timelimit;
2607
2608 timelimit = jiffies - (CLEANUPTIME * HZ);
2609 /* The list is in strict chronological order */
2610 list_for_each_safe(lptr, tptr, &pending_list) {
2611 pq_p = list_entry(lptr, struct work_element, liste);
2612 if (pq_p->requestsent >= timelimit)
2613 break;
2614 PRINTKW("Purging(PQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2615 ((struct caller *)pq_p->requestptr)->caller_id[0],
2616 ((struct caller *)pq_p->requestptr)->caller_id[1],
2617 ((struct caller *)pq_p->requestptr)->caller_id[2],
2618 ((struct caller *)pq_p->requestptr)->caller_id[3],
2619 ((struct caller *)pq_p->requestptr)->caller_id[4],
2620 ((struct caller *)pq_p->requestptr)->caller_id[5],
2621 ((struct caller *)pq_p->requestptr)->caller_id[6],
2622 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2623 pq_p->retcode = -ETIMEOUT;
2624 pq_p->status[0] |= STAT_FAILED;
2625 /* get this off any caller queue it may be on */
2626 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2627 (struct caller *) pq_p->requestptr);
2628 list_del_init(lptr);
2629 pendingq_count--;
2630 pq_p->audit[1] |= FP_TIMEDOUT;
2631 pq_p->audit[1] |= FP_NOTPENDING;
2632 pq_p->audit[1] |= FP_AWAKENING;
2633 atomic_set(&pq_p->alarmrung, 1);
2634 wake_up(&pq_p->waitq);
2635 }
2636
2637 /**
2638 * If pending count is zero, items left on the request queue may
2639 * never be processed.
2640 */
2641 if (pendingq_count <= 0) {
2642 list_for_each_safe(lptr, tptr, &request_list) {
2643 pq_p = list_entry(lptr, struct work_element, liste);
2644 if (pq_p->requestsent >= timelimit)
2645 break;
2646 PRINTKW("Purging(RQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2647 ((struct caller *)pq_p->requestptr)->caller_id[0],
2648 ((struct caller *)pq_p->requestptr)->caller_id[1],
2649 ((struct caller *)pq_p->requestptr)->caller_id[2],
2650 ((struct caller *)pq_p->requestptr)->caller_id[3],
2651 ((struct caller *)pq_p->requestptr)->caller_id[4],
2652 ((struct caller *)pq_p->requestptr)->caller_id[5],
2653 ((struct caller *)pq_p->requestptr)->caller_id[6],
2654 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2655 pq_p->retcode = -ETIMEOUT;
2656 pq_p->status[0] |= STAT_FAILED;
2657 list_del_init(lptr);
2658 requestq_count--;
2659 pq_p->audit[1] |= FP_TIMEDOUT;
2660 pq_p->audit[1] |= FP_REMREQUEST;
2661 pq_p->audit[1] |= FP_AWAKENING;
2662 atomic_set(&pq_p->alarmrung, 1);
2663 wake_up(&pq_p->waitq);
2664 }
2665 }
2666 }
2667
2668 static void
2669 z90crypt_cleanup_task(unsigned long ptr)
2670 {
2671 PDEBUG("jiffies %ld\n", jiffies);
2672 spin_lock_irq(&queuespinlock);
2673 if (z90crypt.mask.st_count <= 0) // no devices!
2674 helper_drain_queues();
2675 else
2676 helper_timeout_requests();
2677 spin_unlock_irq(&queuespinlock);
2678 z90crypt_schedule_cleanup_task();
2679 }
2680
2681 static void
2682 z90crypt_schedule_reader_task(unsigned long ptr)
2683 {
2684 tasklet_schedule(&reader_tasklet);
2685 }
2686
2687 /**
2688 * Lowlevel Functions:
2689 *
2690 * create_z90crypt: creates and initializes basic data structures
2691 * refresh_z90crypt: re-initializes basic data structures
2692 * find_crypto_devices: returns a count and mask of hardware status
2693 * create_crypto_device: builds the descriptor for a device
2694 * destroy_crypto_device: unallocates the descriptor for a device
2695 * destroy_z90crypt: drains all work, unallocates structs
2696 */
2697
2698 /**
2699 * build the z90crypt root structure using the given domain index
2700 */
2701 static int
2702 create_z90crypt(int *cdx_p)
2703 {
2704 struct hdware_block *hdware_blk_p;
2705
2706 memset(&z90crypt, 0x00, sizeof(struct z90crypt));
2707 z90crypt.domain_established = 0;
2708 z90crypt.len = sizeof(struct z90crypt);
2709 z90crypt.max_count = Z90CRYPT_NUM_DEVS;
2710 z90crypt.cdx = *cdx_p;
2711
2712 hdware_blk_p = (struct hdware_block *)
2713 kmalloc(sizeof(struct hdware_block), GFP_ATOMIC);
2714 if (!hdware_blk_p) {
2715 PDEBUG("kmalloc for hardware block failed\n");
2716 return ENOMEM;
2717 }
2718 memset(hdware_blk_p, 0x00, sizeof(struct hdware_block));
2719 z90crypt.hdware_info = hdware_blk_p;
2720
2721 return 0;
2722 }
2723
2724 static inline int
2725 helper_scan_devices(int cdx_array[16], int *cdx_p, int *correct_cdx_found)
2726 {
2727 enum hdstat hd_stat;
2728 int q_depth, dev_type;
2729 int indx, chkdom, numdomains;
2730
2731 q_depth = dev_type = numdomains = 0;
2732 for (chkdom = 0; chkdom <= 15; cdx_array[chkdom++] = -1);
2733 for (indx = 0; indx < z90crypt.max_count; indx++) {
2734 hd_stat = HD_NOT_THERE;
2735 numdomains = 0;
2736 for (chkdom = 0; chkdom <= 15; chkdom++) {
2737 hd_stat = query_online(indx, chkdom, MAX_RESET,
2738 &q_depth, &dev_type);
2739 if (hd_stat == HD_TSQ_EXCEPTION) {
2740 z90crypt.terminating = 1;
2741 PRINTKC("exception taken!\n");
2742 break;
2743 }
2744 if (hd_stat == HD_ONLINE) {
2745 cdx_array[numdomains++] = chkdom;
2746 if (*cdx_p == chkdom) {
2747 *correct_cdx_found = 1;
2748 break;
2749 }
2750 }
2751 }
2752 if ((*correct_cdx_found == 1) || (numdomains != 0))
2753 break;
2754 if (z90crypt.terminating)
2755 break;
2756 }
2757 return numdomains;
2758 }
2759
2760 static inline int
2761 probe_crypto_domain(int *cdx_p)
2762 {
2763 int cdx_array[16];
2764 char cdx_array_text[53], temp[5];
2765 int correct_cdx_found, numdomains;
2766
2767 correct_cdx_found = 0;
2768 numdomains = helper_scan_devices(cdx_array, cdx_p, &correct_cdx_found);
2769
2770 if (z90crypt.terminating)
2771 return TSQ_FATAL_ERROR;
2772
2773 if (correct_cdx_found)
2774 return 0;
2775
2776 if (numdomains == 0) {
2777 PRINTKW("Unable to find crypto domain: No devices found\n");
2778 return Z90C_NO_DEVICES;
2779 }
2780
2781 if (numdomains == 1) {
2782 if (*cdx_p == -1) {
2783 *cdx_p = cdx_array[0];
2784 return 0;
2785 }
2786 PRINTKW("incorrect domain: specified = %d, found = %d\n",
2787 *cdx_p, cdx_array[0]);
2788 return Z90C_INCORRECT_DOMAIN;
2789 }
2790
2791 numdomains--;
2792 sprintf(cdx_array_text, "%d", cdx_array[numdomains]);
2793 while (numdomains) {
2794 numdomains--;
2795 sprintf(temp, ", %d", cdx_array[numdomains]);
2796 strcat(cdx_array_text, temp);
2797 }
2798
2799 PRINTKW("ambiguous domain detected: specified = %d, found array = %s\n",
2800 *cdx_p, cdx_array_text);
2801 return Z90C_AMBIGUOUS_DOMAIN;
2802 }
2803
2804 static int
2805 refresh_z90crypt(int *cdx_p)
2806 {
2807 int i, j, indx, rv;
2808 static struct status local_mask;
2809 struct device *devPtr;
2810 unsigned char oldStat, newStat;
2811 int return_unchanged;
2812
2813 if (z90crypt.len != sizeof(z90crypt))
2814 return ENOTINIT;
2815 if (z90crypt.terminating)
2816 return TSQ_FATAL_ERROR;
2817 rv = 0;
2818 if (!z90crypt.hdware_info->hdware_mask.st_count &&
2819 !z90crypt.domain_established) {
2820 rv = probe_crypto_domain(cdx_p);
2821 if (z90crypt.terminating)
2822 return TSQ_FATAL_ERROR;
2823 if (rv == Z90C_NO_DEVICES)
2824 return 0; // try later
2825 if (rv)
2826 return rv;
2827 z90crypt.cdx = *cdx_p;
2828 z90crypt.domain_established = 1;
2829 }
2830 rv = find_crypto_devices(&local_mask);
2831 if (rv) {
2832 PRINTK("find crypto devices returned %d\n", rv);
2833 return rv;
2834 }
2835 if (!memcmp(&local_mask, &z90crypt.hdware_info->hdware_mask,
2836 sizeof(struct status))) {
2837 return_unchanged = 1;
2838 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++) {
2839 /**
2840 * Check for disabled cards. If any device is marked
2841 * disabled, destroy it.
2842 */
2843 for (j = 0;
2844 j < z90crypt.hdware_info->type_mask[i].st_count;
2845 j++) {
2846 indx = z90crypt.hdware_info->type_x_addr[i].
2847 device_index[j];
2848 devPtr = z90crypt.device_p[indx];
2849 if (devPtr && devPtr->disabled) {
2850 local_mask.st_mask[indx] = HD_NOT_THERE;
2851 return_unchanged = 0;
2852 }
2853 }
2854 }
2855 if (return_unchanged == 1)
2856 return 0;
2857 }
2858
2859 spin_lock_irq(&queuespinlock);
2860 for (i = 0; i < z90crypt.max_count; i++) {
2861 oldStat = z90crypt.hdware_info->hdware_mask.st_mask[i];
2862 newStat = local_mask.st_mask[i];
2863 if ((oldStat == HD_ONLINE) && (newStat != HD_ONLINE))
2864 destroy_crypto_device(i);
2865 else if ((oldStat != HD_ONLINE) && (newStat == HD_ONLINE)) {
2866 rv = create_crypto_device(i);
2867 if (rv >= REC_FATAL_ERROR)
2868 return rv;
2869 if (rv != 0) {
2870 local_mask.st_mask[i] = HD_NOT_THERE;
2871 local_mask.st_count--;
2872 }
2873 }
2874 }
2875 memcpy(z90crypt.hdware_info->hdware_mask.st_mask, local_mask.st_mask,
2876 sizeof(local_mask.st_mask));
2877 z90crypt.hdware_info->hdware_mask.st_count = local_mask.st_count;
2878 z90crypt.hdware_info->hdware_mask.disabled_count =
2879 local_mask.disabled_count;
2880 refresh_index_array(&z90crypt.mask, &z90crypt.overall_device_x);
2881 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++)
2882 refresh_index_array(&(z90crypt.hdware_info->type_mask[i]),
2883 &(z90crypt.hdware_info->type_x_addr[i]));
2884 spin_unlock_irq(&queuespinlock);
2885
2886 return rv;
2887 }
2888
2889 static int
2890 find_crypto_devices(struct status *deviceMask)
2891 {
2892 int i, q_depth, dev_type;
2893 enum hdstat hd_stat;
2894
2895 deviceMask->st_count = 0;
2896 deviceMask->disabled_count = 0;
2897 deviceMask->user_disabled_count = 0;
2898
2899 for (i = 0; i < z90crypt.max_count; i++) {
2900 hd_stat = query_online(i, z90crypt.cdx, MAX_RESET, &q_depth,
2901 &dev_type);
2902 if (hd_stat == HD_TSQ_EXCEPTION) {
2903 z90crypt.terminating = 1;
2904 PRINTKC("Exception during probe for crypto devices\n");
2905 return TSQ_FATAL_ERROR;
2906 }
2907 deviceMask->st_mask[i] = hd_stat;
2908 if (hd_stat == HD_ONLINE) {
2909 PDEBUG("Got an online crypto!: %d\n", i);
2910 PDEBUG("Got a queue depth of %d\n", q_depth);
2911 PDEBUG("Got a device type of %d\n", dev_type);
2912 if (q_depth <= 0)
2913 return TSQ_FATAL_ERROR;
2914 deviceMask->st_count++;
2915 z90crypt.q_depth_array[i] = q_depth;
2916 z90crypt.dev_type_array[i] = dev_type;
2917 }
2918 }
2919
2920 return 0;
2921 }
2922
2923 static int
2924 refresh_index_array(struct status *status_str, struct device_x *index_array)
2925 {
2926 int i, count;
2927 enum devstat stat;
2928
2929 i = -1;
2930 count = 0;
2931 do {
2932 stat = status_str->st_mask[++i];
2933 if (stat == DEV_ONLINE)
2934 index_array->device_index[count++] = i;
2935 } while ((i < Z90CRYPT_NUM_DEVS) && (count < status_str->st_count));
2936
2937 return count;
2938 }
2939
2940 static int
2941 create_crypto_device(int index)
2942 {
2943 int rv, devstat, total_size;
2944 struct device *dev_ptr;
2945 struct status *type_str_p;
2946 int deviceType;
2947
2948 dev_ptr = z90crypt.device_p[index];
2949 if (!dev_ptr) {
2950 total_size = sizeof(struct device) +
2951 z90crypt.q_depth_array[index] * sizeof(int);
2952
2953 dev_ptr = (struct device *) kmalloc(total_size, GFP_ATOMIC);
2954 if (!dev_ptr) {
2955 PRINTK("kmalloc device %d failed\n", index);
2956 return ENOMEM;
2957 }
2958 memset(dev_ptr, 0, total_size);
2959 dev_ptr->dev_resp_p = kmalloc(MAX_RESPONSE_SIZE, GFP_ATOMIC);
2960 if (!dev_ptr->dev_resp_p) {
2961 kfree(dev_ptr);
2962 PRINTK("kmalloc device %d rec buffer failed\n", index);
2963 return ENOMEM;
2964 }
2965 dev_ptr->dev_resp_l = MAX_RESPONSE_SIZE;
2966 INIT_LIST_HEAD(&(dev_ptr->dev_caller_list));
2967 }
2968
2969 devstat = reset_device(index, z90crypt.cdx, MAX_RESET);
2970 if (devstat == DEV_RSQ_EXCEPTION) {
2971 PRINTK("exception during reset device %d\n", index);
2972 kfree(dev_ptr->dev_resp_p);
2973 kfree(dev_ptr);
2974 return RSQ_FATAL_ERROR;
2975 }
2976 if (devstat == DEV_ONLINE) {
2977 dev_ptr->dev_self_x = index;
2978 dev_ptr->dev_type = z90crypt.dev_type_array[index];
2979 if (dev_ptr->dev_type == NILDEV) {
2980 rv = probe_device_type(dev_ptr);
2981 if (rv) {
2982 PRINTK("rv = %d from probe_device_type %d\n",
2983 rv, index);
2984 kfree(dev_ptr->dev_resp_p);
2985 kfree(dev_ptr);
2986 return rv;
2987 }
2988 }
2989 if (dev_ptr->dev_type == PCIXCC_UNK) {
2990 rv = probe_PCIXCC_type(dev_ptr);
2991 if (rv) {
2992 PRINTK("rv = %d from probe_PCIXCC_type %d\n",
2993 rv, index);
2994 kfree(dev_ptr->dev_resp_p);
2995 kfree(dev_ptr);
2996 return rv;
2997 }
2998 }
2999 deviceType = dev_ptr->dev_type;
3000 z90crypt.dev_type_array[index] = deviceType;
3001 if (deviceType == PCICA)
3002 z90crypt.hdware_info->device_type_array[index] = 1;
3003 else if (deviceType == PCICC)
3004 z90crypt.hdware_info->device_type_array[index] = 2;
3005 else if (deviceType == PCIXCC_MCL2)
3006 z90crypt.hdware_info->device_type_array[index] = 3;
3007 else if (deviceType == PCIXCC_MCL3)
3008 z90crypt.hdware_info->device_type_array[index] = 4;
3009 else if (deviceType == CEX2C)
3010 z90crypt.hdware_info->device_type_array[index] = 5;
3011 else
3012 z90crypt.hdware_info->device_type_array[index] = -1;
3013 }
3014
3015 /**
3016 * 'q_depth' returned by the hardware is one less than
3017 * the actual depth
3018 */
3019 dev_ptr->dev_q_depth = z90crypt.q_depth_array[index];
3020 dev_ptr->dev_type = z90crypt.dev_type_array[index];
3021 dev_ptr->dev_stat = devstat;
3022 dev_ptr->disabled = 0;
3023 z90crypt.device_p[index] = dev_ptr;
3024
3025 if (devstat == DEV_ONLINE) {
3026 if (z90crypt.mask.st_mask[index] != DEV_ONLINE) {
3027 z90crypt.mask.st_mask[index] = DEV_ONLINE;
3028 z90crypt.mask.st_count++;
3029 }
3030 deviceType = dev_ptr->dev_type;
3031 type_str_p = &z90crypt.hdware_info->type_mask[deviceType];
3032 if (type_str_p->st_mask[index] != DEV_ONLINE) {
3033 type_str_p->st_mask[index] = DEV_ONLINE;
3034 type_str_p->st_count++;
3035 }
3036 }
3037
3038 return 0;
3039 }
3040
3041 static int
3042 destroy_crypto_device(int index)
3043 {
3044 struct device *dev_ptr;
3045 int t, disabledFlag;
3046
3047 dev_ptr = z90crypt.device_p[index];
3048
3049 /* remember device type; get rid of device struct */
3050 if (dev_ptr) {
3051 disabledFlag = dev_ptr->disabled;
3052 t = dev_ptr->dev_type;
3053 kfree(dev_ptr->dev_resp_p);
3054 kfree(dev_ptr);
3055 } else {
3056 disabledFlag = 0;
3057 t = -1;
3058 }
3059 z90crypt.device_p[index] = 0;
3060
3061 /* if the type is valid, remove the device from the type_mask */
3062 if ((t != -1) && z90crypt.hdware_info->type_mask[t].st_mask[index]) {
3063 z90crypt.hdware_info->type_mask[t].st_mask[index] = 0x00;
3064 z90crypt.hdware_info->type_mask[t].st_count--;
3065 if (disabledFlag == 1)
3066 z90crypt.hdware_info->type_mask[t].disabled_count--;
3067 }
3068 if (z90crypt.mask.st_mask[index] != DEV_GONE) {
3069 z90crypt.mask.st_mask[index] = DEV_GONE;
3070 z90crypt.mask.st_count--;
3071 }
3072 z90crypt.hdware_info->device_type_array[index] = 0;
3073
3074 return 0;
3075 }
3076
3077 static void
3078 destroy_z90crypt(void)
3079 {
3080 int i;
3081
3082 for (i = 0; i < z90crypt.max_count; i++)
3083 if (z90crypt.device_p[i])
3084 destroy_crypto_device(i);
3085 kfree(z90crypt.hdware_info);
3086 memset((void *)&z90crypt, 0, sizeof(z90crypt));
3087 }
3088
3089 static unsigned char static_testmsg[384] = {
3090 0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x00,0x06,0x00,0x00,
3091 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x58,
3092 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x43,0x43,
3093 0x41,0x2d,0x41,0x50,0x50,0x4c,0x20,0x20,0x20,0x01,0x01,0x01,0x00,0x00,0x00,0x00,
3094 0x50,0x4b,0x00,0x00,0x00,0x00,0x01,0x1c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3095 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3096 0x00,0x00,0x00,0x00,0x70,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x32,
3097 0x01,0x00,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3098 0xb8,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3099 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3100 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3101 0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3102 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x49,0x43,0x53,0x46,
3103 0x20,0x20,0x20,0x20,0x50,0x4b,0x0a,0x00,0x50,0x4b,0x43,0x53,0x2d,0x31,0x2e,0x32,
3104 0x37,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,
3105 0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,
3106 0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,
3107 0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x5d,0x00,0x5b,0x00,0x77,0x88,0x1e,0x00,0x00,
3108 0x57,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x4f,0x00,0x00,0x00,0x03,0x02,0x00,0x00,
3109 0x40,0x01,0x00,0x01,0xce,0x02,0x68,0x2d,0x5f,0xa9,0xde,0x0c,0xf6,0xd2,0x7b,0x58,
3110 0x4b,0xf9,0x28,0x68,0x3d,0xb4,0xf4,0xef,0x78,0xd5,0xbe,0x66,0x63,0x42,0xef,0xf8,
3111 0xfd,0xa4,0xf8,0xb0,0x8e,0x29,0xc2,0xc9,0x2e,0xd8,0x45,0xb8,0x53,0x8c,0x6f,0x4e,
3112 0x72,0x8f,0x6c,0x04,0x9c,0x88,0xfc,0x1e,0xc5,0x83,0x55,0x57,0xf7,0xdd,0xfd,0x4f,
3113 0x11,0x36,0x95,0x5d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
3114 };
3115
3116 static int
3117 probe_device_type(struct device *devPtr)
3118 {
3119 int rv, dv, i, index, length;
3120 unsigned char psmid[8];
3121 static unsigned char loc_testmsg[sizeof(static_testmsg)];
3122
3123 index = devPtr->dev_self_x;
3124 rv = 0;
3125 do {
3126 memcpy(loc_testmsg, static_testmsg, sizeof(static_testmsg));
3127 length = sizeof(static_testmsg) - 24;
3128 /* the -24 allows for the header */
3129 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3130 if (dv) {
3131 PDEBUG("dv returned by send during probe: %d\n", dv);
3132 if (dv == DEV_SEN_EXCEPTION) {
3133 rv = SEN_FATAL_ERROR;
3134 PRINTKC("exception in send to AP %d\n", index);
3135 break;
3136 }
3137 PDEBUG("return value from send_to_AP: %d\n", rv);
3138 switch (dv) {
3139 case DEV_GONE:
3140 PDEBUG("dev %d not available\n", index);
3141 rv = SEN_NOT_AVAIL;
3142 break;
3143 case DEV_ONLINE:
3144 rv = 0;
3145 break;
3146 case DEV_EMPTY:
3147 rv = SEN_NOT_AVAIL;
3148 break;
3149 case DEV_NO_WORK:
3150 rv = SEN_FATAL_ERROR;
3151 break;
3152 case DEV_BAD_MESSAGE:
3153 rv = SEN_USER_ERROR;
3154 break;
3155 case DEV_QUEUE_FULL:
3156 rv = SEN_QUEUE_FULL;
3157 break;
3158 default:
3159 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3160 rv = SEN_NOT_AVAIL;
3161 break;
3162 }
3163 }
3164
3165 if (rv)
3166 break;
3167
3168 for (i = 0; i < 6; i++) {
3169 mdelay(300);
3170 dv = receive_from_AP(index, z90crypt.cdx,
3171 devPtr->dev_resp_l,
3172 devPtr->dev_resp_p, psmid);
3173 PDEBUG("dv returned by DQ = %d\n", dv);
3174 if (dv == DEV_REC_EXCEPTION) {
3175 rv = REC_FATAL_ERROR;
3176 PRINTKC("exception in dequeue %d\n",
3177 index);
3178 break;
3179 }
3180 switch (dv) {
3181 case DEV_ONLINE:
3182 rv = 0;
3183 break;
3184 case DEV_EMPTY:
3185 rv = REC_EMPTY;
3186 break;
3187 case DEV_NO_WORK:
3188 rv = REC_NO_WORK;
3189 break;
3190 case DEV_BAD_MESSAGE:
3191 case DEV_GONE:
3192 default:
3193 rv = REC_NO_RESPONSE;
3194 break;
3195 }
3196 if ((rv != 0) && (rv != REC_NO_WORK))
3197 break;
3198 if (rv == 0)
3199 break;
3200 }
3201 if (rv)
3202 break;
3203 rv = (devPtr->dev_resp_p[0] == 0x00) &&
3204 (devPtr->dev_resp_p[1] == 0x86);
3205 if (rv)
3206 devPtr->dev_type = PCICC;
3207 else
3208 devPtr->dev_type = PCICA;
3209 rv = 0;
3210 } while (0);
3211 /* In a general error case, the card is not marked online */
3212 return rv;
3213 }
3214
3215 static unsigned char MCL3_testmsg[] = {
3216 0x00,0x00,0x00,0x00,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,
3217 0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3218 0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3219 0x43,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3220 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x00,0x00,0x00,0x01,0xC4,0x00,0x00,0x00,0x00,
3221 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,0x00,0x00,0x00,0x00,
3222 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDC,0x02,0x00,0x00,0x00,0x54,0x32,
3223 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE8,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,
3224 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3225 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3226 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3227 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3228 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3229 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3230 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3231 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3232 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3233 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3234 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3235 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3236 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x0A,0x4D,0x52,0x50,0x20,0x20,0x20,0x20,0x20,
3237 0x00,0x42,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,
3238 0x0E,0x0F,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xAA,0xBB,0xCC,0xDD,
3239 0xEE,0xFF,0xFF,0xEE,0xDD,0xCC,0xBB,0xAA,0x99,0x88,0x77,0x66,0x55,0x44,0x33,0x22,
3240 0x11,0x00,0x01,0x23,0x45,0x67,0x89,0xAB,0xCD,0xEF,0xFE,0xDC,0xBA,0x98,0x76,0x54,
3241 0x32,0x10,0x00,0x9A,0x00,0x98,0x00,0x00,0x1E,0x00,0x00,0x94,0x00,0x00,0x00,0x00,
3242 0x04,0x00,0x00,0x8C,0x00,0x00,0x00,0x40,0x02,0x00,0x00,0x40,0xBA,0xE8,0x23,0x3C,
3243 0x75,0xF3,0x91,0x61,0xD6,0x73,0x39,0xCF,0x7B,0x6D,0x8E,0x61,0x97,0x63,0x9E,0xD9,
3244 0x60,0x55,0xD6,0xC7,0xEF,0xF8,0x1E,0x63,0x95,0x17,0xCC,0x28,0x45,0x60,0x11,0xC5,
3245 0xC4,0x4E,0x66,0xC6,0xE6,0xC3,0xDE,0x8A,0x19,0x30,0xCF,0x0E,0xD7,0xAA,0xDB,0x01,
3246 0xD8,0x00,0xBB,0x8F,0x39,0x9F,0x64,0x28,0xF5,0x7A,0x77,0x49,0xCC,0x6B,0xA3,0x91,
3247 0x97,0x70,0xE7,0x60,0x1E,0x39,0xE1,0xE5,0x33,0xE1,0x15,0x63,0x69,0x08,0x80,0x4C,
3248 0x67,0xC4,0x41,0x8F,0x48,0xDF,0x26,0x98,0xF1,0xD5,0x8D,0x88,0xD9,0x6A,0xA4,0x96,
3249 0xC5,0x84,0xD9,0x30,0x49,0x67,0x7D,0x19,0xB1,0xB3,0x45,0x4D,0xB2,0x53,0x9A,0x47,
3250 0x3C,0x7C,0x55,0xBF,0xCC,0x85,0x00,0x36,0xF1,0x3D,0x93,0x53
3251 };
3252
3253 static int
3254 probe_PCIXCC_type(struct device *devPtr)
3255 {
3256 int rv, dv, i, index, length;
3257 unsigned char psmid[8];
3258 static unsigned char loc_testmsg[548];
3259 struct CPRBX *cprbx_p;
3260
3261 index = devPtr->dev_self_x;
3262 rv = 0;
3263 do {
3264 memcpy(loc_testmsg, MCL3_testmsg, sizeof(MCL3_testmsg));
3265 length = sizeof(MCL3_testmsg) - 0x0C;
3266 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3267 if (dv) {
3268 PDEBUG("dv returned = %d\n", dv);
3269 if (dv == DEV_SEN_EXCEPTION) {
3270 rv = SEN_FATAL_ERROR;
3271 PRINTKC("exception in send to AP %d\n", index);
3272 break;
3273 }
3274 PDEBUG("return value from send_to_AP: %d\n", rv);
3275 switch (dv) {
3276 case DEV_GONE:
3277 PDEBUG("dev %d not available\n", index);
3278 rv = SEN_NOT_AVAIL;
3279 break;
3280 case DEV_ONLINE:
3281 rv = 0;
3282 break;
3283 case DEV_EMPTY:
3284 rv = SEN_NOT_AVAIL;
3285 break;
3286 case DEV_NO_WORK:
3287 rv = SEN_FATAL_ERROR;
3288 break;
3289 case DEV_BAD_MESSAGE:
3290 rv = SEN_USER_ERROR;
3291 break;
3292 case DEV_QUEUE_FULL:
3293 rv = SEN_QUEUE_FULL;
3294 break;
3295 default:
3296 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3297 rv = SEN_NOT_AVAIL;
3298 break;
3299 }
3300 }
3301
3302 if (rv)
3303 break;
3304
3305 for (i = 0; i < 6; i++) {
3306 mdelay(300);
3307 dv = receive_from_AP(index, z90crypt.cdx,
3308 devPtr->dev_resp_l,
3309 devPtr->dev_resp_p, psmid);
3310 PDEBUG("dv returned by DQ = %d\n", dv);
3311 if (dv == DEV_REC_EXCEPTION) {
3312 rv = REC_FATAL_ERROR;
3313 PRINTKC("exception in dequeue %d\n",
3314 index);
3315 break;
3316 }
3317 switch (dv) {
3318 case DEV_ONLINE:
3319 rv = 0;
3320 break;
3321 case DEV_EMPTY:
3322 rv = REC_EMPTY;
3323 break;
3324 case DEV_NO_WORK:
3325 rv = REC_NO_WORK;
3326 break;
3327 case DEV_BAD_MESSAGE:
3328 case DEV_GONE:
3329 default:
3330 rv = REC_NO_RESPONSE;
3331 break;
3332 }
3333 if ((rv != 0) && (rv != REC_NO_WORK))
3334 break;
3335 if (rv == 0)
3336 break;
3337 }
3338 if (rv)
3339 break;
3340 cprbx_p = (struct CPRBX *) (devPtr->dev_resp_p + 48);
3341 if ((cprbx_p->ccp_rtcode == 8) && (cprbx_p->ccp_rscode == 33)) {
3342 devPtr->dev_type = PCIXCC_MCL2;
3343 PDEBUG("device %d is MCL2\n", index);
3344 } else {
3345 devPtr->dev_type = PCIXCC_MCL3;
3346 PDEBUG("device %d is MCL3\n", index);
3347 }
3348 } while (0);
3349 /* In a general error case, the card is not marked online */
3350 return rv;
3351 }
3352
3353 module_init(z90crypt_init_module);
3354 module_exit(z90crypt_cleanup_module);
Linux kernel - Deliverables
This page took 0.160728 seconds and 6 git commands to generate.