projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Pull pnpacpi into acpica branch
[deliverable/linux.git] / drivers / s390 / crypto / z90main.c
1 /*
2 * linux/drivers/s390/crypto/z90main.c
3 *
4 * z90crypt 1.3.2
5 *
6 * Copyright (C) 2001, 2004 IBM Corporation
7 * Author(s): Robert Burroughs (burrough@us.ibm.com)
8 * Eric Rossman (edrossma@us.ibm.com)
9 *
10 * Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <asm/uaccess.h> // copy_(from|to)_user
28 #include <linux/compat.h>
29 #include <linux/compiler.h>
30 #include <linux/delay.h> // mdelay
31 #include <linux/init.h>
32 #include <linux/interrupt.h> // for tasklets
33 #include <linux/ioctl32.h>
34 #include <linux/miscdevice.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/proc_fs.h>
38 #include <linux/syscalls.h>
39 #include "z90crypt.h"
40 #include "z90common.h"
41
42 #define VERSION_Z90MAIN_C "$Revision: 1.62 $"
43
44 static char z90main_version[] __initdata =
45 "z90main.o (" VERSION_Z90MAIN_C "/"
46 VERSION_Z90COMMON_H "/" VERSION_Z90CRYPT_H ")";
47
48 extern char z90hardware_version[];
49
50 /**
51 * Defaults that may be modified.
52 */
53
54 /**
55 * You can specify a different minor at compile time.
56 */
57 #ifndef Z90CRYPT_MINOR
58 #define Z90CRYPT_MINOR MISC_DYNAMIC_MINOR
59 #endif
60
61 /**
62 * You can specify a different domain at compile time or on the insmod
63 * command line.
64 */
65 #ifndef DOMAIN_INDEX
66 #define DOMAIN_INDEX -1
67 #endif
68
69 /**
70 * This is the name under which the device is registered in /proc/modules.
71 */
72 #define REG_NAME "z90crypt"
73
74 /**
75 * Cleanup should run every CLEANUPTIME seconds and should clean up requests
76 * older than CLEANUPTIME seconds in the past.
77 */
78 #ifndef CLEANUPTIME
79 #define CLEANUPTIME 15
80 #endif
81
82 /**
83 * Config should run every CONFIGTIME seconds
84 */
85 #ifndef CONFIGTIME
86 #define CONFIGTIME 30
87 #endif
88
89 /**
90 * The first execution of the config task should take place
91 * immediately after initialization
92 */
93 #ifndef INITIAL_CONFIGTIME
94 #define INITIAL_CONFIGTIME 1
95 #endif
96
97 /**
98 * Reader should run every READERTIME milliseconds
99 * With the 100Hz patch for s390, z90crypt can lock the system solid while
100 * under heavy load. We'll try to avoid that.
101 */
102 #ifndef READERTIME
103 #if HZ > 1000
104 #define READERTIME 2
105 #else
106 #define READERTIME 10
107 #endif
108 #endif
109
110 /**
111 * turn long device array index into device pointer
112 */
113 #define LONG2DEVPTR(ndx) (z90crypt.device_p[(ndx)])
114
115 /**
116 * turn short device array index into long device array index
117 */
118 #define SHRT2LONG(ndx) (z90crypt.overall_device_x.device_index[(ndx)])
119
120 /**
121 * turn short device array index into device pointer
122 */
123 #define SHRT2DEVPTR(ndx) LONG2DEVPTR(SHRT2LONG(ndx))
124
125 /**
126 * Status for a work-element
127 */
128 #define STAT_DEFAULT 0x00 // request has not been processed
129
130 #define STAT_ROUTED 0x80 // bit 7: requests get routed to specific device
131 // else, device is determined each write
132 #define STAT_FAILED 0x40 // bit 6: this bit is set if the request failed
133 // before being sent to the hardware.
134 #define STAT_WRITTEN 0x30 // bits 5-4: work to be done, not sent to device
135 // 0x20 // UNUSED state
136 #define STAT_READPEND 0x10 // bits 5-4: work done, we're returning data now
137 #define STAT_NOWORK 0x00 // bits off: no work on any queue
138 #define STAT_RDWRMASK 0x30 // mask for bits 5-4
139
140 /**
141 * Macros to check the status RDWRMASK
142 */
143 #define CHK_RDWRMASK(statbyte) ((statbyte) & STAT_RDWRMASK)
144 #define SET_RDWRMASK(statbyte, newval) \
145 {(statbyte) &= ~STAT_RDWRMASK; (statbyte) |= newval;}
146
147 /**
148 * Audit Trail. Progress of a Work element
149 * audit[0]: Unless noted otherwise, these bits are all set by the process
150 */
151 #define FP_COPYFROM 0x80 // Caller's buffer has been copied to work element
152 #define FP_BUFFREQ 0x40 // Low Level buffer requested
153 #define FP_BUFFGOT 0x20 // Low Level buffer obtained
154 #define FP_SENT 0x10 // Work element sent to a crypto device
155 // (may be set by process or by reader task)
156 #define FP_PENDING 0x08 // Work element placed on pending queue
157 // (may be set by process or by reader task)
158 #define FP_REQUEST 0x04 // Work element placed on request queue
159 #define FP_ASLEEP 0x02 // Work element about to sleep
160 #define FP_AWAKE 0x01 // Work element has been awakened
161
162 /**
163 * audit[1]: These bits are set by the reader task and/or the cleanup task
164 */
165 #define FP_NOTPENDING 0x80 // Work element removed from pending queue
166 #define FP_AWAKENING 0x40 // Caller about to be awakened
167 #define FP_TIMEDOUT 0x20 // Caller timed out
168 #define FP_RESPSIZESET 0x10 // Response size copied to work element
169 #define FP_RESPADDRCOPIED 0x08 // Response address copied to work element
170 #define FP_RESPBUFFCOPIED 0x04 // Response buffer copied to work element
171 #define FP_REMREQUEST 0x02 // Work element removed from request queue
172 #define FP_SIGNALED 0x01 // Work element was awakened by a signal
173
174 /**
175 * audit[2]: unused
176 */
177
178 /**
179 * state of the file handle in private_data.status
180 */
181 #define STAT_OPEN 0
182 #define STAT_CLOSED 1
183
184 /**
185 * PID() expands to the process ID of the current process
186 */
187 #define PID() (current->pid)
188
189 /**
190 * Selected Constants. The number of APs and the number of devices
191 */
192 #ifndef Z90CRYPT_NUM_APS
193 #define Z90CRYPT_NUM_APS 64
194 #endif
195 #ifndef Z90CRYPT_NUM_DEVS
196 #define Z90CRYPT_NUM_DEVS Z90CRYPT_NUM_APS
197 #endif
198
199 /**
200 * Buffer size for receiving responses. The maximum Response Size
201 * is actually the maximum request size, since in an error condition
202 * the request itself may be returned unchanged.
203 */
204 #define MAX_RESPONSE_SIZE 0x0000077C
205
206 /**
207 * A count and status-byte mask
208 */
209 struct status {
210 int st_count; // # of enabled devices
211 int disabled_count; // # of disabled devices
212 int user_disabled_count; // # of devices disabled via proc fs
213 unsigned char st_mask[Z90CRYPT_NUM_APS]; // current status mask
214 };
215
216 /**
217 * The array of device indexes is a mechanism for fast indexing into
218 * a long (and sparse) array. For instance, if APs 3, 9 and 47 are
219 * installed, z90CDeviceIndex[0] is 3, z90CDeviceIndex[1] is 9, and
220 * z90CDeviceIndex[2] is 47.
221 */
222 struct device_x {
223 int device_index[Z90CRYPT_NUM_DEVS];
224 };
225
226 /**
227 * All devices are arranged in a single array: 64 APs
228 */
229 struct device {
230 int dev_type; // PCICA, PCICC, PCIXCC_MCL2,
231 // PCIXCC_MCL3, CEX2C, CEX2A
232 enum devstat dev_stat; // current device status
233 int dev_self_x; // Index in array
234 int disabled; // Set when device is in error
235 int user_disabled; // Set when device is disabled by user
236 int dev_q_depth; // q depth
237 unsigned char * dev_resp_p; // Response buffer address
238 int dev_resp_l; // Response Buffer length
239 int dev_caller_count; // Number of callers
240 int dev_total_req_cnt; // # requests for device since load
241 struct list_head dev_caller_list; // List of callers
242 };
243
244 /**
245 * There's a struct status and a struct device_x for each device type.
246 */
247 struct hdware_block {
248 struct status hdware_mask;
249 struct status type_mask[Z90CRYPT_NUM_TYPES];
250 struct device_x type_x_addr[Z90CRYPT_NUM_TYPES];
251 unsigned char device_type_array[Z90CRYPT_NUM_APS];
252 };
253
254 /**
255 * z90crypt is the topmost data structure in the hierarchy.
256 */
257 struct z90crypt {
258 int max_count; // Nr of possible crypto devices
259 struct status mask;
260 int q_depth_array[Z90CRYPT_NUM_DEVS];
261 int dev_type_array[Z90CRYPT_NUM_DEVS];
262 struct device_x overall_device_x; // array device indexes
263 struct device * device_p[Z90CRYPT_NUM_DEVS];
264 int terminating;
265 int domain_established;// TRUE: domain has been found
266 int cdx; // Crypto Domain Index
267 int len; // Length of this data structure
268 struct hdware_block *hdware_info;
269 };
270
271 /**
272 * An array of these structures is pointed to from dev_caller
273 * The length of the array depends on the device type. For APs,
274 * there are 8.
275 *
276 * The caller buffer is allocated to the user at OPEN. At WRITE,
277 * it contains the request; at READ, the response. The function
278 * send_to_crypto_device converts the request to device-dependent
279 * form and use the caller's OPEN-allocated buffer for the response.
280 *
281 * For the contents of caller_dev_dep_req and caller_dev_dep_req_p
282 * because that points to it, see the discussion in z90hardware.c.
283 * Search for "extended request message block".
284 */
285 struct caller {
286 int caller_buf_l; // length of original request
287 unsigned char * caller_buf_p; // Original request on WRITE
288 int caller_dev_dep_req_l; // len device dependent request
289 unsigned char * caller_dev_dep_req_p; // Device dependent form
290 unsigned char caller_id[8]; // caller-supplied message id
291 struct list_head caller_liste;
292 unsigned char caller_dev_dep_req[MAX_RESPONSE_SIZE];
293 };
294
295 /**
296 * Function prototypes from z90hardware.c
297 */
298 enum hdstat query_online(int deviceNr, int cdx, int resetNr, int *q_depth,
299 int *dev_type);
300 enum devstat reset_device(int deviceNr, int cdx, int resetNr);
301 enum devstat send_to_AP(int dev_nr, int cdx, int msg_len, unsigned char *msg_ext);
302 enum devstat receive_from_AP(int dev_nr, int cdx, int resplen,
303 unsigned char *resp, unsigned char *psmid);
304 int convert_request(unsigned char *buffer, int func, unsigned short function,
305 int cdx, int dev_type, int *msg_l_p, unsigned char *msg_p);
306 int convert_response(unsigned char *response, unsigned char *buffer,
307 int *respbufflen_p, unsigned char *resp_buff);
308
309 /**
310 * Low level function prototypes
311 */
312 static int create_z90crypt(int *cdx_p);
313 static int refresh_z90crypt(int *cdx_p);
314 static int find_crypto_devices(struct status *deviceMask);
315 static int create_crypto_device(int index);
316 static int destroy_crypto_device(int index);
317 static void destroy_z90crypt(void);
318 static int refresh_index_array(struct status *status_str,
319 struct device_x *index_array);
320 static int probe_device_type(struct device *devPtr);
321 static int probe_PCIXCC_type(struct device *devPtr);
322
323 /**
324 * proc fs definitions
325 */
326 static struct proc_dir_entry *z90crypt_entry;
327
328 /**
329 * data structures
330 */
331
332 /**
333 * work_element.opener points back to this structure
334 */
335 struct priv_data {
336 pid_t opener_pid;
337 unsigned char status; // 0: open 1: closed
338 };
339
340 /**
341 * A work element is allocated for each request
342 */
343 struct work_element {
344 struct priv_data *priv_data;
345 pid_t pid;
346 int devindex; // index of device processing this w_e
347 // (If request did not specify device,
348 // -1 until placed onto a queue)
349 int devtype;
350 struct list_head liste; // used for requestq and pendingq
351 char buffer[128]; // local copy of user request
352 int buff_size; // size of the buffer for the request
353 char resp_buff[RESPBUFFSIZE];
354 int resp_buff_size;
355 char __user * resp_addr; // address of response in user space
356 unsigned int funccode; // function code of request
357 wait_queue_head_t waitq;
358 unsigned long requestsent; // time at which the request was sent
359 atomic_t alarmrung; // wake-up signal
360 unsigned char caller_id[8]; // pid + counter, for this w_e
361 unsigned char status[1]; // bits to mark status of the request
362 unsigned char audit[3]; // record of work element's progress
363 unsigned char * requestptr; // address of request buffer
364 int retcode; // return code of request
365 };
366
367 /**
368 * High level function prototypes
369 */
370 static int z90crypt_open(struct inode *, struct file *);
371 static int z90crypt_release(struct inode *, struct file *);
372 static ssize_t z90crypt_read(struct file *, char __user *, size_t, loff_t *);
373 static ssize_t z90crypt_write(struct file *, const char __user *,
374 size_t, loff_t *);
375 static long z90crypt_unlocked_ioctl(struct file *, unsigned int, unsigned long);
376 static long z90crypt_compat_ioctl(struct file *, unsigned int, unsigned long);
377
378 static void z90crypt_reader_task(unsigned long);
379 static void z90crypt_schedule_reader_task(unsigned long);
380 static void z90crypt_config_task(unsigned long);
381 static void z90crypt_cleanup_task(unsigned long);
382
383 static int z90crypt_status(char *, char **, off_t, int, int *, void *);
384 static int z90crypt_status_write(struct file *, const char __user *,
385 unsigned long, void *);
386
387 /**
388 * Storage allocated at initialization and used throughout the life of
389 * this insmod
390 */
391 static int domain = DOMAIN_INDEX;
392 static struct z90crypt z90crypt;
393 static int quiesce_z90crypt;
394 static spinlock_t queuespinlock;
395 static struct list_head request_list;
396 static int requestq_count;
397 static struct list_head pending_list;
398 static int pendingq_count;
399
400 static struct tasklet_struct reader_tasklet;
401 static struct timer_list reader_timer;
402 static struct timer_list config_timer;
403 static struct timer_list cleanup_timer;
404 static atomic_t total_open;
405 static atomic_t z90crypt_step;
406
407 static struct file_operations z90crypt_fops = {
408 .owner = THIS_MODULE,
409 .read = z90crypt_read,
410 .write = z90crypt_write,
411 .unlocked_ioctl = z90crypt_unlocked_ioctl,
412 #ifdef CONFIG_COMPAT
413 .compat_ioctl = z90crypt_compat_ioctl,
414 #endif
415 .open = z90crypt_open,
416 .release = z90crypt_release
417 };
418
419 static struct miscdevice z90crypt_misc_device = {
420 .minor = Z90CRYPT_MINOR,
421 .name = DEV_NAME,
422 .fops = &z90crypt_fops,
423 .devfs_name = DEV_NAME
424 };
425
426 /**
427 * Documentation values.
428 */
429 MODULE_AUTHOR("zSeries Linux Crypto Team: Robert H. Burroughs, Eric D. Rossman"
430 "and Jochen Roehrig");
431 MODULE_DESCRIPTION("zSeries Linux Cryptographic Coprocessor device driver, "
432 "Copyright 2001, 2005 IBM Corporation");
433 MODULE_LICENSE("GPL");
434 module_param(domain, int, 0);
435 MODULE_PARM_DESC(domain, "domain index for device");
436
437 #ifdef CONFIG_COMPAT
438 /**
439 * ioctl32 conversion routines
440 */
441 struct ica_rsa_modexpo_32 { // For 32-bit callers
442 compat_uptr_t inputdata;
443 unsigned int inputdatalength;
444 compat_uptr_t outputdata;
445 unsigned int outputdatalength;
446 compat_uptr_t b_key;
447 compat_uptr_t n_modulus;
448 };
449
450 static long
451 trans_modexpo32(struct file *filp, unsigned int cmd, unsigned long arg)
452 {
453 struct ica_rsa_modexpo_32 __user *mex32u = compat_ptr(arg);
454 struct ica_rsa_modexpo_32 mex32k;
455 struct ica_rsa_modexpo __user *mex64;
456 long ret = 0;
457 unsigned int i;
458
459 if (!access_ok(VERIFY_WRITE, mex32u, sizeof(struct ica_rsa_modexpo_32)))
460 return -EFAULT;
461 mex64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo));
462 if (!access_ok(VERIFY_WRITE, mex64, sizeof(struct ica_rsa_modexpo)))
463 return -EFAULT;
464 if (copy_from_user(&mex32k, mex32u, sizeof(struct ica_rsa_modexpo_32)))
465 return -EFAULT;
466 if (__put_user(compat_ptr(mex32k.inputdata), &mex64->inputdata) ||
467 __put_user(mex32k.inputdatalength, &mex64->inputdatalength) ||
468 __put_user(compat_ptr(mex32k.outputdata), &mex64->outputdata) ||
469 __put_user(mex32k.outputdatalength, &mex64->outputdatalength) ||
470 __put_user(compat_ptr(mex32k.b_key), &mex64->b_key) ||
471 __put_user(compat_ptr(mex32k.n_modulus), &mex64->n_modulus))
472 return -EFAULT;
473 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)mex64);
474 if (!ret)
475 if (__get_user(i, &mex64->outputdatalength) ||
476 __put_user(i, &mex32u->outputdatalength))
477 ret = -EFAULT;
478 return ret;
479 }
480
481 struct ica_rsa_modexpo_crt_32 { // For 32-bit callers
482 compat_uptr_t inputdata;
483 unsigned int inputdatalength;
484 compat_uptr_t outputdata;
485 unsigned int outputdatalength;
486 compat_uptr_t bp_key;
487 compat_uptr_t bq_key;
488 compat_uptr_t np_prime;
489 compat_uptr_t nq_prime;
490 compat_uptr_t u_mult_inv;
491 };
492
493 static long
494 trans_modexpo_crt32(struct file *filp, unsigned int cmd, unsigned long arg)
495 {
496 struct ica_rsa_modexpo_crt_32 __user *crt32u = compat_ptr(arg);
497 struct ica_rsa_modexpo_crt_32 crt32k;
498 struct ica_rsa_modexpo_crt __user *crt64;
499 long ret = 0;
500 unsigned int i;
501
502 if (!access_ok(VERIFY_WRITE, crt32u,
503 sizeof(struct ica_rsa_modexpo_crt_32)))
504 return -EFAULT;
505 crt64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo_crt));
506 if (!access_ok(VERIFY_WRITE, crt64, sizeof(struct ica_rsa_modexpo_crt)))
507 return -EFAULT;
508 if (copy_from_user(&crt32k, crt32u,
509 sizeof(struct ica_rsa_modexpo_crt_32)))
510 return -EFAULT;
511 if (__put_user(compat_ptr(crt32k.inputdata), &crt64->inputdata) ||
512 __put_user(crt32k.inputdatalength, &crt64->inputdatalength) ||
513 __put_user(compat_ptr(crt32k.outputdata), &crt64->outputdata) ||
514 __put_user(crt32k.outputdatalength, &crt64->outputdatalength) ||
515 __put_user(compat_ptr(crt32k.bp_key), &crt64->bp_key) ||
516 __put_user(compat_ptr(crt32k.bq_key), &crt64->bq_key) ||
517 __put_user(compat_ptr(crt32k.np_prime), &crt64->np_prime) ||
518 __put_user(compat_ptr(crt32k.nq_prime), &crt64->nq_prime) ||
519 __put_user(compat_ptr(crt32k.u_mult_inv), &crt64->u_mult_inv))
520 return -EFAULT;
521 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)crt64);
522 if (!ret)
523 if (__get_user(i, &crt64->outputdatalength) ||
524 __put_user(i, &crt32u->outputdatalength))
525 ret = -EFAULT;
526 return ret;
527 }
528
529 static long
530 z90crypt_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
531 {
532 switch (cmd) {
533 case ICAZ90STATUS:
534 case Z90QUIESCE:
535 case Z90STAT_TOTALCOUNT:
536 case Z90STAT_PCICACOUNT:
537 case Z90STAT_PCICCCOUNT:
538 case Z90STAT_PCIXCCCOUNT:
539 case Z90STAT_PCIXCCMCL2COUNT:
540 case Z90STAT_PCIXCCMCL3COUNT:
541 case Z90STAT_CEX2CCOUNT:
542 case Z90STAT_REQUESTQ_COUNT:
543 case Z90STAT_PENDINGQ_COUNT:
544 case Z90STAT_TOTALOPEN_COUNT:
545 case Z90STAT_DOMAIN_INDEX:
546 case Z90STAT_STATUS_MASK:
547 case Z90STAT_QDEPTH_MASK:
548 case Z90STAT_PERDEV_REQCNT:
549 return z90crypt_unlocked_ioctl(filp, cmd, arg);
550 case ICARSAMODEXPO:
551 return trans_modexpo32(filp, cmd, arg);
552 case ICARSACRT:
553 return trans_modexpo_crt32(filp, cmd, arg);
554 default:
555 return -ENOIOCTLCMD;
556 }
557 }
558 #endif
559
560 /**
561 * The module initialization code.
562 */
563 static int __init
564 z90crypt_init_module(void)
565 {
566 int result, nresult;
567 struct proc_dir_entry *entry;
568
569 PDEBUG("PID %d\n", PID());
570
571 if ((domain < -1) || (domain > 15)) {
572 PRINTKW("Invalid param: domain = %d. Not loading.\n", domain);
573 return -EINVAL;
574 }
575
576 /* Register as misc device with given minor (or get a dynamic one). */
577 result = misc_register(&z90crypt_misc_device);
578 if (result < 0) {
579 PRINTKW(KERN_ERR "misc_register (minor %d) failed with %d\n",
580 z90crypt_misc_device.minor, result);
581 return result;
582 }
583
584 PDEBUG("Registered " DEV_NAME " with result %d\n", result);
585
586 result = create_z90crypt(&domain);
587 if (result != 0) {
588 PRINTKW("create_z90crypt (domain index %d) failed with %d.\n",
589 domain, result);
590 result = -ENOMEM;
591 goto init_module_cleanup;
592 }
593
594 if (result == 0) {
595 PRINTKN("Version %d.%d.%d loaded, built on %s %s\n",
596 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT,
597 __DATE__, __TIME__);
598 PRINTKN("%s\n", z90main_version);
599 PRINTKN("%s\n", z90hardware_version);
600 PDEBUG("create_z90crypt (domain index %d) successful.\n",
601 domain);
602 } else
603 PRINTK("No devices at startup\n");
604
605 /* Initialize globals. */
606 spin_lock_init(&queuespinlock);
607
608 INIT_LIST_HEAD(&pending_list);
609 pendingq_count = 0;
610
611 INIT_LIST_HEAD(&request_list);
612 requestq_count = 0;
613
614 quiesce_z90crypt = 0;
615
616 atomic_set(&total_open, 0);
617 atomic_set(&z90crypt_step, 0);
618
619 /* Set up the cleanup task. */
620 init_timer(&cleanup_timer);
621 cleanup_timer.function = z90crypt_cleanup_task;
622 cleanup_timer.data = 0;
623 cleanup_timer.expires = jiffies + (CLEANUPTIME * HZ);
624 add_timer(&cleanup_timer);
625
626 /* Set up the proc file system */
627 entry = create_proc_entry("driver/z90crypt", 0644, 0);
628 if (entry) {
629 entry->nlink = 1;
630 entry->data = 0;
631 entry->read_proc = z90crypt_status;
632 entry->write_proc = z90crypt_status_write;
633 }
634 else
635 PRINTK("Couldn't create z90crypt proc entry\n");
636 z90crypt_entry = entry;
637
638 /* Set up the configuration task. */
639 init_timer(&config_timer);
640 config_timer.function = z90crypt_config_task;
641 config_timer.data = 0;
642 config_timer.expires = jiffies + (INITIAL_CONFIGTIME * HZ);
643 add_timer(&config_timer);
644
645 /* Set up the reader task */
646 tasklet_init(&reader_tasklet, z90crypt_reader_task, 0);
647 init_timer(&reader_timer);
648 reader_timer.function = z90crypt_schedule_reader_task;
649 reader_timer.data = 0;
650 reader_timer.expires = jiffies + (READERTIME * HZ / 1000);
651 add_timer(&reader_timer);
652
653 return 0; // success
654
655 init_module_cleanup:
656 if ((nresult = misc_deregister(&z90crypt_misc_device)))
657 PRINTK("misc_deregister failed with %d.\n", nresult);
658 else
659 PDEBUG("misc_deregister successful.\n");
660
661 return result; // failure
662 }
663
664 /**
665 * The module termination code
666 */
667 static void __exit
668 z90crypt_cleanup_module(void)
669 {
670 int nresult;
671
672 PDEBUG("PID %d\n", PID());
673
674 remove_proc_entry("driver/z90crypt", 0);
675
676 if ((nresult = misc_deregister(&z90crypt_misc_device)))
677 PRINTK("misc_deregister failed with %d.\n", nresult);
678 else
679 PDEBUG("misc_deregister successful.\n");
680
681 /* Remove the tasks */
682 tasklet_kill(&reader_tasklet);
683 del_timer(&reader_timer);
684 del_timer(&config_timer);
685 del_timer(&cleanup_timer);
686
687 destroy_z90crypt();
688
689 PRINTKN("Unloaded.\n");
690 }
691
692 /**
693 * Functions running under a process id
694 *
695 * The I/O functions:
696 * z90crypt_open
697 * z90crypt_release
698 * z90crypt_read
699 * z90crypt_write
700 * z90crypt_unlocked_ioctl
701 * z90crypt_status
702 * z90crypt_status_write
703 * disable_card
704 * enable_card
705 *
706 * Helper functions:
707 * z90crypt_rsa
708 * z90crypt_prepare
709 * z90crypt_send
710 * z90crypt_process_results
711 *
712 */
713 static int
714 z90crypt_open(struct inode *inode, struct file *filp)
715 {
716 struct priv_data *private_data_p;
717
718 if (quiesce_z90crypt)
719 return -EQUIESCE;
720
721 private_data_p = kmalloc(sizeof(struct priv_data), GFP_KERNEL);
722 if (!private_data_p) {
723 PRINTK("Memory allocate failed\n");
724 return -ENOMEM;
725 }
726
727 memset((void *)private_data_p, 0, sizeof(struct priv_data));
728 private_data_p->status = STAT_OPEN;
729 private_data_p->opener_pid = PID();
730 filp->private_data = private_data_p;
731 atomic_inc(&total_open);
732
733 return 0;
734 }
735
736 static int
737 z90crypt_release(struct inode *inode, struct file *filp)
738 {
739 struct priv_data *private_data_p = filp->private_data;
740
741 PDEBUG("PID %d (filp %p)\n", PID(), filp);
742
743 private_data_p->status = STAT_CLOSED;
744 memset(private_data_p, 0, sizeof(struct priv_data));
745 kfree(private_data_p);
746 atomic_dec(&total_open);
747
748 return 0;
749 }
750
751 /*
752 * there are two read functions, of which compile options will choose one
753 * without USE_GET_RANDOM_BYTES
754 * => read() always returns -EPERM;
755 * otherwise
756 * => read() uses get_random_bytes() kernel function
757 */
758 #ifndef USE_GET_RANDOM_BYTES
759 /**
760 * z90crypt_read will not be supported beyond z90crypt 1.3.1
761 */
762 static ssize_t
763 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
764 {
765 PDEBUG("filp %p (PID %d)\n", filp, PID());
766 return -EPERM;
767 }
768 #else // we want to use get_random_bytes
769 /**
770 * read() just returns a string of random bytes. Since we have no way
771 * to generate these cryptographically, we just execute get_random_bytes
772 * for the length specified.
773 */
774 #include <linux/random.h>
775 static ssize_t
776 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
777 {
778 unsigned char *temp_buff;
779
780 PDEBUG("filp %p (PID %d)\n", filp, PID());
781
782 if (quiesce_z90crypt)
783 return -EQUIESCE;
784 if (count < 0) {
785 PRINTK("Requested random byte count negative: %ld\n", count);
786 return -EINVAL;
787 }
788 if (count > RESPBUFFSIZE) {
789 PDEBUG("count[%d] > RESPBUFFSIZE", count);
790 return -EINVAL;
791 }
792 if (count == 0)
793 return 0;
794 temp_buff = kmalloc(RESPBUFFSIZE, GFP_KERNEL);
795 if (!temp_buff) {
796 PRINTK("Memory allocate failed\n");
797 return -ENOMEM;
798 }
799 get_random_bytes(temp_buff, count);
800
801 if (copy_to_user(buf, temp_buff, count) != 0) {
802 kfree(temp_buff);
803 return -EFAULT;
804 }
805 kfree(temp_buff);
806 return count;
807 }
808 #endif
809
810 /**
811 * Write is is not allowed
812 */
813 static ssize_t
814 z90crypt_write(struct file *filp, const char __user *buf, size_t count, loff_t *f_pos)
815 {
816 PDEBUG("filp %p (PID %d)\n", filp, PID());
817 return -EPERM;
818 }
819
820 /**
821 * New status functions
822 */
823 static inline int
824 get_status_totalcount(void)
825 {
826 return z90crypt.hdware_info->hdware_mask.st_count;
827 }
828
829 static inline int
830 get_status_PCICAcount(void)
831 {
832 return z90crypt.hdware_info->type_mask[PCICA].st_count;
833 }
834
835 static inline int
836 get_status_PCICCcount(void)
837 {
838 return z90crypt.hdware_info->type_mask[PCICC].st_count;
839 }
840
841 static inline int
842 get_status_PCIXCCcount(void)
843 {
844 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count +
845 z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
846 }
847
848 static inline int
849 get_status_PCIXCCMCL2count(void)
850 {
851 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count;
852 }
853
854 static inline int
855 get_status_PCIXCCMCL3count(void)
856 {
857 return z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
858 }
859
860 static inline int
861 get_status_CEX2Ccount(void)
862 {
863 return z90crypt.hdware_info->type_mask[CEX2C].st_count;
864 }
865
866 static inline int
867 get_status_CEX2Acount(void)
868 {
869 return z90crypt.hdware_info->type_mask[CEX2A].st_count;
870 }
871
872 static inline int
873 get_status_requestq_count(void)
874 {
875 return requestq_count;
876 }
877
878 static inline int
879 get_status_pendingq_count(void)
880 {
881 return pendingq_count;
882 }
883
884 static inline int
885 get_status_totalopen_count(void)
886 {
887 return atomic_read(&total_open);
888 }
889
890 static inline int
891 get_status_domain_index(void)
892 {
893 return z90crypt.cdx;
894 }
895
896 static inline unsigned char *
897 get_status_status_mask(unsigned char status[Z90CRYPT_NUM_APS])
898 {
899 int i, ix;
900
901 memcpy(status, z90crypt.hdware_info->device_type_array,
902 Z90CRYPT_NUM_APS);
903
904 for (i = 0; i < get_status_totalcount(); i++) {
905 ix = SHRT2LONG(i);
906 if (LONG2DEVPTR(ix)->user_disabled)
907 status[ix] = 0x0d;
908 }
909
910 return status;
911 }
912
913 static inline unsigned char *
914 get_status_qdepth_mask(unsigned char qdepth[Z90CRYPT_NUM_APS])
915 {
916 int i, ix;
917
918 memset(qdepth, 0, Z90CRYPT_NUM_APS);
919
920 for (i = 0; i < get_status_totalcount(); i++) {
921 ix = SHRT2LONG(i);
922 qdepth[ix] = LONG2DEVPTR(ix)->dev_caller_count;
923 }
924
925 return qdepth;
926 }
927
928 static inline unsigned int *
929 get_status_perdevice_reqcnt(unsigned int reqcnt[Z90CRYPT_NUM_APS])
930 {
931 int i, ix;
932
933 memset(reqcnt, 0, Z90CRYPT_NUM_APS * sizeof(int));
934
935 for (i = 0; i < get_status_totalcount(); i++) {
936 ix = SHRT2LONG(i);
937 reqcnt[ix] = LONG2DEVPTR(ix)->dev_total_req_cnt;
938 }
939
940 return reqcnt;
941 }
942
943 static inline void
944 init_work_element(struct work_element *we_p,
945 struct priv_data *priv_data, pid_t pid)
946 {
947 int step;
948
949 we_p->requestptr = (unsigned char *)we_p + sizeof(struct work_element);
950 /* Come up with a unique id for this caller. */
951 step = atomic_inc_return(&z90crypt_step);
952 memcpy(we_p->caller_id+0, (void *) &pid, sizeof(pid));
953 memcpy(we_p->caller_id+4, (void *) &step, sizeof(step));
954 we_p->pid = pid;
955 we_p->priv_data = priv_data;
956 we_p->status[0] = STAT_DEFAULT;
957 we_p->audit[0] = 0x00;
958 we_p->audit[1] = 0x00;
959 we_p->audit[2] = 0x00;
960 we_p->resp_buff_size = 0;
961 we_p->retcode = 0;
962 we_p->devindex = -1;
963 we_p->devtype = -1;
964 atomic_set(&we_p->alarmrung, 0);
965 init_waitqueue_head(&we_p->waitq);
966 INIT_LIST_HEAD(&(we_p->liste));
967 }
968
969 static inline int
970 allocate_work_element(struct work_element **we_pp,
971 struct priv_data *priv_data_p, pid_t pid)
972 {
973 struct work_element *we_p;
974
975 we_p = (struct work_element *) get_zeroed_page(GFP_KERNEL);
976 if (!we_p)
977 return -ENOMEM;
978 init_work_element(we_p, priv_data_p, pid);
979 *we_pp = we_p;
980 return 0;
981 }
982
983 static inline void
984 remove_device(struct device *device_p)
985 {
986 if (!device_p || (device_p->disabled != 0))
987 return;
988 device_p->disabled = 1;
989 z90crypt.hdware_info->type_mask[device_p->dev_type].disabled_count++;
990 z90crypt.hdware_info->hdware_mask.disabled_count++;
991 }
992
993 /**
994 * Bitlength limits for each card
995 *
996 * There are new MCLs which allow more bitlengths. See the table for details.
997 * The MCL must be applied and the newer bitlengths enabled for these to work.
998 *
999 * Card Type Old limit New limit
1000 * PCICA ??-2048 same (the lower limit is less than 128 bit...)
1001 * PCICC 512-1024 512-2048
1002 * PCIXCC_MCL2 512-2048 ----- (applying any GA LIC will make an MCL3 card)
1003 * PCIXCC_MCL3 ----- 128-2048
1004 * CEX2C 512-2048 128-2048
1005 *
1006 * ext_bitlens (extended bitlengths) is a global, since you should not apply an
1007 * MCL to just one card in a machine. We assume, at first, that all cards have
1008 * these capabilities.
1009 */
1010 int ext_bitlens = 1; // This is global
1011 #define PCIXCC_MIN_MOD_SIZE 16 // 128 bits
1012 #define OLD_PCIXCC_MIN_MOD_SIZE 64 // 512 bits
1013 #define PCICC_MIN_MOD_SIZE 64 // 512 bits
1014 #define OLD_PCICC_MAX_MOD_SIZE 128 // 1024 bits
1015 #define MAX_MOD_SIZE 256 // 2048 bits
1016
1017 static inline int
1018 select_device_type(int *dev_type_p, int bytelength)
1019 {
1020 static int count = 0;
1021 int PCICA_avail, PCIXCC_MCL3_avail, CEX2C_avail, CEX2A_avail,
1022 index_to_use;
1023 struct status *stat;
1024 if ((*dev_type_p != PCICC) && (*dev_type_p != PCICA) &&
1025 (*dev_type_p != PCIXCC_MCL2) && (*dev_type_p != PCIXCC_MCL3) &&
1026 (*dev_type_p != CEX2C) && (*dev_type_p != CEX2A) &&
1027 (*dev_type_p != ANYDEV))
1028 return -1;
1029 if (*dev_type_p != ANYDEV) {
1030 stat = &z90crypt.hdware_info->type_mask[*dev_type_p];
1031 if (stat->st_count >
1032 (stat->disabled_count + stat->user_disabled_count))
1033 return 0;
1034 return -1;
1035 }
1036
1037 /**
1038 * Assumption: PCICA, PCIXCC_MCL3, CEX2C, and CEX2A are all similar in
1039 * speed.
1040 *
1041 * PCICA and CEX2A do NOT co-exist, so it would be either one or the
1042 * other present.
1043 */
1044 stat = &z90crypt.hdware_info->type_mask[PCICA];
1045 PCICA_avail = stat->st_count -
1046 (stat->disabled_count + stat->user_disabled_count);
1047 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL3];
1048 PCIXCC_MCL3_avail = stat->st_count -
1049 (stat->disabled_count + stat->user_disabled_count);
1050 stat = &z90crypt.hdware_info->type_mask[CEX2C];
1051 CEX2C_avail = stat->st_count -
1052 (stat->disabled_count + stat->user_disabled_count);
1053 stat = &z90crypt.hdware_info->type_mask[CEX2A];
1054 CEX2A_avail = stat->st_count -
1055 (stat->disabled_count + stat->user_disabled_count);
1056 if (PCICA_avail || PCIXCC_MCL3_avail || CEX2C_avail || CEX2A_avail) {
1057 /**
1058 * bitlength is a factor, PCICA or CEX2A are the most capable,
1059 * even with the new MCL for PCIXCC.
1060 */
1061 if ((bytelength < PCIXCC_MIN_MOD_SIZE) ||
1062 (!ext_bitlens && (bytelength < OLD_PCIXCC_MIN_MOD_SIZE))) {
1063 if (PCICA_avail) {
1064 *dev_type_p = PCICA;
1065 return 0;
1066 }
1067 if (CEX2A_avail) {
1068 *dev_type_p = CEX2A;
1069 return 0;
1070 }
1071 return -1;
1072 }
1073
1074 index_to_use = count % (PCICA_avail + PCIXCC_MCL3_avail +
1075 CEX2C_avail + CEX2A_avail);
1076 if (index_to_use < PCICA_avail)
1077 *dev_type_p = PCICA;
1078 else if (index_to_use < (PCICA_avail + PCIXCC_MCL3_avail))
1079 *dev_type_p = PCIXCC_MCL3;
1080 else if (index_to_use < (PCICA_avail + PCIXCC_MCL3_avail +
1081 CEX2C_avail))
1082 *dev_type_p = CEX2C;
1083 else
1084 *dev_type_p = CEX2A;
1085 count++;
1086 return 0;
1087 }
1088
1089 /* Less than OLD_PCIXCC_MIN_MOD_SIZE cannot go to a PCIXCC_MCL2 */
1090 if (bytelength < OLD_PCIXCC_MIN_MOD_SIZE)
1091 return -1;
1092 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL2];
1093 if (stat->st_count >
1094 (stat->disabled_count + stat->user_disabled_count)) {
1095 *dev_type_p = PCIXCC_MCL2;
1096 return 0;
1097 }
1098
1099 /**
1100 * Less than PCICC_MIN_MOD_SIZE or more than OLD_PCICC_MAX_MOD_SIZE
1101 * (if we don't have the MCL applied and the newer bitlengths enabled)
1102 * cannot go to a PCICC
1103 */
1104 if ((bytelength < PCICC_MIN_MOD_SIZE) ||
1105 (!ext_bitlens && (bytelength > OLD_PCICC_MAX_MOD_SIZE))) {
1106 return -1;
1107 }
1108 stat = &z90crypt.hdware_info->type_mask[PCICC];
1109 if (stat->st_count >
1110 (stat->disabled_count + stat->user_disabled_count)) {
1111 *dev_type_p = PCICC;
1112 return 0;
1113 }
1114
1115 return -1;
1116 }
1117
1118 /**
1119 * Try the selected number, then the selected type (can be ANYDEV)
1120 */
1121 static inline int
1122 select_device(int *dev_type_p, int *device_nr_p, int bytelength)
1123 {
1124 int i, indx, devTp, low_count, low_indx;
1125 struct device_x *index_p;
1126 struct device *dev_ptr;
1127
1128 PDEBUG("device type = %d, index = %d\n", *dev_type_p, *device_nr_p);
1129 if ((*device_nr_p >= 0) && (*device_nr_p < Z90CRYPT_NUM_DEVS)) {
1130 PDEBUG("trying index = %d\n", *device_nr_p);
1131 dev_ptr = z90crypt.device_p[*device_nr_p];
1132
1133 if (dev_ptr &&
1134 (dev_ptr->dev_stat != DEV_GONE) &&
1135 (dev_ptr->disabled == 0) &&
1136 (dev_ptr->user_disabled == 0)) {
1137 PDEBUG("selected by number, index = %d\n",
1138 *device_nr_p);
1139 *dev_type_p = dev_ptr->dev_type;
1140 return *device_nr_p;
1141 }
1142 }
1143 *device_nr_p = -1;
1144 PDEBUG("trying type = %d\n", *dev_type_p);
1145 devTp = *dev_type_p;
1146 if (select_device_type(&devTp, bytelength) == -1) {
1147 PDEBUG("failed to select by type\n");
1148 return -1;
1149 }
1150 PDEBUG("selected type = %d\n", devTp);
1151 index_p = &z90crypt.hdware_info->type_x_addr[devTp];
1152 low_count = 0x0000FFFF;
1153 low_indx = -1;
1154 for (i = 0; i < z90crypt.hdware_info->type_mask[devTp].st_count; i++) {
1155 indx = index_p->device_index[i];
1156 dev_ptr = z90crypt.device_p[indx];
1157 if (dev_ptr &&
1158 (dev_ptr->dev_stat != DEV_GONE) &&
1159 (dev_ptr->disabled == 0) &&
1160 (dev_ptr->user_disabled == 0) &&
1161 (devTp == dev_ptr->dev_type) &&
1162 (low_count > dev_ptr->dev_caller_count)) {
1163 low_count = dev_ptr->dev_caller_count;
1164 low_indx = indx;
1165 }
1166 }
1167 *device_nr_p = low_indx;
1168 return low_indx;
1169 }
1170
1171 static inline int
1172 send_to_crypto_device(struct work_element *we_p)
1173 {
1174 struct caller *caller_p;
1175 struct device *device_p;
1176 int dev_nr;
1177 int bytelen = ((struct ica_rsa_modexpo *)we_p->buffer)->inputdatalength;
1178
1179 if (!we_p->requestptr)
1180 return SEN_FATAL_ERROR;
1181 caller_p = (struct caller *)we_p->requestptr;
1182 dev_nr = we_p->devindex;
1183 if (select_device(&we_p->devtype, &dev_nr, bytelen) == -1) {
1184 if (z90crypt.hdware_info->hdware_mask.st_count != 0)
1185 return SEN_RETRY;
1186 else
1187 return SEN_NOT_AVAIL;
1188 }
1189 we_p->devindex = dev_nr;
1190 device_p = z90crypt.device_p[dev_nr];
1191 if (!device_p)
1192 return SEN_NOT_AVAIL;
1193 if (device_p->dev_type != we_p->devtype)
1194 return SEN_RETRY;
1195 if (device_p->dev_caller_count >= device_p->dev_q_depth)
1196 return SEN_QUEUE_FULL;
1197 PDEBUG("device number prior to send: %d\n", dev_nr);
1198 switch (send_to_AP(dev_nr, z90crypt.cdx,
1199 caller_p->caller_dev_dep_req_l,
1200 caller_p->caller_dev_dep_req_p)) {
1201 case DEV_SEN_EXCEPTION:
1202 PRINTKC("Exception during send to device %d\n", dev_nr);
1203 z90crypt.terminating = 1;
1204 return SEN_FATAL_ERROR;
1205 case DEV_GONE:
1206 PRINTK("Device %d not available\n", dev_nr);
1207 remove_device(device_p);
1208 return SEN_NOT_AVAIL;
1209 case DEV_EMPTY:
1210 return SEN_NOT_AVAIL;
1211 case DEV_NO_WORK:
1212 return SEN_FATAL_ERROR;
1213 case DEV_BAD_MESSAGE:
1214 return SEN_USER_ERROR;
1215 case DEV_QUEUE_FULL:
1216 return SEN_QUEUE_FULL;
1217 default:
1218 case DEV_ONLINE:
1219 break;
1220 }
1221 list_add_tail(&(caller_p->caller_liste), &(device_p->dev_caller_list));
1222 device_p->dev_caller_count++;
1223 return 0;
1224 }
1225
1226 /**
1227 * Send puts the user's work on one of two queues:
1228 * the pending queue if the send was successful
1229 * the request queue if the send failed because device full or busy
1230 */
1231 static inline int
1232 z90crypt_send(struct work_element *we_p, const char *buf)
1233 {
1234 int rv;
1235
1236 PDEBUG("PID %d\n", PID());
1237
1238 if (CHK_RDWRMASK(we_p->status[0]) != STAT_NOWORK) {
1239 PDEBUG("PID %d tried to send more work but has outstanding "
1240 "work.\n", PID());
1241 return -EWORKPEND;
1242 }
1243 we_p->devindex = -1; // Reset device number
1244 spin_lock_irq(&queuespinlock);
1245 rv = send_to_crypto_device(we_p);
1246 switch (rv) {
1247 case 0:
1248 we_p->requestsent = jiffies;
1249 we_p->audit[0] |= FP_SENT;
1250 list_add_tail(&we_p->liste, &pending_list);
1251 ++pendingq_count;
1252 we_p->audit[0] |= FP_PENDING;
1253 break;
1254 case SEN_BUSY:
1255 case SEN_QUEUE_FULL:
1256 rv = 0;
1257 we_p->devindex = -1; // any device will do
1258 we_p->requestsent = jiffies;
1259 list_add_tail(&we_p->liste, &request_list);
1260 ++requestq_count;
1261 we_p->audit[0] |= FP_REQUEST;
1262 break;
1263 case SEN_RETRY:
1264 rv = -ERESTARTSYS;
1265 break;
1266 case SEN_NOT_AVAIL:
1267 PRINTK("*** No devices available.\n");
1268 rv = we_p->retcode = -ENODEV;
1269 we_p->status[0] |= STAT_FAILED;
1270 break;
1271 case REC_OPERAND_INV:
1272 case REC_OPERAND_SIZE:
1273 case REC_EVEN_MOD:
1274 case REC_INVALID_PAD:
1275 rv = we_p->retcode = -EINVAL;
1276 we_p->status[0] |= STAT_FAILED;
1277 break;
1278 default:
1279 we_p->retcode = rv;
1280 we_p->status[0] |= STAT_FAILED;
1281 break;
1282 }
1283 if (rv != -ERESTARTSYS)
1284 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1285 spin_unlock_irq(&queuespinlock);
1286 if (rv == 0)
1287 tasklet_schedule(&reader_tasklet);
1288 return rv;
1289 }
1290
1291 /**
1292 * process_results copies the user's work from kernel space.
1293 */
1294 static inline int
1295 z90crypt_process_results(struct work_element *we_p, char __user *buf)
1296 {
1297 int rv;
1298
1299 PDEBUG("we_p %p (PID %d)\n", we_p, PID());
1300
1301 LONG2DEVPTR(we_p->devindex)->dev_total_req_cnt++;
1302 SET_RDWRMASK(we_p->status[0], STAT_READPEND);
1303
1304 rv = 0;
1305 if (!we_p->buffer) {
1306 PRINTK("we_p %p PID %d in STAT_READPEND: buffer NULL.\n",
1307 we_p, PID());
1308 rv = -ENOBUFF;
1309 }
1310
1311 if (!rv)
1312 if ((rv = copy_to_user(buf, we_p->buffer, we_p->buff_size))) {
1313 PDEBUG("copy_to_user failed: rv = %d\n", rv);
1314 rv = -EFAULT;
1315 }
1316
1317 if (!rv)
1318 rv = we_p->retcode;
1319 if (!rv)
1320 if (we_p->resp_buff_size
1321 && copy_to_user(we_p->resp_addr, we_p->resp_buff,
1322 we_p->resp_buff_size))
1323 rv = -EFAULT;
1324
1325 SET_RDWRMASK(we_p->status[0], STAT_NOWORK);
1326 return rv;
1327 }
1328
1329 static unsigned char NULL_psmid[8] =
1330 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
1331
1332 /**
1333 * Used in device configuration functions
1334 */
1335 #define MAX_RESET 90
1336
1337 /**
1338 * This is used only for PCICC support
1339 */
1340 static inline int
1341 is_PKCS11_padded(unsigned char *buffer, int length)
1342 {
1343 int i;
1344 if ((buffer[0] != 0x00) || (buffer[1] != 0x01))
1345 return 0;
1346 for (i = 2; i < length; i++)
1347 if (buffer[i] != 0xFF)
1348 break;
1349 if ((i < 10) || (i == length))
1350 return 0;
1351 if (buffer[i] != 0x00)
1352 return 0;
1353 return 1;
1354 }
1355
1356 /**
1357 * This is used only for PCICC support
1358 */
1359 static inline int
1360 is_PKCS12_padded(unsigned char *buffer, int length)
1361 {
1362 int i;
1363 if ((buffer[0] != 0x00) || (buffer[1] != 0x02))
1364 return 0;
1365 for (i = 2; i < length; i++)
1366 if (buffer[i] == 0x00)
1367 break;
1368 if ((i < 10) || (i == length))
1369 return 0;
1370 if (buffer[i] != 0x00)
1371 return 0;
1372 return 1;
1373 }
1374
1375 /**
1376 * builds struct caller and converts message from generic format to
1377 * device-dependent format
1378 * func is ICARSAMODEXPO or ICARSACRT
1379 * function is PCI_FUNC_KEY_ENCRYPT or PCI_FUNC_KEY_DECRYPT
1380 */
1381 static inline int
1382 build_caller(struct work_element *we_p, short function)
1383 {
1384 int rv;
1385 struct caller *caller_p = (struct caller *)we_p->requestptr;
1386
1387 if ((we_p->devtype != PCICC) && (we_p->devtype != PCICA) &&
1388 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1389 (we_p->devtype != CEX2C) && (we_p->devtype != CEX2A))
1390 return SEN_NOT_AVAIL;
1391
1392 memcpy(caller_p->caller_id, we_p->caller_id,
1393 sizeof(caller_p->caller_id));
1394 caller_p->caller_dev_dep_req_p = caller_p->caller_dev_dep_req;
1395 caller_p->caller_dev_dep_req_l = MAX_RESPONSE_SIZE;
1396 caller_p->caller_buf_p = we_p->buffer;
1397 INIT_LIST_HEAD(&(caller_p->caller_liste));
1398
1399 rv = convert_request(we_p->buffer, we_p->funccode, function,
1400 z90crypt.cdx, we_p->devtype,
1401 &caller_p->caller_dev_dep_req_l,
1402 caller_p->caller_dev_dep_req_p);
1403 if (rv) {
1404 if (rv == SEN_NOT_AVAIL)
1405 PDEBUG("request can't be processed on hdwr avail\n");
1406 else
1407 PRINTK("Error from convert_request: %d\n", rv);
1408 }
1409 else
1410 memcpy(&(caller_p->caller_dev_dep_req_p[4]), we_p->caller_id,8);
1411 return rv;
1412 }
1413
1414 static inline void
1415 unbuild_caller(struct device *device_p, struct caller *caller_p)
1416 {
1417 if (!caller_p)
1418 return;
1419 if (caller_p->caller_liste.next && caller_p->caller_liste.prev)
1420 if (!list_empty(&caller_p->caller_liste)) {
1421 list_del_init(&caller_p->caller_liste);
1422 device_p->dev_caller_count--;
1423 }
1424 memset(caller_p->caller_id, 0, sizeof(caller_p->caller_id));
1425 }
1426
1427 static inline int
1428 get_crypto_request_buffer(struct work_element *we_p)
1429 {
1430 struct ica_rsa_modexpo *mex_p;
1431 struct ica_rsa_modexpo_crt *crt_p;
1432 unsigned char *temp_buffer;
1433 short function;
1434 int rv;
1435
1436 mex_p = (struct ica_rsa_modexpo *) we_p->buffer;
1437 crt_p = (struct ica_rsa_modexpo_crt *) we_p->buffer;
1438
1439 PDEBUG("device type input = %d\n", we_p->devtype);
1440
1441 if (z90crypt.terminating)
1442 return REC_NO_RESPONSE;
1443 if (memcmp(we_p->caller_id, NULL_psmid, 8) == 0) {
1444 PRINTK("psmid zeroes\n");
1445 return SEN_FATAL_ERROR;
1446 }
1447 if (!we_p->buffer) {
1448 PRINTK("buffer pointer NULL\n");
1449 return SEN_USER_ERROR;
1450 }
1451 if (!we_p->requestptr) {
1452 PRINTK("caller pointer NULL\n");
1453 return SEN_USER_ERROR;
1454 }
1455
1456 if ((we_p->devtype != PCICA) && (we_p->devtype != PCICC) &&
1457 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1458 (we_p->devtype != CEX2C) && (we_p->devtype != CEX2A) &&
1459 (we_p->devtype != ANYDEV)) {
1460 PRINTK("invalid device type\n");
1461 return SEN_USER_ERROR;
1462 }
1463
1464 if ((mex_p->inputdatalength < 1) ||
1465 (mex_p->inputdatalength > MAX_MOD_SIZE)) {
1466 PRINTK("inputdatalength[%d] is not valid\n",
1467 mex_p->inputdatalength);
1468 return SEN_USER_ERROR;
1469 }
1470
1471 if (mex_p->outputdatalength < mex_p->inputdatalength) {
1472 PRINTK("outputdatalength[%d] < inputdatalength[%d]\n",
1473 mex_p->outputdatalength, mex_p->inputdatalength);
1474 return SEN_USER_ERROR;
1475 }
1476
1477 if (!mex_p->inputdata || !mex_p->outputdata) {
1478 PRINTK("inputdata[%p] or outputdata[%p] is NULL\n",
1479 mex_p->outputdata, mex_p->inputdata);
1480 return SEN_USER_ERROR;
1481 }
1482
1483 /**
1484 * As long as outputdatalength is big enough, we can set the
1485 * outputdatalength equal to the inputdatalength, since that is the
1486 * number of bytes we will copy in any case
1487 */
1488 mex_p->outputdatalength = mex_p->inputdatalength;
1489
1490 rv = 0;
1491 switch (we_p->funccode) {
1492 case ICARSAMODEXPO:
1493 if (!mex_p->b_key || !mex_p->n_modulus)
1494 rv = SEN_USER_ERROR;
1495 break;
1496 case ICARSACRT:
1497 if (!IS_EVEN(crt_p->inputdatalength)) {
1498 PRINTK("inputdatalength[%d] is odd, CRT form\n",
1499 crt_p->inputdatalength);
1500 rv = SEN_USER_ERROR;
1501 break;
1502 }
1503 if (!crt_p->bp_key ||
1504 !crt_p->bq_key ||
1505 !crt_p->np_prime ||
1506 !crt_p->nq_prime ||
1507 !crt_p->u_mult_inv) {
1508 PRINTK("CRT form, bad data: %p/%p/%p/%p/%p\n",
1509 crt_p->bp_key, crt_p->bq_key,
1510 crt_p->np_prime, crt_p->nq_prime,
1511 crt_p->u_mult_inv);
1512 rv = SEN_USER_ERROR;
1513 }
1514 break;
1515 default:
1516 PRINTK("bad func = %d\n", we_p->funccode);
1517 rv = SEN_USER_ERROR;
1518 break;
1519 }
1520 if (rv != 0)
1521 return rv;
1522
1523 if (select_device_type(&we_p->devtype, mex_p->inputdatalength) < 0)
1524 return SEN_NOT_AVAIL;
1525
1526 temp_buffer = (unsigned char *)we_p + sizeof(struct work_element) +
1527 sizeof(struct caller);
1528 if (copy_from_user(temp_buffer, mex_p->inputdata,
1529 mex_p->inputdatalength) != 0)
1530 return SEN_RELEASED;
1531
1532 function = PCI_FUNC_KEY_ENCRYPT;
1533 switch (we_p->devtype) {
1534 /* PCICA and CEX2A do everything with a simple RSA mod-expo operation */
1535 case PCICA:
1536 case CEX2A:
1537 function = PCI_FUNC_KEY_ENCRYPT;
1538 break;
1539 /**
1540 * PCIXCC_MCL2 does all Mod-Expo form with a simple RSA mod-expo
1541 * operation, and all CRT forms with a PKCS-1.2 format decrypt.
1542 * PCIXCC_MCL3 and CEX2C do all Mod-Expo and CRT forms with a simple RSA
1543 * mod-expo operation
1544 */
1545 case PCIXCC_MCL2:
1546 if (we_p->funccode == ICARSAMODEXPO)
1547 function = PCI_FUNC_KEY_ENCRYPT;
1548 else
1549 function = PCI_FUNC_KEY_DECRYPT;
1550 break;
1551 case PCIXCC_MCL3:
1552 case CEX2C:
1553 if (we_p->funccode == ICARSAMODEXPO)
1554 function = PCI_FUNC_KEY_ENCRYPT;
1555 else
1556 function = PCI_FUNC_KEY_DECRYPT;
1557 break;
1558 /**
1559 * PCICC does everything as a PKCS-1.2 format request
1560 */
1561 case PCICC:
1562 /* PCICC cannot handle input that is is PKCS#1.1 padded */
1563 if (is_PKCS11_padded(temp_buffer, mex_p->inputdatalength)) {
1564 return SEN_NOT_AVAIL;
1565 }
1566 if (we_p->funccode == ICARSAMODEXPO) {
1567 if (is_PKCS12_padded(temp_buffer,
1568 mex_p->inputdatalength))
1569 function = PCI_FUNC_KEY_ENCRYPT;
1570 else
1571 function = PCI_FUNC_KEY_DECRYPT;
1572 } else
1573 /* all CRT forms are decrypts */
1574 function = PCI_FUNC_KEY_DECRYPT;
1575 break;
1576 }
1577 PDEBUG("function: %04x\n", function);
1578 rv = build_caller(we_p, function);
1579 PDEBUG("rv from build_caller = %d\n", rv);
1580 return rv;
1581 }
1582
1583 static inline int
1584 z90crypt_prepare(struct work_element *we_p, unsigned int funccode,
1585 const char __user *buffer)
1586 {
1587 int rv;
1588
1589 we_p->devindex = -1;
1590 if (funccode == ICARSAMODEXPO)
1591 we_p->buff_size = sizeof(struct ica_rsa_modexpo);
1592 else
1593 we_p->buff_size = sizeof(struct ica_rsa_modexpo_crt);
1594
1595 if (copy_from_user(we_p->buffer, buffer, we_p->buff_size))
1596 return -EFAULT;
1597
1598 we_p->audit[0] |= FP_COPYFROM;
1599 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1600 we_p->funccode = funccode;
1601 we_p->devtype = -1;
1602 we_p->audit[0] |= FP_BUFFREQ;
1603 rv = get_crypto_request_buffer(we_p);
1604 switch (rv) {
1605 case 0:
1606 we_p->audit[0] |= FP_BUFFGOT;
1607 break;
1608 case SEN_USER_ERROR:
1609 rv = -EINVAL;
1610 break;
1611 case SEN_QUEUE_FULL:
1612 rv = 0;
1613 break;
1614 case SEN_RELEASED:
1615 rv = -EFAULT;
1616 break;
1617 case REC_NO_RESPONSE:
1618 rv = -ENODEV;
1619 break;
1620 case SEN_NOT_AVAIL:
1621 case EGETBUFF:
1622 rv = -EGETBUFF;
1623 break;
1624 default:
1625 PRINTK("rv = %d\n", rv);
1626 rv = -EGETBUFF;
1627 break;
1628 }
1629 if (CHK_RDWRMASK(we_p->status[0]) == STAT_WRITTEN)
1630 SET_RDWRMASK(we_p->status[0], STAT_DEFAULT);
1631 return rv;
1632 }
1633
1634 static inline void
1635 purge_work_element(struct work_element *we_p)
1636 {
1637 struct list_head *lptr;
1638
1639 spin_lock_irq(&queuespinlock);
1640 list_for_each(lptr, &request_list) {
1641 if (lptr == &we_p->liste) {
1642 list_del_init(lptr);
1643 requestq_count--;
1644 break;
1645 }
1646 }
1647 list_for_each(lptr, &pending_list) {
1648 if (lptr == &we_p->liste) {
1649 list_del_init(lptr);
1650 pendingq_count--;
1651 break;
1652 }
1653 }
1654 spin_unlock_irq(&queuespinlock);
1655 }
1656
1657 /**
1658 * Build the request and send it.
1659 */
1660 static inline int
1661 z90crypt_rsa(struct priv_data *private_data_p, pid_t pid,
1662 unsigned int cmd, unsigned long arg)
1663 {
1664 struct work_element *we_p;
1665 int rv;
1666
1667 if ((rv = allocate_work_element(&we_p, private_data_p, pid))) {
1668 PDEBUG("PID %d: allocate_work_element returned ENOMEM\n", pid);
1669 return rv;
1670 }
1671 if ((rv = z90crypt_prepare(we_p, cmd, (const char __user *)arg)))
1672 PDEBUG("PID %d: rv = %d from z90crypt_prepare\n", pid, rv);
1673 if (!rv)
1674 if ((rv = z90crypt_send(we_p, (const char *)arg)))
1675 PDEBUG("PID %d: rv %d from z90crypt_send.\n", pid, rv);
1676 if (!rv) {
1677 we_p->audit[0] |= FP_ASLEEP;
1678 wait_event(we_p->waitq, atomic_read(&we_p->alarmrung));
1679 we_p->audit[0] |= FP_AWAKE;
1680 rv = we_p->retcode;
1681 }
1682 if (!rv)
1683 rv = z90crypt_process_results(we_p, (char __user *)arg);
1684
1685 if ((we_p->status[0] & STAT_FAILED)) {
1686 switch (rv) {
1687 /**
1688 * EINVAL *after* receive is almost always a padding error or
1689 * length error issued by a coprocessor (not an accelerator).
1690 * We convert this return value to -EGETBUFF which should
1691 * trigger a fallback to software.
1692 */
1693 case -EINVAL:
1694 if ((we_p->devtype != PCICA) &&
1695 (we_p->devtype != CEX2A))
1696 rv = -EGETBUFF;
1697 break;
1698 case -ETIMEOUT:
1699 if (z90crypt.mask.st_count > 0)
1700 rv = -ERESTARTSYS; // retry with another
1701 else
1702 rv = -ENODEV; // no cards left
1703 /* fall through to clean up request queue */
1704 case -ERESTARTSYS:
1705 case -ERELEASED:
1706 switch (CHK_RDWRMASK(we_p->status[0])) {
1707 case STAT_WRITTEN:
1708 purge_work_element(we_p);
1709 break;
1710 case STAT_READPEND:
1711 case STAT_NOWORK:
1712 default:
1713 break;
1714 }
1715 break;
1716 default:
1717 we_p->status[0] ^= STAT_FAILED;
1718 break;
1719 }
1720 }
1721 free_page((long)we_p);
1722 return rv;
1723 }
1724
1725 /**
1726 * This function is a little long, but it's really just one large switch
1727 * statement.
1728 */
1729 static long
1730 z90crypt_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1731 {
1732 struct priv_data *private_data_p = filp->private_data;
1733 unsigned char *status;
1734 unsigned char *qdepth;
1735 unsigned int *reqcnt;
1736 struct ica_z90_status *pstat;
1737 int ret, i, loopLim, tempstat;
1738 static int deprecated_msg_count1 = 0;
1739 static int deprecated_msg_count2 = 0;
1740
1741 PDEBUG("filp %p (PID %d), cmd 0x%08X\n", filp, PID(), cmd);
1742 PDEBUG("cmd 0x%08X: dir %s, size 0x%04X, type 0x%02X, nr 0x%02X\n",
1743 cmd,
1744 !_IOC_DIR(cmd) ? "NO"
1745 : ((_IOC_DIR(cmd) == (_IOC_READ|_IOC_WRITE)) ? "RW"
1746 : ((_IOC_DIR(cmd) == _IOC_READ) ? "RD"
1747 : "WR")),
1748 _IOC_SIZE(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd));
1749
1750 if (_IOC_TYPE(cmd) != Z90_IOCTL_MAGIC) {
1751 PRINTK("cmd 0x%08X contains bad magic\n", cmd);
1752 return -ENOTTY;
1753 }
1754
1755 ret = 0;
1756 switch (cmd) {
1757 case ICARSAMODEXPO:
1758 case ICARSACRT:
1759 if (quiesce_z90crypt) {
1760 ret = -EQUIESCE;
1761 break;
1762 }
1763 ret = -ENODEV; // Default if no devices
1764 loopLim = z90crypt.hdware_info->hdware_mask.st_count -
1765 (z90crypt.hdware_info->hdware_mask.disabled_count +
1766 z90crypt.hdware_info->hdware_mask.user_disabled_count);
1767 for (i = 0; i < loopLim; i++) {
1768 ret = z90crypt_rsa(private_data_p, PID(), cmd, arg);
1769 if (ret != -ERESTARTSYS)
1770 break;
1771 }
1772 if (ret == -ERESTARTSYS)
1773 ret = -ENODEV;
1774 break;
1775
1776 case Z90STAT_TOTALCOUNT:
1777 tempstat = get_status_totalcount();
1778 if (copy_to_user((int __user *)arg, &tempstat,sizeof(int)) != 0)
1779 ret = -EFAULT;
1780 break;
1781
1782 case Z90STAT_PCICACOUNT:
1783 tempstat = get_status_PCICAcount();
1784 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1785 ret = -EFAULT;
1786 break;
1787
1788 case Z90STAT_PCICCCOUNT:
1789 tempstat = get_status_PCICCcount();
1790 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1791 ret = -EFAULT;
1792 break;
1793
1794 case Z90STAT_PCIXCCMCL2COUNT:
1795 tempstat = get_status_PCIXCCMCL2count();
1796 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1797 ret = -EFAULT;
1798 break;
1799
1800 case Z90STAT_PCIXCCMCL3COUNT:
1801 tempstat = get_status_PCIXCCMCL3count();
1802 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1803 ret = -EFAULT;
1804 break;
1805
1806 case Z90STAT_CEX2CCOUNT:
1807 tempstat = get_status_CEX2Ccount();
1808 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1809 ret = -EFAULT;
1810 break;
1811
1812 case Z90STAT_CEX2ACOUNT:
1813 tempstat = get_status_CEX2Acount();
1814 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1815 ret = -EFAULT;
1816 break;
1817
1818 case Z90STAT_REQUESTQ_COUNT:
1819 tempstat = get_status_requestq_count();
1820 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1821 ret = -EFAULT;
1822 break;
1823
1824 case Z90STAT_PENDINGQ_COUNT:
1825 tempstat = get_status_pendingq_count();
1826 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1827 ret = -EFAULT;
1828 break;
1829
1830 case Z90STAT_TOTALOPEN_COUNT:
1831 tempstat = get_status_totalopen_count();
1832 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1833 ret = -EFAULT;
1834 break;
1835
1836 case Z90STAT_DOMAIN_INDEX:
1837 tempstat = get_status_domain_index();
1838 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1839 ret = -EFAULT;
1840 break;
1841
1842 case Z90STAT_STATUS_MASK:
1843 status = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1844 if (!status) {
1845 PRINTK("kmalloc for status failed!\n");
1846 ret = -ENOMEM;
1847 break;
1848 }
1849 get_status_status_mask(status);
1850 if (copy_to_user((char __user *) arg, status, Z90CRYPT_NUM_APS)
1851 != 0)
1852 ret = -EFAULT;
1853 kfree(status);
1854 break;
1855
1856 case Z90STAT_QDEPTH_MASK:
1857 qdepth = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1858 if (!qdepth) {
1859 PRINTK("kmalloc for qdepth failed!\n");
1860 ret = -ENOMEM;
1861 break;
1862 }
1863 get_status_qdepth_mask(qdepth);
1864 if (copy_to_user((char __user *) arg, qdepth, Z90CRYPT_NUM_APS) != 0)
1865 ret = -EFAULT;
1866 kfree(qdepth);
1867 break;
1868
1869 case Z90STAT_PERDEV_REQCNT:
1870 reqcnt = kmalloc(sizeof(int) * Z90CRYPT_NUM_APS, GFP_KERNEL);
1871 if (!reqcnt) {
1872 PRINTK("kmalloc for reqcnt failed!\n");
1873 ret = -ENOMEM;
1874 break;
1875 }
1876 get_status_perdevice_reqcnt(reqcnt);
1877 if (copy_to_user((char __user *) arg, reqcnt,
1878 Z90CRYPT_NUM_APS * sizeof(int)) != 0)
1879 ret = -EFAULT;
1880 kfree(reqcnt);
1881 break;
1882
1883 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1884 case ICAZ90STATUS:
1885 if (deprecated_msg_count1 < 20) {
1886 PRINTK("deprecated call to ioctl (ICAZ90STATUS)!\n");
1887 deprecated_msg_count1++;
1888 if (deprecated_msg_count1 == 20)
1889 PRINTK("No longer issuing messages related to "
1890 "deprecated call to ICAZ90STATUS.\n");
1891 }
1892
1893 pstat = kmalloc(sizeof(struct ica_z90_status), GFP_KERNEL);
1894 if (!pstat) {
1895 PRINTK("kmalloc for pstat failed!\n");
1896 ret = -ENOMEM;
1897 break;
1898 }
1899
1900 pstat->totalcount = get_status_totalcount();
1901 pstat->leedslitecount = get_status_PCICAcount();
1902 pstat->leeds2count = get_status_PCICCcount();
1903 pstat->requestqWaitCount = get_status_requestq_count();
1904 pstat->pendingqWaitCount = get_status_pendingq_count();
1905 pstat->totalOpenCount = get_status_totalopen_count();
1906 pstat->cryptoDomain = get_status_domain_index();
1907 get_status_status_mask(pstat->status);
1908 get_status_qdepth_mask(pstat->qdepth);
1909
1910 if (copy_to_user((struct ica_z90_status __user *) arg, pstat,
1911 sizeof(struct ica_z90_status)) != 0)
1912 ret = -EFAULT;
1913 kfree(pstat);
1914 break;
1915
1916 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1917 case Z90STAT_PCIXCCCOUNT:
1918 if (deprecated_msg_count2 < 20) {
1919 PRINTK("deprecated ioctl (Z90STAT_PCIXCCCOUNT)!\n");
1920 deprecated_msg_count2++;
1921 if (deprecated_msg_count2 == 20)
1922 PRINTK("No longer issuing messages about depre"
1923 "cated ioctl Z90STAT_PCIXCCCOUNT.\n");
1924 }
1925
1926 tempstat = get_status_PCIXCCcount();
1927 if (copy_to_user((int *)arg, &tempstat, sizeof(int)) != 0)
1928 ret = -EFAULT;
1929 break;
1930
1931 case Z90QUIESCE:
1932 if (current->euid != 0) {
1933 PRINTK("QUIESCE fails: euid %d\n",
1934 current->euid);
1935 ret = -EACCES;
1936 } else {
1937 PRINTK("QUIESCE device from PID %d\n", PID());
1938 quiesce_z90crypt = 1;
1939 }
1940 break;
1941
1942 default:
1943 /* user passed an invalid IOCTL number */
1944 PDEBUG("cmd 0x%08X contains invalid ioctl code\n", cmd);
1945 ret = -ENOTTY;
1946 break;
1947 }
1948
1949 return ret;
1950 }
1951
1952 static inline int
1953 sprintcl(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1954 {
1955 int hl, i;
1956
1957 hl = 0;
1958 for (i = 0; i < len; i++)
1959 hl += sprintf(outaddr+hl, "%01x", (unsigned int) addr[i]);
1960 hl += sprintf(outaddr+hl, " ");
1961
1962 return hl;
1963 }
1964
1965 static inline int
1966 sprintrw(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1967 {
1968 int hl, inl, c, cx;
1969
1970 hl = sprintf(outaddr, " ");
1971 inl = 0;
1972 for (c = 0; c < (len / 16); c++) {
1973 hl += sprintcl(outaddr+hl, addr+inl, 16);
1974 inl += 16;
1975 }
1976
1977 cx = len%16;
1978 if (cx) {
1979 hl += sprintcl(outaddr+hl, addr+inl, cx);
1980 inl += cx;
1981 }
1982
1983 hl += sprintf(outaddr+hl, "\n");
1984
1985 return hl;
1986 }
1987
1988 static inline int
1989 sprinthx(unsigned char *title, unsigned char *outaddr,
1990 unsigned char *addr, unsigned int len)
1991 {
1992 int hl, inl, r, rx;
1993
1994 hl = sprintf(outaddr, "\n%s\n", title);
1995 inl = 0;
1996 for (r = 0; r < (len / 64); r++) {
1997 hl += sprintrw(outaddr+hl, addr+inl, 64);
1998 inl += 64;
1999 }
2000 rx = len % 64;
2001 if (rx) {
2002 hl += sprintrw(outaddr+hl, addr+inl, rx);
2003 inl += rx;
2004 }
2005
2006 hl += sprintf(outaddr+hl, "\n");
2007
2008 return hl;
2009 }
2010
2011 static inline int
2012 sprinthx4(unsigned char *title, unsigned char *outaddr,
2013 unsigned int *array, unsigned int len)
2014 {
2015 int hl, r;
2016
2017 hl = sprintf(outaddr, "\n%s\n", title);
2018
2019 for (r = 0; r < len; r++) {
2020 if ((r % 8) == 0)
2021 hl += sprintf(outaddr+hl, " ");
2022 hl += sprintf(outaddr+hl, "%08X ", array[r]);
2023 if ((r % 8) == 7)
2024 hl += sprintf(outaddr+hl, "\n");
2025 }
2026
2027 hl += sprintf(outaddr+hl, "\n");
2028
2029 return hl;
2030 }
2031
2032 static int
2033 z90crypt_status(char *resp_buff, char **start, off_t offset,
2034 int count, int *eof, void *data)
2035 {
2036 unsigned char *workarea;
2037 int len;
2038
2039 /* resp_buff is a page. Use the right half for a work area */
2040 workarea = resp_buff+2000;
2041 len = 0;
2042 len += sprintf(resp_buff+len, "\nz90crypt version: %d.%d.%d\n",
2043 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT);
2044 len += sprintf(resp_buff+len, "Cryptographic domain: %d\n",
2045 get_status_domain_index());
2046 len += sprintf(resp_buff+len, "Total device count: %d\n",
2047 get_status_totalcount());
2048 len += sprintf(resp_buff+len, "PCICA count: %d\n",
2049 get_status_PCICAcount());
2050 len += sprintf(resp_buff+len, "PCICC count: %d\n",
2051 get_status_PCICCcount());
2052 len += sprintf(resp_buff+len, "PCIXCC MCL2 count: %d\n",
2053 get_status_PCIXCCMCL2count());
2054 len += sprintf(resp_buff+len, "PCIXCC MCL3 count: %d\n",
2055 get_status_PCIXCCMCL3count());
2056 len += sprintf(resp_buff+len, "CEX2C count: %d\n",
2057 get_status_CEX2Ccount());
2058 len += sprintf(resp_buff+len, "CEX2A count: %d\n",
2059 get_status_CEX2Acount());
2060 len += sprintf(resp_buff+len, "requestq count: %d\n",
2061 get_status_requestq_count());
2062 len += sprintf(resp_buff+len, "pendingq count: %d\n",
2063 get_status_pendingq_count());
2064 len += sprintf(resp_buff+len, "Total open handles: %d\n\n",
2065 get_status_totalopen_count());
2066 len += sprinthx(
2067 "Online devices: 1=PCICA 2=PCICC 3=PCIXCC(MCL2) "
2068 "4=PCIXCC(MCL3) 5=CEX2C 6=CEX2A",
2069 resp_buff+len,
2070 get_status_status_mask(workarea),
2071 Z90CRYPT_NUM_APS);
2072 len += sprinthx("Waiting work element counts",
2073 resp_buff+len,
2074 get_status_qdepth_mask(workarea),
2075 Z90CRYPT_NUM_APS);
2076 len += sprinthx4(
2077 "Per-device successfully completed request counts",
2078 resp_buff+len,
2079 get_status_perdevice_reqcnt((unsigned int *)workarea),
2080 Z90CRYPT_NUM_APS);
2081 *eof = 1;
2082 memset(workarea, 0, Z90CRYPT_NUM_APS * sizeof(unsigned int));
2083 return len;
2084 }
2085
2086 static inline void
2087 disable_card(int card_index)
2088 {
2089 struct device *devp;
2090
2091 devp = LONG2DEVPTR(card_index);
2092 if (!devp || devp->user_disabled)
2093 return;
2094 devp->user_disabled = 1;
2095 z90crypt.hdware_info->hdware_mask.user_disabled_count++;
2096 if (devp->dev_type == -1)
2097 return;
2098 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count++;
2099 }
2100
2101 static inline void
2102 enable_card(int card_index)
2103 {
2104 struct device *devp;
2105
2106 devp = LONG2DEVPTR(card_index);
2107 if (!devp || !devp->user_disabled)
2108 return;
2109 devp->user_disabled = 0;
2110 z90crypt.hdware_info->hdware_mask.user_disabled_count--;
2111 if (devp->dev_type == -1)
2112 return;
2113 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count--;
2114 }
2115
2116 static int
2117 z90crypt_status_write(struct file *file, const char __user *buffer,
2118 unsigned long count, void *data)
2119 {
2120 int j, eol;
2121 unsigned char *lbuf, *ptr;
2122 unsigned int local_count;
2123
2124 #define LBUFSIZE 1200
2125 lbuf = kmalloc(LBUFSIZE, GFP_KERNEL);
2126 if (!lbuf) {
2127 PRINTK("kmalloc failed!\n");
2128 return 0;
2129 }
2130
2131 if (count <= 0)
2132 return 0;
2133
2134 local_count = UMIN((unsigned int)count, LBUFSIZE-1);
2135
2136 if (copy_from_user(lbuf, buffer, local_count) != 0) {
2137 kfree(lbuf);
2138 return -EFAULT;
2139 }
2140
2141 lbuf[local_count] = '\0';
2142
2143 ptr = strstr(lbuf, "Online devices");
2144 if (ptr == 0) {
2145 PRINTK("Unable to parse data (missing \"Online devices\")\n");
2146 kfree(lbuf);
2147 return count;
2148 }
2149
2150 ptr = strstr(ptr, "\n");
2151 if (ptr == 0) {
2152 PRINTK("Unable to parse data (missing newline after \"Online devices\")\n");
2153 kfree(lbuf);
2154 return count;
2155 }
2156 ptr++;
2157
2158 if (strstr(ptr, "Waiting work element counts") == NULL) {
2159 PRINTK("Unable to parse data (missing \"Waiting work element counts\")\n");
2160 kfree(lbuf);
2161 return count;
2162 }
2163
2164 j = 0;
2165 eol = 0;
2166 while ((j < 64) && (*ptr != '\0')) {
2167 switch (*ptr) {
2168 case '\t':
2169 case ' ':
2170 break;
2171 case '\n':
2172 default:
2173 eol = 1;
2174 break;
2175 case '0': // no device
2176 case '1': // PCICA
2177 case '2': // PCICC
2178 case '3': // PCIXCC_MCL2
2179 case '4': // PCIXCC_MCL3
2180 case '5': // CEX2C
2181 case '6': // CEX2A
2182 j++;
2183 break;
2184 case 'd':
2185 case 'D':
2186 disable_card(j);
2187 j++;
2188 break;
2189 case 'e':
2190 case 'E':
2191 enable_card(j);
2192 j++;
2193 break;
2194 }
2195 if (eol)
2196 break;
2197 ptr++;
2198 }
2199
2200 kfree(lbuf);
2201 return count;
2202 }
2203
2204 /**
2205 * Functions that run under a timer, with no process id
2206 *
2207 * The task functions:
2208 * z90crypt_reader_task
2209 * helper_send_work
2210 * helper_handle_work_element
2211 * helper_receive_rc
2212 * z90crypt_config_task
2213 * z90crypt_cleanup_task
2214 *
2215 * Helper functions:
2216 * z90crypt_schedule_reader_timer
2217 * z90crypt_schedule_reader_task
2218 * z90crypt_schedule_config_task
2219 * z90crypt_schedule_cleanup_task
2220 */
2221 static inline int
2222 receive_from_crypto_device(int index, unsigned char *psmid, int *buff_len_p,
2223 unsigned char *buff, unsigned char __user **dest_p_p)
2224 {
2225 int dv, rv;
2226 struct device *dev_ptr;
2227 struct caller *caller_p;
2228 struct ica_rsa_modexpo *icaMsg_p;
2229 struct list_head *ptr, *tptr;
2230
2231 memcpy(psmid, NULL_psmid, sizeof(NULL_psmid));
2232
2233 if (z90crypt.terminating)
2234 return REC_FATAL_ERROR;
2235
2236 caller_p = 0;
2237 dev_ptr = z90crypt.device_p[index];
2238 rv = 0;
2239 do {
2240 if (!dev_ptr || dev_ptr->disabled) {
2241 rv = REC_NO_WORK; // a disabled device can't return work
2242 break;
2243 }
2244 if (dev_ptr->dev_self_x != index) {
2245 PRINTKC("Corrupt dev ptr\n");
2246 z90crypt.terminating = 1;
2247 rv = REC_FATAL_ERROR;
2248 break;
2249 }
2250 if (!dev_ptr->dev_resp_l || !dev_ptr->dev_resp_p) {
2251 dv = DEV_REC_EXCEPTION;
2252 PRINTK("dev_resp_l = %d, dev_resp_p = %p\n",
2253 dev_ptr->dev_resp_l, dev_ptr->dev_resp_p);
2254 } else {
2255 PDEBUG("Dequeue called for device %d\n", index);
2256 dv = receive_from_AP(index, z90crypt.cdx,
2257 dev_ptr->dev_resp_l,
2258 dev_ptr->dev_resp_p, psmid);
2259 }
2260 switch (dv) {
2261 case DEV_REC_EXCEPTION:
2262 rv = REC_FATAL_ERROR;
2263 z90crypt.terminating = 1;
2264 PRINTKC("Exception in receive from device %d\n",
2265 index);
2266 break;
2267 case DEV_ONLINE:
2268 rv = 0;
2269 break;
2270 case DEV_EMPTY:
2271 rv = REC_EMPTY;
2272 break;
2273 case DEV_NO_WORK:
2274 rv = REC_NO_WORK;
2275 break;
2276 case DEV_BAD_MESSAGE:
2277 case DEV_GONE:
2278 case REC_HARDWAR_ERR:
2279 default:
2280 rv = REC_NO_RESPONSE;
2281 break;
2282 }
2283 if (rv)
2284 break;
2285 if (dev_ptr->dev_caller_count <= 0) {
2286 rv = REC_USER_GONE;
2287 break;
2288 }
2289
2290 list_for_each_safe(ptr, tptr, &dev_ptr->dev_caller_list) {
2291 caller_p = list_entry(ptr, struct caller, caller_liste);
2292 if (!memcmp(caller_p->caller_id, psmid,
2293 sizeof(caller_p->caller_id))) {
2294 if (!list_empty(&caller_p->caller_liste)) {
2295 list_del_init(ptr);
2296 dev_ptr->dev_caller_count--;
2297 break;
2298 }
2299 }
2300 caller_p = 0;
2301 }
2302 if (!caller_p) {
2303 PRINTKW("Unable to locate PSMID %02X%02X%02X%02X%02X"
2304 "%02X%02X%02X in device list\n",
2305 psmid[0], psmid[1], psmid[2], psmid[3],
2306 psmid[4], psmid[5], psmid[6], psmid[7]);
2307 rv = REC_USER_GONE;
2308 break;
2309 }
2310
2311 PDEBUG("caller_p after successful receive: %p\n", caller_p);
2312 rv = convert_response(dev_ptr->dev_resp_p,
2313 caller_p->caller_buf_p, buff_len_p, buff);
2314 switch (rv) {
2315 case REC_USE_PCICA:
2316 break;
2317 case REC_OPERAND_INV:
2318 case REC_OPERAND_SIZE:
2319 case REC_EVEN_MOD:
2320 case REC_INVALID_PAD:
2321 PDEBUG("device %d: 'user error' %d\n", index, rv);
2322 break;
2323 case WRONG_DEVICE_TYPE:
2324 case REC_HARDWAR_ERR:
2325 case REC_BAD_MESSAGE:
2326 PRINTKW("device %d: hardware error %d\n", index, rv);
2327 rv = REC_NO_RESPONSE;
2328 break;
2329 default:
2330 PDEBUG("device %d: rv = %d\n", index, rv);
2331 break;
2332 }
2333 } while (0);
2334
2335 switch (rv) {
2336 case 0:
2337 PDEBUG("Successful receive from device %d\n", index);
2338 icaMsg_p = (struct ica_rsa_modexpo *)caller_p->caller_buf_p;
2339 *dest_p_p = icaMsg_p->outputdata;
2340 if (*buff_len_p == 0)
2341 PRINTK("Zero *buff_len_p\n");
2342 break;
2343 case REC_NO_RESPONSE:
2344 PRINTKW("Removing device %d from availability\n", index);
2345 remove_device(dev_ptr);
2346 break;
2347 }
2348
2349 if (caller_p)
2350 unbuild_caller(dev_ptr, caller_p);
2351
2352 return rv;
2353 }
2354
2355 static inline void
2356 helper_send_work(int index)
2357 {
2358 struct work_element *rq_p;
2359 int rv;
2360
2361 if (list_empty(&request_list))
2362 return;
2363 requestq_count--;
2364 rq_p = list_entry(request_list.next, struct work_element, liste);
2365 list_del_init(&rq_p->liste);
2366 rq_p->audit[1] |= FP_REMREQUEST;
2367 if (rq_p->devtype == SHRT2DEVPTR(index)->dev_type) {
2368 rq_p->devindex = SHRT2LONG(index);
2369 rv = send_to_crypto_device(rq_p);
2370 if (rv == 0) {
2371 rq_p->requestsent = jiffies;
2372 rq_p->audit[0] |= FP_SENT;
2373 list_add_tail(&rq_p->liste, &pending_list);
2374 ++pendingq_count;
2375 rq_p->audit[0] |= FP_PENDING;
2376 } else {
2377 switch (rv) {
2378 case REC_OPERAND_INV:
2379 case REC_OPERAND_SIZE:
2380 case REC_EVEN_MOD:
2381 case REC_INVALID_PAD:
2382 rq_p->retcode = -EINVAL;
2383 break;
2384 case SEN_NOT_AVAIL:
2385 case SEN_RETRY:
2386 case REC_NO_RESPONSE:
2387 default:
2388 if (z90crypt.mask.st_count > 1)
2389 rq_p->retcode =
2390 -ERESTARTSYS;
2391 else
2392 rq_p->retcode = -ENODEV;
2393 break;
2394 }
2395 rq_p->status[0] |= STAT_FAILED;
2396 rq_p->audit[1] |= FP_AWAKENING;
2397 atomic_set(&rq_p->alarmrung, 1);
2398 wake_up(&rq_p->waitq);
2399 }
2400 } else {
2401 if (z90crypt.mask.st_count > 1)
2402 rq_p->retcode = -ERESTARTSYS;
2403 else
2404 rq_p->retcode = -ENODEV;
2405 rq_p->status[0] |= STAT_FAILED;
2406 rq_p->audit[1] |= FP_AWAKENING;
2407 atomic_set(&rq_p->alarmrung, 1);
2408 wake_up(&rq_p->waitq);
2409 }
2410 }
2411
2412 static inline void
2413 helper_handle_work_element(int index, unsigned char psmid[8], int rc,
2414 int buff_len, unsigned char *buff,
2415 unsigned char __user *resp_addr)
2416 {
2417 struct work_element *pq_p;
2418 struct list_head *lptr, *tptr;
2419
2420 pq_p = 0;
2421 list_for_each_safe(lptr, tptr, &pending_list) {
2422 pq_p = list_entry(lptr, struct work_element, liste);
2423 if (!memcmp(pq_p->caller_id, psmid, sizeof(pq_p->caller_id))) {
2424 list_del_init(lptr);
2425 pendingq_count--;
2426 pq_p->audit[1] |= FP_NOTPENDING;
2427 break;
2428 }
2429 pq_p = 0;
2430 }
2431
2432 if (!pq_p) {
2433 PRINTK("device %d has work but no caller exists on pending Q\n",
2434 SHRT2LONG(index));
2435 return;
2436 }
2437
2438 switch (rc) {
2439 case 0:
2440 pq_p->resp_buff_size = buff_len;
2441 pq_p->audit[1] |= FP_RESPSIZESET;
2442 if (buff_len) {
2443 pq_p->resp_addr = resp_addr;
2444 pq_p->audit[1] |= FP_RESPADDRCOPIED;
2445 memcpy(pq_p->resp_buff, buff, buff_len);
2446 pq_p->audit[1] |= FP_RESPBUFFCOPIED;
2447 }
2448 break;
2449 case REC_OPERAND_INV:
2450 case REC_OPERAND_SIZE:
2451 case REC_EVEN_MOD:
2452 case REC_INVALID_PAD:
2453 PDEBUG("-EINVAL after application error %d\n", rc);
2454 pq_p->retcode = -EINVAL;
2455 pq_p->status[0] |= STAT_FAILED;
2456 break;
2457 case REC_USE_PCICA:
2458 pq_p->retcode = -ERESTARTSYS;
2459 pq_p->status[0] |= STAT_FAILED;
2460 break;
2461 case REC_NO_RESPONSE:
2462 default:
2463 if (z90crypt.mask.st_count > 1)
2464 pq_p->retcode = -ERESTARTSYS;
2465 else
2466 pq_p->retcode = -ENODEV;
2467 pq_p->status[0] |= STAT_FAILED;
2468 break;
2469 }
2470 if ((pq_p->status[0] != STAT_FAILED) || (pq_p->retcode != -ERELEASED)) {
2471 pq_p->audit[1] |= FP_AWAKENING;
2472 atomic_set(&pq_p->alarmrung, 1);
2473 wake_up(&pq_p->waitq);
2474 }
2475 }
2476
2477 /**
2478 * return TRUE if the work element should be removed from the queue
2479 */
2480 static inline int
2481 helper_receive_rc(int index, int *rc_p)
2482 {
2483 switch (*rc_p) {
2484 case 0:
2485 case REC_OPERAND_INV:
2486 case REC_OPERAND_SIZE:
2487 case REC_EVEN_MOD:
2488 case REC_INVALID_PAD:
2489 case REC_USE_PCICA:
2490 break;
2491
2492 case REC_BUSY:
2493 case REC_NO_WORK:
2494 case REC_EMPTY:
2495 case REC_RETRY_DEV:
2496 case REC_FATAL_ERROR:
2497 return 0;
2498
2499 case REC_NO_RESPONSE:
2500 break;
2501
2502 default:
2503 PRINTK("rc %d, device %d converted to REC_NO_RESPONSE\n",
2504 *rc_p, SHRT2LONG(index));
2505 *rc_p = REC_NO_RESPONSE;
2506 break;
2507 }
2508 return 1;
2509 }
2510
2511 static inline void
2512 z90crypt_schedule_reader_timer(void)
2513 {
2514 if (timer_pending(&reader_timer))
2515 return;
2516 if (mod_timer(&reader_timer, jiffies+(READERTIME*HZ/1000)) != 0)
2517 PRINTK("Timer pending while modifying reader timer\n");
2518 }
2519
2520 static void
2521 z90crypt_reader_task(unsigned long ptr)
2522 {
2523 int workavail, index, rc, buff_len;
2524 unsigned char psmid[8];
2525 unsigned char __user *resp_addr;
2526 static unsigned char buff[1024];
2527
2528 /**
2529 * we use workavail = 2 to ensure 2 passes with nothing dequeued before
2530 * exiting the loop. If (pendingq_count+requestq_count) == 0 after the
2531 * loop, there is no work remaining on the queues.
2532 */
2533 resp_addr = 0;
2534 workavail = 2;
2535 buff_len = 0;
2536 while (workavail) {
2537 workavail--;
2538 rc = 0;
2539 spin_lock_irq(&queuespinlock);
2540 memset(buff, 0x00, sizeof(buff));
2541
2542 /* Dequeue once from each device in round robin. */
2543 for (index = 0; index < z90crypt.mask.st_count; index++) {
2544 PDEBUG("About to receive.\n");
2545 rc = receive_from_crypto_device(SHRT2LONG(index),
2546 psmid,
2547 &buff_len,
2548 buff,
2549 &resp_addr);
2550 PDEBUG("Dequeued: rc = %d.\n", rc);
2551
2552 if (helper_receive_rc(index, &rc)) {
2553 if (rc != REC_NO_RESPONSE) {
2554 helper_send_work(index);
2555 workavail = 2;
2556 }
2557
2558 helper_handle_work_element(index, psmid, rc,
2559 buff_len, buff,
2560 resp_addr);
2561 }
2562
2563 if (rc == REC_FATAL_ERROR)
2564 PRINTKW("REC_FATAL_ERROR from device %d!\n",
2565 SHRT2LONG(index));
2566 }
2567 spin_unlock_irq(&queuespinlock);
2568 }
2569
2570 if (pendingq_count + requestq_count)
2571 z90crypt_schedule_reader_timer();
2572 }
2573
2574 static inline void
2575 z90crypt_schedule_config_task(unsigned int expiration)
2576 {
2577 if (timer_pending(&config_timer))
2578 return;
2579 if (mod_timer(&config_timer, jiffies+(expiration*HZ)) != 0)
2580 PRINTK("Timer pending while modifying config timer\n");
2581 }
2582
2583 static void
2584 z90crypt_config_task(unsigned long ptr)
2585 {
2586 int rc;
2587
2588 PDEBUG("jiffies %ld\n", jiffies);
2589
2590 if ((rc = refresh_z90crypt(&z90crypt.cdx)))
2591 PRINTK("Error %d detected in refresh_z90crypt.\n", rc);
2592 /* If return was fatal, don't bother reconfiguring */
2593 if ((rc != TSQ_FATAL_ERROR) && (rc != RSQ_FATAL_ERROR))
2594 z90crypt_schedule_config_task(CONFIGTIME);
2595 }
2596
2597 static inline void
2598 z90crypt_schedule_cleanup_task(void)
2599 {
2600 if (timer_pending(&cleanup_timer))
2601 return;
2602 if (mod_timer(&cleanup_timer, jiffies+(CLEANUPTIME*HZ)) != 0)
2603 PRINTK("Timer pending while modifying cleanup timer\n");
2604 }
2605
2606 static inline void
2607 helper_drain_queues(void)
2608 {
2609 struct work_element *pq_p;
2610 struct list_head *lptr, *tptr;
2611
2612 list_for_each_safe(lptr, tptr, &pending_list) {
2613 pq_p = list_entry(lptr, struct work_element, liste);
2614 pq_p->retcode = -ENODEV;
2615 pq_p->status[0] |= STAT_FAILED;
2616 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2617 (struct caller *)pq_p->requestptr);
2618 list_del_init(lptr);
2619 pendingq_count--;
2620 pq_p->audit[1] |= FP_NOTPENDING;
2621 pq_p->audit[1] |= FP_AWAKENING;
2622 atomic_set(&pq_p->alarmrung, 1);
2623 wake_up(&pq_p->waitq);
2624 }
2625
2626 list_for_each_safe(lptr, tptr, &request_list) {
2627 pq_p = list_entry(lptr, struct work_element, liste);
2628 pq_p->retcode = -ENODEV;
2629 pq_p->status[0] |= STAT_FAILED;
2630 list_del_init(lptr);
2631 requestq_count--;
2632 pq_p->audit[1] |= FP_REMREQUEST;
2633 pq_p->audit[1] |= FP_AWAKENING;
2634 atomic_set(&pq_p->alarmrung, 1);
2635 wake_up(&pq_p->waitq);
2636 }
2637 }
2638
2639 static inline void
2640 helper_timeout_requests(void)
2641 {
2642 struct work_element *pq_p;
2643 struct list_head *lptr, *tptr;
2644 long timelimit;
2645
2646 timelimit = jiffies - (CLEANUPTIME * HZ);
2647 /* The list is in strict chronological order */
2648 list_for_each_safe(lptr, tptr, &pending_list) {
2649 pq_p = list_entry(lptr, struct work_element, liste);
2650 if (pq_p->requestsent >= timelimit)
2651 break;
2652 PRINTKW("Purging(PQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2653 ((struct caller *)pq_p->requestptr)->caller_id[0],
2654 ((struct caller *)pq_p->requestptr)->caller_id[1],
2655 ((struct caller *)pq_p->requestptr)->caller_id[2],
2656 ((struct caller *)pq_p->requestptr)->caller_id[3],
2657 ((struct caller *)pq_p->requestptr)->caller_id[4],
2658 ((struct caller *)pq_p->requestptr)->caller_id[5],
2659 ((struct caller *)pq_p->requestptr)->caller_id[6],
2660 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2661 pq_p->retcode = -ETIMEOUT;
2662 pq_p->status[0] |= STAT_FAILED;
2663 /* get this off any caller queue it may be on */
2664 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2665 (struct caller *) pq_p->requestptr);
2666 list_del_init(lptr);
2667 pendingq_count--;
2668 pq_p->audit[1] |= FP_TIMEDOUT;
2669 pq_p->audit[1] |= FP_NOTPENDING;
2670 pq_p->audit[1] |= FP_AWAKENING;
2671 atomic_set(&pq_p->alarmrung, 1);
2672 wake_up(&pq_p->waitq);
2673 }
2674
2675 /**
2676 * If pending count is zero, items left on the request queue may
2677 * never be processed.
2678 */
2679 if (pendingq_count <= 0) {
2680 list_for_each_safe(lptr, tptr, &request_list) {
2681 pq_p = list_entry(lptr, struct work_element, liste);
2682 if (pq_p->requestsent >= timelimit)
2683 break;
2684 PRINTKW("Purging(RQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2685 ((struct caller *)pq_p->requestptr)->caller_id[0],
2686 ((struct caller *)pq_p->requestptr)->caller_id[1],
2687 ((struct caller *)pq_p->requestptr)->caller_id[2],
2688 ((struct caller *)pq_p->requestptr)->caller_id[3],
2689 ((struct caller *)pq_p->requestptr)->caller_id[4],
2690 ((struct caller *)pq_p->requestptr)->caller_id[5],
2691 ((struct caller *)pq_p->requestptr)->caller_id[6],
2692 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2693 pq_p->retcode = -ETIMEOUT;
2694 pq_p->status[0] |= STAT_FAILED;
2695 list_del_init(lptr);
2696 requestq_count--;
2697 pq_p->audit[1] |= FP_TIMEDOUT;
2698 pq_p->audit[1] |= FP_REMREQUEST;
2699 pq_p->audit[1] |= FP_AWAKENING;
2700 atomic_set(&pq_p->alarmrung, 1);
2701 wake_up(&pq_p->waitq);
2702 }
2703 }
2704 }
2705
2706 static void
2707 z90crypt_cleanup_task(unsigned long ptr)
2708 {
2709 PDEBUG("jiffies %ld\n", jiffies);
2710 spin_lock_irq(&queuespinlock);
2711 if (z90crypt.mask.st_count <= 0) // no devices!
2712 helper_drain_queues();
2713 else
2714 helper_timeout_requests();
2715 spin_unlock_irq(&queuespinlock);
2716 z90crypt_schedule_cleanup_task();
2717 }
2718
2719 static void
2720 z90crypt_schedule_reader_task(unsigned long ptr)
2721 {
2722 tasklet_schedule(&reader_tasklet);
2723 }
2724
2725 /**
2726 * Lowlevel Functions:
2727 *
2728 * create_z90crypt: creates and initializes basic data structures
2729 * refresh_z90crypt: re-initializes basic data structures
2730 * find_crypto_devices: returns a count and mask of hardware status
2731 * create_crypto_device: builds the descriptor for a device
2732 * destroy_crypto_device: unallocates the descriptor for a device
2733 * destroy_z90crypt: drains all work, unallocates structs
2734 */
2735
2736 /**
2737 * build the z90crypt root structure using the given domain index
2738 */
2739 static int
2740 create_z90crypt(int *cdx_p)
2741 {
2742 struct hdware_block *hdware_blk_p;
2743
2744 memset(&z90crypt, 0x00, sizeof(struct z90crypt));
2745 z90crypt.domain_established = 0;
2746 z90crypt.len = sizeof(struct z90crypt);
2747 z90crypt.max_count = Z90CRYPT_NUM_DEVS;
2748 z90crypt.cdx = *cdx_p;
2749
2750 hdware_blk_p = (struct hdware_block *)
2751 kmalloc(sizeof(struct hdware_block), GFP_ATOMIC);
2752 if (!hdware_blk_p) {
2753 PDEBUG("kmalloc for hardware block failed\n");
2754 return ENOMEM;
2755 }
2756 memset(hdware_blk_p, 0x00, sizeof(struct hdware_block));
2757 z90crypt.hdware_info = hdware_blk_p;
2758
2759 return 0;
2760 }
2761
2762 static inline int
2763 helper_scan_devices(int cdx_array[16], int *cdx_p, int *correct_cdx_found)
2764 {
2765 enum hdstat hd_stat;
2766 int q_depth, dev_type;
2767 int indx, chkdom, numdomains;
2768
2769 q_depth = dev_type = numdomains = 0;
2770 for (chkdom = 0; chkdom <= 15; cdx_array[chkdom++] = -1);
2771 for (indx = 0; indx < z90crypt.max_count; indx++) {
2772 hd_stat = HD_NOT_THERE;
2773 numdomains = 0;
2774 for (chkdom = 0; chkdom <= 15; chkdom++) {
2775 hd_stat = query_online(indx, chkdom, MAX_RESET,
2776 &q_depth, &dev_type);
2777 if (hd_stat == HD_TSQ_EXCEPTION) {
2778 z90crypt.terminating = 1;
2779 PRINTKC("exception taken!\n");
2780 break;
2781 }
2782 if (hd_stat == HD_ONLINE) {
2783 cdx_array[numdomains++] = chkdom;
2784 if (*cdx_p == chkdom) {
2785 *correct_cdx_found = 1;
2786 break;
2787 }
2788 }
2789 }
2790 if ((*correct_cdx_found == 1) || (numdomains != 0))
2791 break;
2792 if (z90crypt.terminating)
2793 break;
2794 }
2795 return numdomains;
2796 }
2797
2798 static inline int
2799 probe_crypto_domain(int *cdx_p)
2800 {
2801 int cdx_array[16];
2802 char cdx_array_text[53], temp[5];
2803 int correct_cdx_found, numdomains;
2804
2805 correct_cdx_found = 0;
2806 numdomains = helper_scan_devices(cdx_array, cdx_p, &correct_cdx_found);
2807
2808 if (z90crypt.terminating)
2809 return TSQ_FATAL_ERROR;
2810
2811 if (correct_cdx_found)
2812 return 0;
2813
2814 if (numdomains == 0) {
2815 PRINTKW("Unable to find crypto domain: No devices found\n");
2816 return Z90C_NO_DEVICES;
2817 }
2818
2819 if (numdomains == 1) {
2820 if (*cdx_p == -1) {
2821 *cdx_p = cdx_array[0];
2822 return 0;
2823 }
2824 PRINTKW("incorrect domain: specified = %d, found = %d\n",
2825 *cdx_p, cdx_array[0]);
2826 return Z90C_INCORRECT_DOMAIN;
2827 }
2828
2829 numdomains--;
2830 sprintf(cdx_array_text, "%d", cdx_array[numdomains]);
2831 while (numdomains) {
2832 numdomains--;
2833 sprintf(temp, ", %d", cdx_array[numdomains]);
2834 strcat(cdx_array_text, temp);
2835 }
2836
2837 PRINTKW("ambiguous domain detected: specified = %d, found array = %s\n",
2838 *cdx_p, cdx_array_text);
2839 return Z90C_AMBIGUOUS_DOMAIN;
2840 }
2841
2842 static int
2843 refresh_z90crypt(int *cdx_p)
2844 {
2845 int i, j, indx, rv;
2846 static struct status local_mask;
2847 struct device *devPtr;
2848 unsigned char oldStat, newStat;
2849 int return_unchanged;
2850
2851 if (z90crypt.len != sizeof(z90crypt))
2852 return ENOTINIT;
2853 if (z90crypt.terminating)
2854 return TSQ_FATAL_ERROR;
2855 rv = 0;
2856 if (!z90crypt.hdware_info->hdware_mask.st_count &&
2857 !z90crypt.domain_established) {
2858 rv = probe_crypto_domain(cdx_p);
2859 if (z90crypt.terminating)
2860 return TSQ_FATAL_ERROR;
2861 if (rv == Z90C_NO_DEVICES)
2862 return 0; // try later
2863 if (rv)
2864 return rv;
2865 z90crypt.cdx = *cdx_p;
2866 z90crypt.domain_established = 1;
2867 }
2868 rv = find_crypto_devices(&local_mask);
2869 if (rv) {
2870 PRINTK("find crypto devices returned %d\n", rv);
2871 return rv;
2872 }
2873 if (!memcmp(&local_mask, &z90crypt.hdware_info->hdware_mask,
2874 sizeof(struct status))) {
2875 return_unchanged = 1;
2876 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++) {
2877 /**
2878 * Check for disabled cards. If any device is marked
2879 * disabled, destroy it.
2880 */
2881 for (j = 0;
2882 j < z90crypt.hdware_info->type_mask[i].st_count;
2883 j++) {
2884 indx = z90crypt.hdware_info->type_x_addr[i].
2885 device_index[j];
2886 devPtr = z90crypt.device_p[indx];
2887 if (devPtr && devPtr->disabled) {
2888 local_mask.st_mask[indx] = HD_NOT_THERE;
2889 return_unchanged = 0;
2890 }
2891 }
2892 }
2893 if (return_unchanged == 1)
2894 return 0;
2895 }
2896
2897 spin_lock_irq(&queuespinlock);
2898 for (i = 0; i < z90crypt.max_count; i++) {
2899 oldStat = z90crypt.hdware_info->hdware_mask.st_mask[i];
2900 newStat = local_mask.st_mask[i];
2901 if ((oldStat == HD_ONLINE) && (newStat != HD_ONLINE))
2902 destroy_crypto_device(i);
2903 else if ((oldStat != HD_ONLINE) && (newStat == HD_ONLINE)) {
2904 rv = create_crypto_device(i);
2905 if (rv >= REC_FATAL_ERROR)
2906 return rv;
2907 if (rv != 0) {
2908 local_mask.st_mask[i] = HD_NOT_THERE;
2909 local_mask.st_count--;
2910 }
2911 }
2912 }
2913 memcpy(z90crypt.hdware_info->hdware_mask.st_mask, local_mask.st_mask,
2914 sizeof(local_mask.st_mask));
2915 z90crypt.hdware_info->hdware_mask.st_count = local_mask.st_count;
2916 z90crypt.hdware_info->hdware_mask.disabled_count =
2917 local_mask.disabled_count;
2918 refresh_index_array(&z90crypt.mask, &z90crypt.overall_device_x);
2919 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++)
2920 refresh_index_array(&(z90crypt.hdware_info->type_mask[i]),
2921 &(z90crypt.hdware_info->type_x_addr[i]));
2922 spin_unlock_irq(&queuespinlock);
2923
2924 return rv;
2925 }
2926
2927 static int
2928 find_crypto_devices(struct status *deviceMask)
2929 {
2930 int i, q_depth, dev_type;
2931 enum hdstat hd_stat;
2932
2933 deviceMask->st_count = 0;
2934 deviceMask->disabled_count = 0;
2935 deviceMask->user_disabled_count = 0;
2936
2937 for (i = 0; i < z90crypt.max_count; i++) {
2938 hd_stat = query_online(i, z90crypt.cdx, MAX_RESET, &q_depth,
2939 &dev_type);
2940 if (hd_stat == HD_TSQ_EXCEPTION) {
2941 z90crypt.terminating = 1;
2942 PRINTKC("Exception during probe for crypto devices\n");
2943 return TSQ_FATAL_ERROR;
2944 }
2945 deviceMask->st_mask[i] = hd_stat;
2946 if (hd_stat == HD_ONLINE) {
2947 PDEBUG("Got an online crypto!: %d\n", i);
2948 PDEBUG("Got a queue depth of %d\n", q_depth);
2949 PDEBUG("Got a device type of %d\n", dev_type);
2950 if (q_depth <= 0)
2951 return TSQ_FATAL_ERROR;
2952 deviceMask->st_count++;
2953 z90crypt.q_depth_array[i] = q_depth;
2954 z90crypt.dev_type_array[i] = dev_type;
2955 }
2956 }
2957
2958 return 0;
2959 }
2960
2961 static int
2962 refresh_index_array(struct status *status_str, struct device_x *index_array)
2963 {
2964 int i, count;
2965 enum devstat stat;
2966
2967 i = -1;
2968 count = 0;
2969 do {
2970 stat = status_str->st_mask[++i];
2971 if (stat == DEV_ONLINE)
2972 index_array->device_index[count++] = i;
2973 } while ((i < Z90CRYPT_NUM_DEVS) && (count < status_str->st_count));
2974
2975 return count;
2976 }
2977
2978 static int
2979 create_crypto_device(int index)
2980 {
2981 int rv, devstat, total_size;
2982 struct device *dev_ptr;
2983 struct status *type_str_p;
2984 int deviceType;
2985
2986 dev_ptr = z90crypt.device_p[index];
2987 if (!dev_ptr) {
2988 total_size = sizeof(struct device) +
2989 z90crypt.q_depth_array[index] * sizeof(int);
2990
2991 dev_ptr = (struct device *) kmalloc(total_size, GFP_ATOMIC);
2992 if (!dev_ptr) {
2993 PRINTK("kmalloc device %d failed\n", index);
2994 return ENOMEM;
2995 }
2996 memset(dev_ptr, 0, total_size);
2997 dev_ptr->dev_resp_p = kmalloc(MAX_RESPONSE_SIZE, GFP_ATOMIC);
2998 if (!dev_ptr->dev_resp_p) {
2999 kfree(dev_ptr);
3000 PRINTK("kmalloc device %d rec buffer failed\n", index);
3001 return ENOMEM;
3002 }
3003 dev_ptr->dev_resp_l = MAX_RESPONSE_SIZE;
3004 INIT_LIST_HEAD(&(dev_ptr->dev_caller_list));
3005 }
3006
3007 devstat = reset_device(index, z90crypt.cdx, MAX_RESET);
3008 if (devstat == DEV_RSQ_EXCEPTION) {
3009 PRINTK("exception during reset device %d\n", index);
3010 kfree(dev_ptr->dev_resp_p);
3011 kfree(dev_ptr);
3012 return RSQ_FATAL_ERROR;
3013 }
3014 if (devstat == DEV_ONLINE) {
3015 dev_ptr->dev_self_x = index;
3016 dev_ptr->dev_type = z90crypt.dev_type_array[index];
3017 if (dev_ptr->dev_type == NILDEV) {
3018 rv = probe_device_type(dev_ptr);
3019 if (rv) {
3020 PRINTK("rv = %d from probe_device_type %d\n",
3021 rv, index);
3022 kfree(dev_ptr->dev_resp_p);
3023 kfree(dev_ptr);
3024 return rv;
3025 }
3026 }
3027 if (dev_ptr->dev_type == PCIXCC_UNK) {
3028 rv = probe_PCIXCC_type(dev_ptr);
3029 if (rv) {
3030 PRINTK("rv = %d from probe_PCIXCC_type %d\n",
3031 rv, index);
3032 kfree(dev_ptr->dev_resp_p);
3033 kfree(dev_ptr);
3034 return rv;
3035 }
3036 }
3037 deviceType = dev_ptr->dev_type;
3038 z90crypt.dev_type_array[index] = deviceType;
3039 if (deviceType == PCICA)
3040 z90crypt.hdware_info->device_type_array[index] = 1;
3041 else if (deviceType == PCICC)
3042 z90crypt.hdware_info->device_type_array[index] = 2;
3043 else if (deviceType == PCIXCC_MCL2)
3044 z90crypt.hdware_info->device_type_array[index] = 3;
3045 else if (deviceType == PCIXCC_MCL3)
3046 z90crypt.hdware_info->device_type_array[index] = 4;
3047 else if (deviceType == CEX2C)
3048 z90crypt.hdware_info->device_type_array[index] = 5;
3049 else if (deviceType == CEX2A)
3050 z90crypt.hdware_info->device_type_array[index] = 6;
3051 else // No idea how this would happen.
3052 z90crypt.hdware_info->device_type_array[index] = -1;
3053 }
3054
3055 /**
3056 * 'q_depth' returned by the hardware is one less than
3057 * the actual depth
3058 */
3059 dev_ptr->dev_q_depth = z90crypt.q_depth_array[index];
3060 dev_ptr->dev_type = z90crypt.dev_type_array[index];
3061 dev_ptr->dev_stat = devstat;
3062 dev_ptr->disabled = 0;
3063 z90crypt.device_p[index] = dev_ptr;
3064
3065 if (devstat == DEV_ONLINE) {
3066 if (z90crypt.mask.st_mask[index] != DEV_ONLINE) {
3067 z90crypt.mask.st_mask[index] = DEV_ONLINE;
3068 z90crypt.mask.st_count++;
3069 }
3070 deviceType = dev_ptr->dev_type;
3071 type_str_p = &z90crypt.hdware_info->type_mask[deviceType];
3072 if (type_str_p->st_mask[index] != DEV_ONLINE) {
3073 type_str_p->st_mask[index] = DEV_ONLINE;
3074 type_str_p->st_count++;
3075 }
3076 }
3077
3078 return 0;
3079 }
3080
3081 static int
3082 destroy_crypto_device(int index)
3083 {
3084 struct device *dev_ptr;
3085 int t, disabledFlag;
3086
3087 dev_ptr = z90crypt.device_p[index];
3088
3089 /* remember device type; get rid of device struct */
3090 if (dev_ptr) {
3091 disabledFlag = dev_ptr->disabled;
3092 t = dev_ptr->dev_type;
3093 kfree(dev_ptr->dev_resp_p);
3094 kfree(dev_ptr);
3095 } else {
3096 disabledFlag = 0;
3097 t = -1;
3098 }
3099 z90crypt.device_p[index] = 0;
3100
3101 /* if the type is valid, remove the device from the type_mask */
3102 if ((t != -1) && z90crypt.hdware_info->type_mask[t].st_mask[index]) {
3103 z90crypt.hdware_info->type_mask[t].st_mask[index] = 0x00;
3104 z90crypt.hdware_info->type_mask[t].st_count--;
3105 if (disabledFlag == 1)
3106 z90crypt.hdware_info->type_mask[t].disabled_count--;
3107 }
3108 if (z90crypt.mask.st_mask[index] != DEV_GONE) {
3109 z90crypt.mask.st_mask[index] = DEV_GONE;
3110 z90crypt.mask.st_count--;
3111 }
3112 z90crypt.hdware_info->device_type_array[index] = 0;
3113
3114 return 0;
3115 }
3116
3117 static void
3118 destroy_z90crypt(void)
3119 {
3120 int i;
3121
3122 for (i = 0; i < z90crypt.max_count; i++)
3123 if (z90crypt.device_p[i])
3124 destroy_crypto_device(i);
3125 kfree(z90crypt.hdware_info);
3126 memset((void *)&z90crypt, 0, sizeof(z90crypt));
3127 }
3128
3129 static unsigned char static_testmsg[384] = {
3130 0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x00,0x06,0x00,0x00,
3131 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x58,
3132 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x43,0x43,
3133 0x41,0x2d,0x41,0x50,0x50,0x4c,0x20,0x20,0x20,0x01,0x01,0x01,0x00,0x00,0x00,0x00,
3134 0x50,0x4b,0x00,0x00,0x00,0x00,0x01,0x1c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3135 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3136 0x00,0x00,0x00,0x00,0x70,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x32,
3137 0x01,0x00,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3138 0xb8,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3139 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3140 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3141 0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3142 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x49,0x43,0x53,0x46,
3143 0x20,0x20,0x20,0x20,0x50,0x4b,0x0a,0x00,0x50,0x4b,0x43,0x53,0x2d,0x31,0x2e,0x32,
3144 0x37,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,
3145 0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,
3146 0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,
3147 0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x5d,0x00,0x5b,0x00,0x77,0x88,0x1e,0x00,0x00,
3148 0x57,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x4f,0x00,0x00,0x00,0x03,0x02,0x00,0x00,
3149 0x40,0x01,0x00,0x01,0xce,0x02,0x68,0x2d,0x5f,0xa9,0xde,0x0c,0xf6,0xd2,0x7b,0x58,
3150 0x4b,0xf9,0x28,0x68,0x3d,0xb4,0xf4,0xef,0x78,0xd5,0xbe,0x66,0x63,0x42,0xef,0xf8,
3151 0xfd,0xa4,0xf8,0xb0,0x8e,0x29,0xc2,0xc9,0x2e,0xd8,0x45,0xb8,0x53,0x8c,0x6f,0x4e,
3152 0x72,0x8f,0x6c,0x04,0x9c,0x88,0xfc,0x1e,0xc5,0x83,0x55,0x57,0xf7,0xdd,0xfd,0x4f,
3153 0x11,0x36,0x95,0x5d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
3154 };
3155
3156 static int
3157 probe_device_type(struct device *devPtr)
3158 {
3159 int rv, dv, i, index, length;
3160 unsigned char psmid[8];
3161 static unsigned char loc_testmsg[sizeof(static_testmsg)];
3162
3163 index = devPtr->dev_self_x;
3164 rv = 0;
3165 do {
3166 memcpy(loc_testmsg, static_testmsg, sizeof(static_testmsg));
3167 length = sizeof(static_testmsg) - 24;
3168 /* the -24 allows for the header */
3169 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3170 if (dv) {
3171 PDEBUG("dv returned by send during probe: %d\n", dv);
3172 if (dv == DEV_SEN_EXCEPTION) {
3173 rv = SEN_FATAL_ERROR;
3174 PRINTKC("exception in send to AP %d\n", index);
3175 break;
3176 }
3177 PDEBUG("return value from send_to_AP: %d\n", rv);
3178 switch (dv) {
3179 case DEV_GONE:
3180 PDEBUG("dev %d not available\n", index);
3181 rv = SEN_NOT_AVAIL;
3182 break;
3183 case DEV_ONLINE:
3184 rv = 0;
3185 break;
3186 case DEV_EMPTY:
3187 rv = SEN_NOT_AVAIL;
3188 break;
3189 case DEV_NO_WORK:
3190 rv = SEN_FATAL_ERROR;
3191 break;
3192 case DEV_BAD_MESSAGE:
3193 rv = SEN_USER_ERROR;
3194 break;
3195 case DEV_QUEUE_FULL:
3196 rv = SEN_QUEUE_FULL;
3197 break;
3198 default:
3199 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3200 rv = SEN_NOT_AVAIL;
3201 break;
3202 }
3203 }
3204
3205 if (rv)
3206 break;
3207
3208 for (i = 0; i < 6; i++) {
3209 mdelay(300);
3210 dv = receive_from_AP(index, z90crypt.cdx,
3211 devPtr->dev_resp_l,
3212 devPtr->dev_resp_p, psmid);
3213 PDEBUG("dv returned by DQ = %d\n", dv);
3214 if (dv == DEV_REC_EXCEPTION) {
3215 rv = REC_FATAL_ERROR;
3216 PRINTKC("exception in dequeue %d\n",
3217 index);
3218 break;
3219 }
3220 switch (dv) {
3221 case DEV_ONLINE:
3222 rv = 0;
3223 break;
3224 case DEV_EMPTY:
3225 rv = REC_EMPTY;
3226 break;
3227 case DEV_NO_WORK:
3228 rv = REC_NO_WORK;
3229 break;
3230 case DEV_BAD_MESSAGE:
3231 case DEV_GONE:
3232 default:
3233 rv = REC_NO_RESPONSE;
3234 break;
3235 }
3236 if ((rv != 0) && (rv != REC_NO_WORK))
3237 break;
3238 if (rv == 0)
3239 break;
3240 }
3241 if (rv)
3242 break;
3243 rv = (devPtr->dev_resp_p[0] == 0x00) &&
3244 (devPtr->dev_resp_p[1] == 0x86);
3245 if (rv)
3246 devPtr->dev_type = PCICC;
3247 else
3248 devPtr->dev_type = PCICA;
3249 rv = 0;
3250 } while (0);
3251 /* In a general error case, the card is not marked online */
3252 return rv;
3253 }
3254
3255 static unsigned char MCL3_testmsg[] = {
3256 0x00,0x00,0x00,0x00,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,
3257 0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3258 0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3259 0x43,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3260 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x00,0x00,0x00,0x01,0xC4,0x00,0x00,0x00,0x00,
3261 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,0x00,0x00,0x00,0x00,
3262 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDC,0x02,0x00,0x00,0x00,0x54,0x32,
3263 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE8,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,
3264 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3265 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3266 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3267 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3268 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3269 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3270 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3271 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3272 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3273 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3274 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3275 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3276 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x0A,0x4D,0x52,0x50,0x20,0x20,0x20,0x20,0x20,
3277 0x00,0x42,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,
3278 0x0E,0x0F,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xAA,0xBB,0xCC,0xDD,
3279 0xEE,0xFF,0xFF,0xEE,0xDD,0xCC,0xBB,0xAA,0x99,0x88,0x77,0x66,0x55,0x44,0x33,0x22,
3280 0x11,0x00,0x01,0x23,0x45,0x67,0x89,0xAB,0xCD,0xEF,0xFE,0xDC,0xBA,0x98,0x76,0x54,
3281 0x32,0x10,0x00,0x9A,0x00,0x98,0x00,0x00,0x1E,0x00,0x00,0x94,0x00,0x00,0x00,0x00,
3282 0x04,0x00,0x00,0x8C,0x00,0x00,0x00,0x40,0x02,0x00,0x00,0x40,0xBA,0xE8,0x23,0x3C,
3283 0x75,0xF3,0x91,0x61,0xD6,0x73,0x39,0xCF,0x7B,0x6D,0x8E,0x61,0x97,0x63,0x9E,0xD9,
3284 0x60,0x55,0xD6,0xC7,0xEF,0xF8,0x1E,0x63,0x95,0x17,0xCC,0x28,0x45,0x60,0x11,0xC5,
3285 0xC4,0x4E,0x66,0xC6,0xE6,0xC3,0xDE,0x8A,0x19,0x30,0xCF,0x0E,0xD7,0xAA,0xDB,0x01,
3286 0xD8,0x00,0xBB,0x8F,0x39,0x9F,0x64,0x28,0xF5,0x7A,0x77,0x49,0xCC,0x6B,0xA3,0x91,
3287 0x97,0x70,0xE7,0x60,0x1E,0x39,0xE1,0xE5,0x33,0xE1,0x15,0x63,0x69,0x08,0x80,0x4C,
3288 0x67,0xC4,0x41,0x8F,0x48,0xDF,0x26,0x98,0xF1,0xD5,0x8D,0x88,0xD9,0x6A,0xA4,0x96,
3289 0xC5,0x84,0xD9,0x30,0x49,0x67,0x7D,0x19,0xB1,0xB3,0x45,0x4D,0xB2,0x53,0x9A,0x47,
3290 0x3C,0x7C,0x55,0xBF,0xCC,0x85,0x00,0x36,0xF1,0x3D,0x93,0x53
3291 };
3292
3293 static int
3294 probe_PCIXCC_type(struct device *devPtr)
3295 {
3296 int rv, dv, i, index, length;
3297 unsigned char psmid[8];
3298 static unsigned char loc_testmsg[548];
3299 struct CPRBX *cprbx_p;
3300
3301 index = devPtr->dev_self_x;
3302 rv = 0;
3303 do {
3304 memcpy(loc_testmsg, MCL3_testmsg, sizeof(MCL3_testmsg));
3305 length = sizeof(MCL3_testmsg) - 0x0C;
3306 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3307 if (dv) {
3308 PDEBUG("dv returned = %d\n", dv);
3309 if (dv == DEV_SEN_EXCEPTION) {
3310 rv = SEN_FATAL_ERROR;
3311 PRINTKC("exception in send to AP %d\n", index);
3312 break;
3313 }
3314 PDEBUG("return value from send_to_AP: %d\n", rv);
3315 switch (dv) {
3316 case DEV_GONE:
3317 PDEBUG("dev %d not available\n", index);
3318 rv = SEN_NOT_AVAIL;
3319 break;
3320 case DEV_ONLINE:
3321 rv = 0;
3322 break;
3323 case DEV_EMPTY:
3324 rv = SEN_NOT_AVAIL;
3325 break;
3326 case DEV_NO_WORK:
3327 rv = SEN_FATAL_ERROR;
3328 break;
3329 case DEV_BAD_MESSAGE:
3330 rv = SEN_USER_ERROR;
3331 break;
3332 case DEV_QUEUE_FULL:
3333 rv = SEN_QUEUE_FULL;
3334 break;
3335 default:
3336 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3337 rv = SEN_NOT_AVAIL;
3338 break;
3339 }
3340 }
3341
3342 if (rv)
3343 break;
3344
3345 for (i = 0; i < 6; i++) {
3346 mdelay(300);
3347 dv = receive_from_AP(index, z90crypt.cdx,
3348 devPtr->dev_resp_l,
3349 devPtr->dev_resp_p, psmid);
3350 PDEBUG("dv returned by DQ = %d\n", dv);
3351 if (dv == DEV_REC_EXCEPTION) {
3352 rv = REC_FATAL_ERROR;
3353 PRINTKC("exception in dequeue %d\n",
3354 index);
3355 break;
3356 }
3357 switch (dv) {
3358 case DEV_ONLINE:
3359 rv = 0;
3360 break;
3361 case DEV_EMPTY:
3362 rv = REC_EMPTY;
3363 break;
3364 case DEV_NO_WORK:
3365 rv = REC_NO_WORK;
3366 break;
3367 case DEV_BAD_MESSAGE:
3368 case DEV_GONE:
3369 default:
3370 rv = REC_NO_RESPONSE;
3371 break;
3372 }
3373 if ((rv != 0) && (rv != REC_NO_WORK))
3374 break;
3375 if (rv == 0)
3376 break;
3377 }
3378 if (rv)
3379 break;
3380 cprbx_p = (struct CPRBX *) (devPtr->dev_resp_p + 48);
3381 if ((cprbx_p->ccp_rtcode == 8) && (cprbx_p->ccp_rscode == 33)) {
3382 devPtr->dev_type = PCIXCC_MCL2;
3383 PDEBUG("device %d is MCL2\n", index);
3384 } else {
3385 devPtr->dev_type = PCIXCC_MCL3;
3386 PDEBUG("device %d is MCL3\n", index);
3387 }
3388 } while (0);
3389 /* In a general error case, the card is not marked online */
3390 return rv;
3391 }
3392
3393 module_init(z90crypt_init_module);
3394 module_exit(z90crypt_cleanup_module);
Linux kernel - Deliverables
This page took 0.184343 seconds and 6 git commands to generate.