drivers/scsi/NCR5380.h

   1 /*
   2  * NCR 5380 defines
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  * DISTRIBUTION RELEASE 7
  11  *
  12  * For more information, please consult
  13  *
  14  * NCR 5380 Family
  15  * SCSI Protocol Controller
  16  * Databook
  17  * NCR Microelectronics
  18  * 1635 Aeroplaza Drive
  19  * Colorado Springs, CO 80916
  20  * 1+ (719) 578-3400
  21  * 1+ (800) 334-5454
  22  */
  23
  24 #ifndef NCR5380_H
  25 #define NCR5380_H
  26
  27 #include <linux/interrupt.h>
  28 #include <scsi/scsi_eh.h>
  29
  30 #define NCR5380_PUBLIC_RELEASE 7
  31 #define NCR53C400_PUBLIC_RELEASE 2
  32
  33 #define NDEBUG_ARBITRATION      0x1
  34 #define NDEBUG_AUTOSENSE        0x2
  35 #define NDEBUG_DMA              0x4
  36 #define NDEBUG_HANDSHAKE        0x8
  37 #define NDEBUG_INFORMATION      0x10
  38 #define NDEBUG_INIT             0x20
  39 #define NDEBUG_INTR             0x40
  40 #define NDEBUG_LINKED           0x80
  41 #define NDEBUG_MAIN             0x100
  42 #define NDEBUG_NO_DATAOUT       0x200
  43 #define NDEBUG_NO_WRITE         0x400
  44 #define NDEBUG_PIO              0x800
  45 #define NDEBUG_PSEUDO_DMA       0x1000
  46 #define NDEBUG_QUEUES           0x2000
  47 #define NDEBUG_RESELECTION      0x4000
  48 #define NDEBUG_SELECTION        0x8000
  49 #define NDEBUG_USLEEP           0x10000
  50 #define NDEBUG_LAST_BYTE_SENT   0x20000
  51 #define NDEBUG_RESTART_SELECT   0x40000
  52 #define NDEBUG_EXTENDED         0x80000
  53 #define NDEBUG_C400_PREAD       0x100000
  54 #define NDEBUG_C400_PWRITE      0x200000
  55 #define NDEBUG_LISTS            0x400000
  56 #define NDEBUG_ABORT            0x800000
  57 #define NDEBUG_TAGS             0x1000000
  58 #define NDEBUG_MERGING          0x2000000
  59
  60 #define NDEBUG_ANY              0xFFFFFFFFUL
  61
  62 /*
  63  * The contents of the OUTPUT DATA register are asserted on the bus when
  64  * either arbitration is occurring or the phase-indicating signals (
  65  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  66  * bit in the INITIATOR COMMAND register is set.
  67  */
  68
  69 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  70 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  71
  72 #define INITIATOR_COMMAND_REG   1       /* rw */
  73 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  74 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  75 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  76 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  77 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  78 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  79 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  80 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  81 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  82 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  83
  84 #ifdef DIFFERENTIAL
  85 #define ICR_BASE                ICR_DIFF_ENABLE
  86 #else
  87 #define ICR_BASE                0
  88 #endif
  89
  90 #define MODE_REG                2
  91 /*
  92  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
  93  * transfer, causing the chip to hog the bus.  You probably don't want
  94  * this.
  95  */
  96 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  97 #define MR_TARGET               0x40    /* rw target mode */
  98 #define MR_ENABLE_PAR_CHECK     0x20    /* rw enable parity checking */
  99 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
 100 #define MR_ENABLE_EOP_INTR      0x08    /* rw enable eop interrupt */
 101 #define MR_MONITOR_BSY          0x04    /* rw enable int on unexpected bsy fail */
 102 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
 103 #define MR_ARBITRATE            0x01    /* rw start arbitration */
 104
 105 #ifdef PARITY
 106 #define MR_BASE                 MR_ENABLE_PAR_CHECK
 107 #else
 108 #define MR_BASE                 0
 109 #endif
 110
 111 #define TARGET_COMMAND_REG      3
 112 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 113 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 114 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 115 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 116 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 117
 118 #define STATUS_REG              4       /* ro */
 119 /*
 120  * Note : a set bit indicates an active signal, driven by us or another
 121  * device.
 122  */
 123 #define SR_RST                  0x80
 124 #define SR_BSY                  0x40
 125 #define SR_REQ                  0x20
 126 #define SR_MSG                  0x10
 127 #define SR_CD                   0x08
 128 #define SR_IO                   0x04
 129 #define SR_SEL                  0x02
 130 #define SR_DBP                  0x01
 131
 132 /*
 133  * Setting a bit in this register will cause an interrupt to be generated when
 134  * BSY is false and SEL true and this bit is asserted  on the bus.
 135  */
 136 #define SELECT_ENABLE_REG       4       /* wo */
 137
 138 #define BUS_AND_STATUS_REG      5       /* ro */
 139 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 140 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 141 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 142 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 143 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 144 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 145 #define BASR_ATN                0x02    /* ro BUS status */
 146 #define BASR_ACK                0x01    /* ro BUS status */
 147
 148 /* Write any value to this register to start a DMA send */
 149 #define START_DMA_SEND_REG      5       /* wo */
 150
 151 /*
 152  * Used in DMA transfer mode, data is latched from the SCSI bus on
 153  * the falling edge of REQ (ini) or ACK (tgt)
 154  */
 155 #define INPUT_DATA_REG                  6       /* ro */
 156
 157 /* Write any value to this register to start a DMA receive */
 158 #define START_DMA_TARGET_RECEIVE_REG    6       /* wo */
 159
 160 /* Read this register to clear interrupt conditions */
 161 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 162
 163 /* Write any value to this register to start an ini mode DMA receive */
 164 #define START_DMA_INITIATOR_RECEIVE_REG 7       /* wo */
 165
 166 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8     /* rw */
 167
 168 #define CSR_RESET              0x80     /* wo  Resets 53c400 */
 169 #define CSR_53C80_REG          0x80     /* ro  5380 registers busy */
 170 #define CSR_TRANS_DIR          0x40     /* rw  Data transfer direction */
 171 #define CSR_SCSI_BUFF_INTR     0x20     /* rw  Enable int on transfer ready */
 172 #define CSR_53C80_INTR         0x10     /* rw  Enable 53c80 interrupts */
 173 #define CSR_SHARED_INTR        0x08     /* rw  Interrupt sharing */
 174 #define CSR_HOST_BUF_NOT_RDY   0x04     /* ro  Is Host buffer ready */
 175 #define CSR_SCSI_BUF_RDY       0x02     /* ro  SCSI buffer read */
 176 #define CSR_GATED_53C80_IRQ    0x01     /* ro  Last block xferred */
 177
 178 #if 0
 179 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
 180 #else
 181 #define CSR_BASE CSR_53C80_INTR
 182 #endif
 183
 184 /* Number of 128-byte blocks to be transferred */
 185 #define C400_BLOCK_COUNTER_REG   NCR53C400_register_offset-7    /* rw */
 186
 187 /* Resume transfer after disconnect */
 188 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6    /* wo */
 189
 190 /* Access to host buffer stack */
 191 #define C400_HOST_BUFFER         NCR53C400_register_offset-4    /* rw */
 192
 193
 194 /* Note : PHASE_* macros are based on the values of the STATUS register */
 195 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 196
 197 #define PHASE_DATAOUT           0
 198 #define PHASE_DATAIN            SR_IO
 199 #define PHASE_CMDOUT            SR_CD
 200 #define PHASE_STATIN            (SR_CD | SR_IO)
 201 #define PHASE_MSGOUT            (SR_MSG | SR_CD)
 202 #define PHASE_MSGIN             (SR_MSG | SR_CD | SR_IO)
 203 #define PHASE_UNKNOWN           0xff
 204
 205 /*
 206  * Convert status register phase to something we can use to set phase in
 207  * the target register so we can get phase mismatch interrupts on DMA
 208  * transfers.
 209  */
 210
 211 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
 212
 213 /*
 214  * The internal should_disconnect() function returns these based on the
 215  * expected length of a disconnect if a device supports disconnect/
 216  * reconnect.
 217  */
 218
 219 #define DISCONNECT_NONE         0
 220 #define DISCONNECT_TIME_TO_DATA 1
 221 #define DISCONNECT_LONG         2
 222
 223 /*
 224  * "Special" value for the (unsigned char) command tag, to indicate
 225  * I_T_L nexus instead of I_T_L_Q.
 226  */
 227
 228 #define TAG_NONE        0xff
 229
 230 /*
 231  * These are "special" values for the irq and dma_channel fields of the
 232  * Scsi_Host structure
 233  */
 234
 235 #define DMA_NONE        255
 236 #define IRQ_AUTO        254
 237 #define DMA_AUTO        254
 238 #define PORT_AUTO       0xffff  /* autoprobe io port for 53c400a */
 239
 240 #ifndef NO_IRQ
 241 #define NO_IRQ          0
 242 #endif
 243
 244 #define FLAG_HAS_LAST_BYTE_SENT         1       /* NCR53c81 or better */
 245 #define FLAG_CHECK_LAST_BYTE_SENT       2       /* Only test once */
 246 #define FLAG_NCR53C400                  4       /* NCR53c400 */
 247 #define FLAG_NO_PSEUDO_DMA              8       /* Inhibit DMA */
 248 #define FLAG_DTC3181E                   16      /* DTC3181E */
 249
 250 #ifndef ASM
 251 struct NCR5380_hostdata {
 252         NCR5380_implementation_fields;          /* implementation specific */
 253         struct Scsi_Host *host;                 /* Host backpointer */
 254         unsigned char id_mask, id_higher_mask;  /* 1 << id, all bits greater */
 255         unsigned char targets_present;          /* targets we have connected
 256                                                    to, so we can call a select
 257                                                    failure a retryable condition */
 258         volatile unsigned char busy[8];         /* index = target, bit = lun */
 259 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
 260         volatile int dma_len;                   /* requested length of DMA */
 261 #endif
 262         volatile unsigned char last_message;    /* last message OUT */
 263         volatile Scsi_Cmnd *connected;          /* currently connected command */
 264         volatile Scsi_Cmnd *issue_queue;        /* waiting to be issued */
 265         volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
 266         volatile int restart_select;            /* we have disconnected,
 267                                                    used to restart
 268                                                    NCR5380_select() */
 269         volatile unsigned aborted:1;            /* flag, says aborted */
 270         int flags;
 271         unsigned long time_expires;             /* in jiffies, set prior to sleeping */
 272         int select_time;                        /* timer in select for target response */
 273         volatile Scsi_Cmnd *selecting;
 274         struct delayed_work coroutine;          /* our co-routine */
 275         struct scsi_eh_save ses;
 276         char info[256];
 277 };
 278
 279 #ifdef __KERNEL__
 280
 281 #ifndef NDEBUG
 282 #define NDEBUG (0)
 283 #endif
 284
 285 #define dprintk(flg, fmt, ...) \
 286         do { if ((NDEBUG) & (flg)) \
 287                 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
 288
 289 #if NDEBUG
 290 #define NCR5380_dprint(flg, arg) \
 291         do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
 292 #define NCR5380_dprint_phase(flg, arg) \
 293         do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
 294 static void NCR5380_print_phase(struct Scsi_Host *instance);
 295 static void NCR5380_print(struct Scsi_Host *instance);
 296 #else
 297 #define NCR5380_dprint(flg, arg)       do {} while (0)
 298 #define NCR5380_dprint_phase(flg, arg) do {} while (0)
 299 #endif
 300
 301 #if defined(AUTOPROBE_IRQ)
 302 static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
 303 #endif
 304 static int NCR5380_init(struct Scsi_Host *instance, int flags);
 305 static void NCR5380_exit(struct Scsi_Host *instance);
 306 static void NCR5380_information_transfer(struct Scsi_Host *instance);
 307 #ifndef DONT_USE_INTR
 308 static irqreturn_t NCR5380_intr(int irq, void *dev_id);
 309 #endif
 310 static void NCR5380_main(struct work_struct *work);
 311 static const char *NCR5380_info(struct Scsi_Host *instance);
 312 static void NCR5380_reselect(struct Scsi_Host *instance);
 313 static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd *cmd);
 314 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
 315 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 316 #endif
 317 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 318
 319 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
 320
 321 #if defined(i386) || defined(__alpha__)
 322
 323 /**
 324  *      NCR5380_pc_dma_setup            -       setup ISA DMA
 325  *      @instance: adapter to set up
 326  *      @ptr: block to transfer (virtual address)
 327  *      @count: number of bytes to transfer
 328  *      @mode: DMA controller mode to use
 329  *
 330  *      Program the DMA controller ready to perform an ISA DMA transfer
 331  *      on this chip.
 332  *
 333  *      Locks: takes and releases the ISA DMA lock.
 334  */
 335
 336 static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
 337 {
 338         unsigned limit;
 339         unsigned long bus_addr = virt_to_bus(ptr);
 340         unsigned long flags;
 341
 342         if (instance->dma_channel <= 3) {
 343                 if (count > 65536)
 344                         count = 65536;
 345                 limit = 65536 - (bus_addr & 0xFFFF);
 346         } else {
 347                 if (count > 65536 * 2)
 348                         count = 65536 * 2;
 349                 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
 350         }
 351
 352         if (count > limit)
 353                 count = limit;
 354
 355         if ((count & 1) || (bus_addr & 1))
 356                 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
 357
 358         flags=claim_dma_lock();
 359         disable_dma(instance->dma_channel);
 360         clear_dma_ff(instance->dma_channel);
 361         set_dma_addr(instance->dma_channel, bus_addr);
 362         set_dma_count(instance->dma_channel, count);
 363         set_dma_mode(instance->dma_channel, mode);
 364         enable_dma(instance->dma_channel);
 365         release_dma_lock(flags);
 366
 367         return count;
 368 }
 369
 370 /**
 371  *      NCR5380_pc_dma_write_setup              -       setup ISA DMA write
 372  *      @instance: adapter to set up
 373  *      @ptr: block to transfer (virtual address)
 374  *      @count: number of bytes to transfer
 375  *
 376  *      Program the DMA controller ready to perform an ISA DMA write to the
 377  *      SCSI controller.
 378  *
 379  *      Locks: called routines take and release the ISA DMA lock.
 380  */
 381
 382 static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 383 {
 384         return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
 385 }
 386
 387 /**
 388  *      NCR5380_pc_dma_read_setup               -       setup ISA DMA read
 389  *      @instance: adapter to set up
 390  *      @ptr: block to transfer (virtual address)
 391  *      @count: number of bytes to transfer
 392  *
 393  *      Program the DMA controller ready to perform an ISA DMA read from the
 394  *      SCSI controller.
 395  *
 396  *      Locks: called routines take and release the ISA DMA lock.
 397  */
 398
 399 static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 400 {
 401         return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
 402 }
 403
 404 /**
 405  *      NCR5380_pc_dma_residual         -       return bytes left
 406  *      @instance: adapter
 407  *
 408  *      Reports the number of bytes left over after the DMA was terminated.
 409  *
 410  *      Locks: takes and releases the ISA DMA lock.
 411  */
 412
 413 static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
 414 {
 415         unsigned long flags;
 416         int tmp;
 417
 418         flags = claim_dma_lock();
 419         clear_dma_ff(instance->dma_channel);
 420         tmp = get_dma_residue(instance->dma_channel);
 421         release_dma_lock(flags);
 422
 423         return tmp;
 424 }
 425 #endif                          /* defined(i386) || defined(__alpha__) */
 426 #endif                          /* defined(REAL_DMA)  */
 427 #endif                          /* __KERNEL__ */
 428 #endif                          /* ndef ASM */
 429 #endif                          /* NCR5380_H */