2 * ahci.c - AHCI SATA support
4 * Copyright 2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include <linux/dma-mapping.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
41 #define DRV_NAME "ahci"
42 #define DRV_VERSION "1.01"
47 AHCI_MAX_SG
= 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY
= 0xffffffff,
49 AHCI_USE_CLUSTERING
= 0,
50 AHCI_CMD_SLOT_SZ
= 32 * 32,
52 AHCI_CMD_TBL_HDR
= 0x80,
53 AHCI_CMD_TBL_CDB
= 0x40,
54 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
55 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
57 AHCI_IRQ_ON_SG
= (1 << 31),
58 AHCI_CMD_ATAPI
= (1 << 5),
59 AHCI_CMD_WRITE
= (1 << 6),
61 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
65 /* global controller registers */
66 HOST_CAP
= 0x00, /* host capabilities */
67 HOST_CTL
= 0x04, /* global host control */
68 HOST_IRQ_STAT
= 0x08, /* interrupt status */
69 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
70 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
73 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
74 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
75 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
78 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
80 /* registers for each SATA port */
81 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
82 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
83 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
84 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
85 PORT_IRQ_STAT
= 0x10, /* interrupt status */
86 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
87 PORT_CMD
= 0x18, /* port command */
88 PORT_TFDATA
= 0x20, /* taskfile data */
89 PORT_SIG
= 0x24, /* device TF signature */
90 PORT_CMD_ISSUE
= 0x38, /* command issue */
91 PORT_SCR
= 0x28, /* SATA phy register block */
92 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
93 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
94 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
95 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
97 /* PORT_IRQ_{STAT,MASK} bits */
98 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
99 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
100 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
101 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
102 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
103 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
104 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
105 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
107 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
108 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
109 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
110 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
111 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
112 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
113 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
114 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
115 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
117 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
119 PORT_IRQ_HBUS_DATA_ERR
|
121 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
122 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
123 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
124 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
125 PORT_IRQ_D2H_REG_FIS
,
128 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
129 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
130 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
131 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
132 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
133 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
135 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
136 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
137 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
139 /* hpriv->flags bits */
140 AHCI_FLAG_MSI
= (1 << 0),
143 struct ahci_cmd_hdr
{
158 struct ahci_host_priv
{
160 u32 cap
; /* cache of HOST_CAP register */
161 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
164 struct ahci_port_priv
{
165 struct ahci_cmd_hdr
*cmd_slot
;
166 dma_addr_t cmd_slot_dma
;
168 dma_addr_t cmd_tbl_dma
;
169 struct ahci_sg
*cmd_tbl_sg
;
171 dma_addr_t rx_fis_dma
;
174 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
175 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
176 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
177 static int ahci_qc_issue(struct ata_queued_cmd
*qc
);
178 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
179 static void ahci_phy_reset(struct ata_port
*ap
);
180 static void ahci_irq_clear(struct ata_port
*ap
);
181 static void ahci_eng_timeout(struct ata_port
*ap
);
182 static int ahci_port_start(struct ata_port
*ap
);
183 static void ahci_port_stop(struct ata_port
*ap
);
184 static void ahci_host_stop(struct ata_host_set
*host_set
);
185 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
186 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
187 static u8
ahci_check_status(struct ata_port
*ap
);
188 static u8
ahci_check_err(struct ata_port
*ap
);
189 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
190 static void ahci_remove_one (struct pci_dev
*pdev
);
192 static Scsi_Host_Template ahci_sht
= {
193 .module
= THIS_MODULE
,
195 .ioctl
= ata_scsi_ioctl
,
196 .queuecommand
= ata_scsi_queuecmd
,
197 .eh_strategy_handler
= ata_scsi_error
,
198 .can_queue
= ATA_DEF_QUEUE
,
199 .this_id
= ATA_SHT_THIS_ID
,
200 .sg_tablesize
= AHCI_MAX_SG
,
201 .max_sectors
= ATA_MAX_SECTORS
,
202 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
203 .emulated
= ATA_SHT_EMULATED
,
204 .use_clustering
= AHCI_USE_CLUSTERING
,
205 .proc_name
= DRV_NAME
,
206 .dma_boundary
= AHCI_DMA_BOUNDARY
,
207 .slave_configure
= ata_scsi_slave_config
,
208 .bios_param
= ata_std_bios_param
,
212 static struct ata_port_operations ahci_ops
= {
213 .port_disable
= ata_port_disable
,
215 .check_status
= ahci_check_status
,
216 .check_altstatus
= ahci_check_status
,
217 .check_err
= ahci_check_err
,
218 .dev_select
= ata_noop_dev_select
,
220 .tf_read
= ahci_tf_read
,
222 .phy_reset
= ahci_phy_reset
,
224 .qc_prep
= ahci_qc_prep
,
225 .qc_issue
= ahci_qc_issue
,
227 .eng_timeout
= ahci_eng_timeout
,
229 .irq_handler
= ahci_interrupt
,
230 .irq_clear
= ahci_irq_clear
,
232 .scr_read
= ahci_scr_read
,
233 .scr_write
= ahci_scr_write
,
235 .port_start
= ahci_port_start
,
236 .port_stop
= ahci_port_stop
,
237 .host_stop
= ahci_host_stop
,
240 static struct ata_port_info ahci_port_info
[] = {
244 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
245 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
247 .pio_mask
= 0x03, /* pio3-4 */
248 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
249 .port_ops
= &ahci_ops
,
253 static struct pci_device_id ahci_pci_tbl
[] = {
254 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
255 board_ahci
}, /* ICH6 */
256 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
257 board_ahci
}, /* ICH6M */
258 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
259 board_ahci
}, /* ICH7 */
260 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
261 board_ahci
}, /* ICH7M */
262 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
263 board_ahci
}, /* ICH7R */
264 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
265 board_ahci
}, /* ULi M5288 */
266 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
267 board_ahci
}, /* ESB2 */
268 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
269 board_ahci
}, /* ESB2 */
270 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
271 board_ahci
}, /* ESB2 */
272 { } /* terminate list */
276 static struct pci_driver ahci_pci_driver
= {
278 .id_table
= ahci_pci_tbl
,
279 .probe
= ahci_init_one
,
280 .remove
= ahci_remove_one
,
284 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
286 return base
+ 0x100 + (port
* 0x80);
289 static inline void *ahci_port_base (void *base
, unsigned int port
)
291 return (void *) ahci_port_base_ul((unsigned long)base
, port
);
294 static void ahci_host_stop(struct ata_host_set
*host_set
)
296 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
299 ata_host_stop(host_set
);
302 static int ahci_port_start(struct ata_port
*ap
)
304 struct device
*dev
= ap
->host_set
->dev
;
305 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
306 struct ahci_port_priv
*pp
;
308 void *mem
, *mmio
= ap
->host_set
->mmio_base
;
309 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
312 rc
= ata_port_start(ap
);
316 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
321 memset(pp
, 0, sizeof(*pp
));
323 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
328 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
331 * First item in chunk of DMA memory: 32-slot command table,
332 * 32 bytes each in size
335 pp
->cmd_slot_dma
= mem_dma
;
337 mem
+= AHCI_CMD_SLOT_SZ
;
338 mem_dma
+= AHCI_CMD_SLOT_SZ
;
341 * Second item: Received-FIS area
344 pp
->rx_fis_dma
= mem_dma
;
346 mem
+= AHCI_RX_FIS_SZ
;
347 mem_dma
+= AHCI_RX_FIS_SZ
;
350 * Third item: data area for storing a single command
351 * and its scatter-gather table
354 pp
->cmd_tbl_dma
= mem_dma
;
356 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
358 ap
->private_data
= pp
;
360 if (hpriv
->cap
& HOST_CAP_64
)
361 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
362 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
363 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
365 if (hpriv
->cap
& HOST_CAP_64
)
366 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
367 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
368 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
370 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
371 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
372 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
373 readl(port_mmio
+ PORT_CMD
); /* flush */
385 static void ahci_port_stop(struct ata_port
*ap
)
387 struct device
*dev
= ap
->host_set
->dev
;
388 struct ahci_port_priv
*pp
= ap
->private_data
;
389 void *mmio
= ap
->host_set
->mmio_base
;
390 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
393 tmp
= readl(port_mmio
+ PORT_CMD
);
394 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
395 writel(tmp
, port_mmio
+ PORT_CMD
);
396 readl(port_mmio
+ PORT_CMD
); /* flush */
398 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
399 * this is slightly incorrect.
403 ap
->private_data
= NULL
;
404 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
405 pp
->cmd_slot
, pp
->cmd_slot_dma
);
410 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
415 case SCR_STATUS
: sc_reg
= 0; break;
416 case SCR_CONTROL
: sc_reg
= 1; break;
417 case SCR_ERROR
: sc_reg
= 2; break;
418 case SCR_ACTIVE
: sc_reg
= 3; break;
423 return readl((void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
427 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
433 case SCR_STATUS
: sc_reg
= 0; break;
434 case SCR_CONTROL
: sc_reg
= 1; break;
435 case SCR_ERROR
: sc_reg
= 2; break;
436 case SCR_ACTIVE
: sc_reg
= 3; break;
441 writel(val
, (void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
444 static void ahci_phy_reset(struct ata_port
*ap
)
446 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
447 struct ata_taskfile tf
;
448 struct ata_device
*dev
= &ap
->device
[0];
451 __sata_phy_reset(ap
);
453 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
456 tmp
= readl(port_mmio
+ PORT_SIG
);
457 tf
.lbah
= (tmp
>> 24) & 0xff;
458 tf
.lbam
= (tmp
>> 16) & 0xff;
459 tf
.lbal
= (tmp
>> 8) & 0xff;
460 tf
.nsect
= (tmp
) & 0xff;
462 dev
->class = ata_dev_classify(&tf
);
463 if (!ata_dev_present(dev
))
464 ata_port_disable(ap
);
467 static u8
ahci_check_status(struct ata_port
*ap
)
469 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
471 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
474 static u8
ahci_check_err(struct ata_port
*ap
)
476 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
478 return (readl(mmio
+ PORT_TFDATA
) >> 8) & 0xFF;
481 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
483 struct ahci_port_priv
*pp
= ap
->private_data
;
484 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
486 ata_tf_from_fis(d2h_fis
, tf
);
489 static void ahci_fill_sg(struct ata_queued_cmd
*qc
)
491 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
497 * Next, the S/G list.
499 for (i
= 0; i
< qc
->n_elem
; i
++) {
503 addr
= sg_dma_address(&qc
->sg
[i
]);
504 sg_len
= sg_dma_len(&qc
->sg
[i
]);
506 pp
->cmd_tbl_sg
[i
].addr
= cpu_to_le32(addr
& 0xffffffff);
507 pp
->cmd_tbl_sg
[i
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
508 pp
->cmd_tbl_sg
[i
].flags_size
= cpu_to_le32(sg_len
- 1);
512 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
514 struct ata_port
*ap
= qc
->ap
;
515 struct ahci_port_priv
*pp
= ap
->private_data
;
517 const u32 cmd_fis_len
= 5; /* five dwords */
520 * Fill in command slot information (currently only one slot,
521 * slot 0, is currently since we don't do queueing)
524 opts
= (qc
->n_elem
<< 16) | cmd_fis_len
;
525 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
526 opts
|= AHCI_CMD_WRITE
;
527 if (is_atapi_taskfile(&qc
->tf
))
528 opts
|= AHCI_CMD_ATAPI
;
530 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
531 pp
->cmd_slot
[0].status
= 0;
532 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
533 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
536 * Fill in command table information. First, the header,
537 * a SATA Register - Host to Device command FIS.
539 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
540 if (opts
& AHCI_CMD_ATAPI
) {
541 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
542 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, ap
->cdb_len
);
545 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
551 static void ahci_intr_error(struct ata_port
*ap
, u32 irq_stat
)
553 void *mmio
= ap
->host_set
->mmio_base
;
554 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
559 tmp
= readl(port_mmio
+ PORT_CMD
);
560 tmp
&= ~PORT_CMD_START
;
561 writel(tmp
, port_mmio
+ PORT_CMD
);
563 /* wait for engine to stop. TODO: this could be
564 * as long as 500 msec
568 tmp
= readl(port_mmio
+ PORT_CMD
);
569 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
574 /* clear SATA phy error, if any */
575 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
576 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
578 /* if DRQ/BSY is set, device needs to be reset.
579 * if so, issue COMRESET
581 tmp
= readl(port_mmio
+ PORT_TFDATA
);
582 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
583 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
584 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
586 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
587 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
591 tmp
= readl(port_mmio
+ PORT_CMD
);
592 tmp
|= PORT_CMD_START
;
593 writel(tmp
, port_mmio
+ PORT_CMD
);
594 readl(port_mmio
+ PORT_CMD
); /* flush */
596 printk(KERN_WARNING
"ata%u: error occurred, port reset\n", ap
->id
);
599 static void ahci_eng_timeout(struct ata_port
*ap
)
601 void *mmio
= ap
->host_set
->mmio_base
;
602 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
603 struct ata_queued_cmd
*qc
;
607 ahci_intr_error(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
609 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
611 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
614 /* hack alert! We cannot use the supplied completion
615 * function from inside the ->eh_strategy_handler() thread.
616 * libata is the only user of ->eh_strategy_handler() in
617 * any kernel, so the default scsi_done() assumes it is
618 * not being called from the SCSI EH.
620 qc
->scsidone
= scsi_finish_command
;
621 ata_qc_complete(qc
, ATA_ERR
);
626 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
628 void *mmio
= ap
->host_set
->mmio_base
;
629 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
630 u32 status
, serr
, ci
;
632 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
633 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
635 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
636 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
638 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
639 if (likely((ci
& 0x1) == 0)) {
641 ata_qc_complete(qc
, 0);
646 if (status
& PORT_IRQ_FATAL
) {
647 ahci_intr_error(ap
, status
);
649 ata_qc_complete(qc
, ATA_ERR
);
655 static void ahci_irq_clear(struct ata_port
*ap
)
660 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
662 struct ata_host_set
*host_set
= dev_instance
;
663 struct ahci_host_priv
*hpriv
;
664 unsigned int i
, handled
= 0;
666 u32 irq_stat
, irq_ack
= 0;
670 hpriv
= host_set
->private_data
;
671 mmio
= host_set
->mmio_base
;
673 /* sigh. 0xffffffff is a valid return from h/w */
674 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
675 irq_stat
&= hpriv
->port_map
;
679 spin_lock(&host_set
->lock
);
681 for (i
= 0; i
< host_set
->n_ports
; i
++) {
685 VPRINTK("port %u\n", i
);
686 ap
= host_set
->ports
[i
];
687 tmp
= irq_stat
& (1 << i
);
689 struct ata_queued_cmd
*qc
;
690 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
691 if (ahci_host_intr(ap
, qc
))
697 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
701 spin_unlock(&host_set
->lock
);
705 return IRQ_RETVAL(handled
);
708 static int ahci_qc_issue(struct ata_queued_cmd
*qc
)
710 struct ata_port
*ap
= qc
->ap
;
711 void *port_mmio
= (void *) ap
->ioaddr
.cmd_addr
;
713 writel(1, port_mmio
+ PORT_SCR_ACT
);
714 readl(port_mmio
+ PORT_SCR_ACT
); /* flush */
716 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
717 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
722 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
723 unsigned int port_idx
)
725 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
726 base
= ahci_port_base_ul(base
, port_idx
);
727 VPRINTK("base now==0x%lx\n", base
);
729 port
->cmd_addr
= base
;
730 port
->scr_addr
= base
+ PORT_SCR
;
735 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
737 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
738 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
739 void __iomem
*mmio
= probe_ent
->mmio_base
;
742 unsigned int i
, j
, using_dac
;
744 void __iomem
*port_mmio
;
746 cap_save
= readl(mmio
+ HOST_CAP
);
747 cap_save
&= ( (1<<28) | (1<<17) );
748 cap_save
|= (1 << 27);
750 /* global controller reset */
751 tmp
= readl(mmio
+ HOST_CTL
);
752 if ((tmp
& HOST_RESET
) == 0) {
753 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
754 readl(mmio
+ HOST_CTL
); /* flush */
757 /* reset must complete within 1 second, or
758 * the hardware should be considered fried.
762 tmp
= readl(mmio
+ HOST_CTL
);
763 if (tmp
& HOST_RESET
) {
764 printk(KERN_ERR DRV_NAME
"(%s): controller reset failed (0x%x)\n",
765 pci_name(pdev
), tmp
);
769 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
770 (void) readl(mmio
+ HOST_CTL
); /* flush */
771 writel(cap_save
, mmio
+ HOST_CAP
);
772 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
773 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
775 pci_read_config_word(pdev
, 0x92, &tmp16
);
777 pci_write_config_word(pdev
, 0x92, tmp16
);
779 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
780 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
781 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
783 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
784 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
786 using_dac
= hpriv
->cap
& HOST_CAP_64
;
788 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
789 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
791 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
793 printk(KERN_ERR DRV_NAME
"(%s): 64-bit DMA enable failed\n",
799 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
801 printk(KERN_ERR DRV_NAME
"(%s): 32-bit DMA enable failed\n",
805 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
807 printk(KERN_ERR DRV_NAME
"(%s): 32-bit consistent DMA enable failed\n",
813 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
814 #if 0 /* BIOSen initialize this incorrectly */
815 if (!(hpriv
->port_map
& (1 << i
)))
819 port_mmio
= ahci_port_base(mmio
, i
);
820 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
822 ahci_setup_port(&probe_ent
->port
[i
],
823 (unsigned long) mmio
, i
);
825 /* make sure port is not active */
826 tmp
= readl(port_mmio
+ PORT_CMD
);
827 VPRINTK("PORT_CMD 0x%x\n", tmp
);
828 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
829 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
830 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
831 PORT_CMD_FIS_RX
| PORT_CMD_START
);
832 writel(tmp
, port_mmio
+ PORT_CMD
);
833 readl(port_mmio
+ PORT_CMD
); /* flush */
835 /* spec says 500 msecs for each bit, so
836 * this is slightly incorrect.
841 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
846 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
847 if ((tmp
& 0xf) == 0x3)
852 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
853 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
854 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
856 /* ack any pending irq events for this port */
857 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
858 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
860 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
862 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
864 /* set irq mask (enables interrupts) */
865 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
868 tmp
= readl(mmio
+ HOST_CTL
);
869 VPRINTK("HOST_CTL 0x%x\n", tmp
);
870 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
871 tmp
= readl(mmio
+ HOST_CTL
);
872 VPRINTK("HOST_CTL 0x%x\n", tmp
);
874 pci_set_master(pdev
);
879 /* move to PCI layer, integrate w/ MSI stuff */
880 static void pci_intx(struct pci_dev
*pdev
, int enable
)
882 u16 pci_command
, new;
884 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
887 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
889 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
891 if (new != pci_command
)
892 pci_write_config_word(pdev
, PCI_COMMAND
, pci_command
);
895 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
897 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
898 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
899 void *mmio
= probe_ent
->mmio_base
;
900 u32 vers
, cap
, impl
, speed
;
905 vers
= readl(mmio
+ HOST_VERSION
);
907 impl
= hpriv
->port_map
;
909 speed
= (cap
>> 20) & 0xf;
917 pci_read_config_word(pdev
, 0x0a, &cc
);
920 else if (cc
== 0x0106)
922 else if (cc
== 0x0104)
927 printk(KERN_INFO DRV_NAME
"(%s) AHCI %02x%02x.%02x%02x "
928 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
937 ((cap
>> 8) & 0x1f) + 1,
943 printk(KERN_INFO DRV_NAME
"(%s) flags: "
949 cap
& (1 << 31) ? "64bit " : "",
950 cap
& (1 << 30) ? "ncq " : "",
951 cap
& (1 << 28) ? "ilck " : "",
952 cap
& (1 << 27) ? "stag " : "",
953 cap
& (1 << 26) ? "pm " : "",
954 cap
& (1 << 25) ? "led " : "",
956 cap
& (1 << 24) ? "clo " : "",
957 cap
& (1 << 19) ? "nz " : "",
958 cap
& (1 << 18) ? "only " : "",
959 cap
& (1 << 17) ? "pmp " : "",
960 cap
& (1 << 15) ? "pio " : "",
961 cap
& (1 << 14) ? "slum " : "",
962 cap
& (1 << 13) ? "part " : ""
966 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
968 static int printed_version
;
969 struct ata_probe_ent
*probe_ent
= NULL
;
970 struct ahci_host_priv
*hpriv
;
973 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
974 int have_msi
, pci_dev_busy
= 0;
979 if (!printed_version
++)
980 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
982 rc
= pci_enable_device(pdev
);
986 rc
= pci_request_regions(pdev
, DRV_NAME
);
992 if (pci_enable_msi(pdev
) == 0)
999 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1000 if (probe_ent
== NULL
) {
1005 memset(probe_ent
, 0, sizeof(*probe_ent
));
1006 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1007 INIT_LIST_HEAD(&probe_ent
->node
);
1009 mmio_base
= ioremap(pci_resource_start(pdev
, AHCI_PCI_BAR
),
1010 pci_resource_len(pdev
, AHCI_PCI_BAR
));
1011 if (mmio_base
== NULL
) {
1013 goto err_out_free_ent
;
1015 base
= (unsigned long) mmio_base
;
1017 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1020 goto err_out_iounmap
;
1022 memset(hpriv
, 0, sizeof(*hpriv
));
1024 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1025 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1026 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1027 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1028 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1030 probe_ent
->irq
= pdev
->irq
;
1031 probe_ent
->irq_flags
= SA_SHIRQ
;
1032 probe_ent
->mmio_base
= mmio_base
;
1033 probe_ent
->private_data
= hpriv
;
1036 hpriv
->flags
|= AHCI_FLAG_MSI
;
1038 /* initialize adapter */
1039 rc
= ahci_host_init(probe_ent
);
1043 ahci_print_info(probe_ent
);
1045 /* FIXME: check ata_device_add return value */
1046 ata_device_add(probe_ent
);
1059 pci_disable_msi(pdev
);
1062 pci_release_regions(pdev
);
1065 pci_disable_device(pdev
);
1069 static void ahci_remove_one (struct pci_dev
*pdev
)
1071 struct device
*dev
= pci_dev_to_dev(pdev
);
1072 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1073 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1074 struct ata_port
*ap
;
1078 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1079 ap
= host_set
->ports
[i
];
1081 scsi_remove_host(ap
->host
);
1084 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1085 free_irq(host_set
->irq
, host_set
);
1087 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1088 ap
= host_set
->ports
[i
];
1090 ata_scsi_release(ap
->host
);
1091 scsi_host_put(ap
->host
);
1094 host_set
->ops
->host_stop(host_set
);
1098 pci_disable_msi(pdev
);
1101 pci_release_regions(pdev
);
1102 pci_disable_device(pdev
);
1103 dev_set_drvdata(dev
, NULL
);
1106 static int __init
ahci_init(void)
1108 return pci_module_init(&ahci_pci_driver
);
1112 static void __exit
ahci_exit(void)
1114 pci_unregister_driver(&ahci_pci_driver
);
1118 MODULE_AUTHOR("Jeff Garzik");
1119 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1120 MODULE_LICENSE("GPL");
1121 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1123 module_init(ahci_init
);
1124 module_exit(ahci_exit
);