3 * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/delay.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
13 #include <scsi/scsi_host.h>
17 #define DRV_MODULE_NAME "am53c974"
18 #define DRV_MODULE_VERSION "1.00"
20 static bool am53c974_debug
;
21 static bool am53c974_fenab
= true;
23 #define esp_dma_log(f, a...) \
26 shost_printk(KERN_DEBUG, esp->host, f, ##a); \
29 #define ESP_DMA_CMD 0x10
30 #define ESP_DMA_STC 0x11
31 #define ESP_DMA_SPA 0x12
32 #define ESP_DMA_WBC 0x13
33 #define ESP_DMA_WAC 0x14
34 #define ESP_DMA_STATUS 0x15
35 #define ESP_DMA_SMDLA 0x16
36 #define ESP_DMA_WMAC 0x17
38 #define ESP_DMA_CMD_IDLE 0x00
39 #define ESP_DMA_CMD_BLAST 0x01
40 #define ESP_DMA_CMD_ABORT 0x02
41 #define ESP_DMA_CMD_START 0x03
42 #define ESP_DMA_CMD_MASK 0x03
43 #define ESP_DMA_CMD_DIAG 0x04
44 #define ESP_DMA_CMD_MDL 0x10
45 #define ESP_DMA_CMD_INTE_P 0x20
46 #define ESP_DMA_CMD_INTE_D 0x40
47 #define ESP_DMA_CMD_DIR 0x80
49 #define ESP_DMA_STAT_PWDN 0x01
50 #define ESP_DMA_STAT_ERROR 0x02
51 #define ESP_DMA_STAT_ABORT 0x04
52 #define ESP_DMA_STAT_DONE 0x08
53 #define ESP_DMA_STAT_SCSIINT 0x10
54 #define ESP_DMA_STAT_BCMPLT 0x20
56 /* EEPROM is accessed with 16-bit values */
57 #define DC390_EEPROM_READ 0x80
58 #define DC390_EEPROM_LEN 0x40
63 * 8 * 4 bytes of per-device options
64 * followed by HBA specific options
67 /* Per-device options */
68 #define DC390_EE_MODE1 0x00
69 #define DC390_EE_SPEED 0x01
71 /* HBA-specific options */
72 #define DC390_EE_ADAPT_SCSI_ID 0x40
73 #define DC390_EE_MODE2 0x41
74 #define DC390_EE_DELAY 0x42
75 #define DC390_EE_TAG_CMD_NUM 0x43
77 #define DC390_EE_MODE1_PARITY_CHK 0x01
78 #define DC390_EE_MODE1_SYNC_NEGO 0x02
79 #define DC390_EE_MODE1_EN_DISC 0x04
80 #define DC390_EE_MODE1_SEND_START 0x08
81 #define DC390_EE_MODE1_TCQ 0x10
83 #define DC390_EE_MODE2_MORE_2DRV 0x01
84 #define DC390_EE_MODE2_GREATER_1G 0x02
85 #define DC390_EE_MODE2_RST_SCSI_BUS 0x04
86 #define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
87 #define DC390_EE_MODE2_NO_SEEK 0x10
88 #define DC390_EE_MODE2_LUN_CHECK 0x20
95 static void pci_esp_dma_drain(struct esp
*esp
);
97 static inline struct pci_esp_priv
*pci_esp_get_priv(struct esp
*esp
)
99 struct pci_dev
*pdev
= esp
->dev
;
101 return pci_get_drvdata(pdev
);
104 static void pci_esp_write8(struct esp
*esp
, u8 val
, unsigned long reg
)
106 iowrite8(val
, esp
->regs
+ (reg
* 4UL));
109 static u8
pci_esp_read8(struct esp
*esp
, unsigned long reg
)
111 return ioread8(esp
->regs
+ (reg
* 4UL));
114 static void pci_esp_write32(struct esp
*esp
, u32 val
, unsigned long reg
)
116 return iowrite32(val
, esp
->regs
+ (reg
* 4UL));
119 static dma_addr_t
pci_esp_map_single(struct esp
*esp
, void *buf
,
122 return pci_map_single(esp
->dev
, buf
, sz
, dir
);
125 static int pci_esp_map_sg(struct esp
*esp
, struct scatterlist
*sg
,
128 return pci_map_sg(esp
->dev
, sg
, num_sg
, dir
);
131 static void pci_esp_unmap_single(struct esp
*esp
, dma_addr_t addr
,
134 pci_unmap_single(esp
->dev
, addr
, sz
, dir
);
137 static void pci_esp_unmap_sg(struct esp
*esp
, struct scatterlist
*sg
,
140 pci_unmap_sg(esp
->dev
, sg
, num_sg
, dir
);
143 static int pci_esp_irq_pending(struct esp
*esp
)
145 struct pci_esp_priv
*pep
= pci_esp_get_priv(esp
);
147 pep
->dma_status
= pci_esp_read8(esp
, ESP_DMA_STATUS
);
148 esp_dma_log("dma intr dreg[%02x]\n", pep
->dma_status
);
150 if (pep
->dma_status
& (ESP_DMA_STAT_ERROR
|
153 ESP_DMA_STAT_SCSIINT
))
159 static void pci_esp_reset_dma(struct esp
*esp
)
161 /* Nothing to do ? */
164 static void pci_esp_dma_drain(struct esp
*esp
)
170 if ((esp
->sreg
& ESP_STAT_PMASK
) == ESP_DOP
||
171 (esp
->sreg
& ESP_STAT_PMASK
) == ESP_DIP
)
172 /* Data-In or Data-Out, nothing to be done */
176 resid
= pci_esp_read8(esp
, ESP_FFLAGS
) & ESP_FF_FBYTES
;
182 /* FIFO not cleared */
183 shost_printk(KERN_INFO
, esp
->host
,
184 "FIFO not cleared, %d bytes left\n",
189 * When there is a residual BCMPLT will never be set
190 * (obviously). But we still have to issue the BLAST
191 * command, otherwise the data will not being transferred.
192 * But we'll never know when the BLAST operation is
193 * finished. So check for some time and give up eventually.
196 pci_esp_write8(esp
, ESP_DMA_CMD_DIR
| ESP_DMA_CMD_BLAST
, ESP_DMA_CMD
);
197 while (pci_esp_read8(esp
, ESP_DMA_STATUS
) & ESP_DMA_STAT_BCMPLT
) {
202 pci_esp_write8(esp
, ESP_DMA_CMD_DIR
| ESP_DMA_CMD_IDLE
, ESP_DMA_CMD
);
203 esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim
, resid
);
204 /* BLAST residual handling is currently untested */
205 if (WARN_ON_ONCE(resid
== 1)) {
206 struct esp_cmd_entry
*ent
= esp
->active_cmd
;
208 ent
->flags
|= ESP_CMD_FLAG_RESIDUAL
;
212 static void pci_esp_dma_invalidate(struct esp
*esp
)
214 struct pci_esp_priv
*pep
= pci_esp_get_priv(esp
);
216 esp_dma_log("invalidate DMA\n");
218 pci_esp_write8(esp
, ESP_DMA_CMD_IDLE
, ESP_DMA_CMD
);
222 static int pci_esp_dma_error(struct esp
*esp
)
224 struct pci_esp_priv
*pep
= pci_esp_get_priv(esp
);
226 if (pep
->dma_status
& ESP_DMA_STAT_ERROR
) {
227 u8 dma_cmd
= pci_esp_read8(esp
, ESP_DMA_CMD
);
229 if ((dma_cmd
& ESP_DMA_CMD_MASK
) == ESP_DMA_CMD_START
)
230 pci_esp_write8(esp
, ESP_DMA_CMD_ABORT
, ESP_DMA_CMD
);
234 if (pep
->dma_status
& ESP_DMA_STAT_ABORT
) {
235 pci_esp_write8(esp
, ESP_DMA_CMD_IDLE
, ESP_DMA_CMD
);
236 pep
->dma_status
= pci_esp_read8(esp
, ESP_DMA_CMD
);
242 static void pci_esp_send_dma_cmd(struct esp
*esp
, u32 addr
, u32 esp_count
,
243 u32 dma_count
, int write
, u8 cmd
)
245 struct pci_esp_priv
*pep
= pci_esp_get_priv(esp
);
248 BUG_ON(!(cmd
& ESP_CMD_DMA
));
252 /* Set DMA engine to IDLE */
254 /* DMA write direction logic is inverted */
255 val
|= ESP_DMA_CMD_DIR
;
256 pci_esp_write8(esp
, ESP_DMA_CMD_IDLE
| val
, ESP_DMA_CMD
);
258 pci_esp_write8(esp
, (esp_count
>> 0) & 0xff, ESP_TCLOW
);
259 pci_esp_write8(esp
, (esp_count
>> 8) & 0xff, ESP_TCMED
);
260 if (esp
->config2
& ESP_CONFIG2_FENAB
)
261 pci_esp_write8(esp
, (esp_count
>> 16) & 0xff, ESP_TCHI
);
263 pci_esp_write32(esp
, esp_count
, ESP_DMA_STC
);
264 pci_esp_write32(esp
, addr
, ESP_DMA_SPA
);
266 esp_dma_log("start dma addr[%x] count[%d:%d]\n",
267 addr
, esp_count
, dma_count
);
269 scsi_esp_cmd(esp
, cmd
);
270 /* Send DMA Start command */
271 pci_esp_write8(esp
, ESP_DMA_CMD_START
| val
, ESP_DMA_CMD
);
274 static u32
pci_esp_dma_length_limit(struct esp
*esp
, u32 dma_addr
, u32 dma_len
)
280 * If CONFIG2_FENAB is set we can
281 * handle up to 24 bit addresses
283 if (esp
->config2
& ESP_CONFIG2_FENAB
)
286 if (dma_len
> (1U << dma_limit
))
287 dma_len
= (1U << dma_limit
);
290 * Prevent crossing a 24-bit address boundary.
292 base
= dma_addr
& ((1U << 24) - 1U);
293 end
= base
+ dma_len
;
294 if (end
> (1U << 24))
296 dma_len
= end
- base
;
301 static const struct esp_driver_ops pci_esp_ops
= {
302 .esp_write8
= pci_esp_write8
,
303 .esp_read8
= pci_esp_read8
,
304 .map_single
= pci_esp_map_single
,
305 .map_sg
= pci_esp_map_sg
,
306 .unmap_single
= pci_esp_unmap_single
,
307 .unmap_sg
= pci_esp_unmap_sg
,
308 .irq_pending
= pci_esp_irq_pending
,
309 .reset_dma
= pci_esp_reset_dma
,
310 .dma_drain
= pci_esp_dma_drain
,
311 .dma_invalidate
= pci_esp_dma_invalidate
,
312 .send_dma_cmd
= pci_esp_send_dma_cmd
,
313 .dma_error
= pci_esp_dma_error
,
314 .dma_length_limit
= pci_esp_dma_length_limit
,
320 static void dc390_eeprom_prepare_read(struct pci_dev
*pdev
, u8 cmd
)
322 u8 carry_flag
= 1, j
= 0x80, bval
;
325 for (i
= 0; i
< 9; i
++) {
327 pci_write_config_byte(pdev
, 0x80, 0x40);
333 pci_write_config_byte(pdev
, 0x80, bval
);
335 pci_write_config_byte(pdev
, 0x80, 0);
338 carry_flag
= (cmd
& j
) ? 1 : 0;
343 static u16
dc390_eeprom_get_data(struct pci_dev
*pdev
)
349 for (i
= 0; i
< 16; i
++) {
352 pci_write_config_byte(pdev
, 0x80, 0x80);
354 pci_write_config_byte(pdev
, 0x80, 0x40);
356 pci_read_config_byte(pdev
, 0x00, &bval
);
365 static void dc390_read_eeprom(struct pci_dev
*pdev
, u16
*ptr
)
367 u8 cmd
= DC390_EEPROM_READ
, i
;
369 for (i
= 0; i
< DC390_EEPROM_LEN
; i
++) {
370 pci_write_config_byte(pdev
, 0xc0, 0);
373 dc390_eeprom_prepare_read(pdev
, cmd
++);
374 *ptr
++ = dc390_eeprom_get_data(pdev
);
376 pci_write_config_byte(pdev
, 0x80, 0);
377 pci_write_config_byte(pdev
, 0x80, 0);
382 static void dc390_check_eeprom(struct esp
*esp
)
385 u16
*ptr
= (u16
*)EEbuf
, wval
= 0;
388 dc390_read_eeprom((struct pci_dev
*)esp
->dev
, ptr
);
390 for (i
= 0; i
< DC390_EEPROM_LEN
; i
++, ptr
++)
393 /* no Tekram EEprom found */
394 if (wval
!= 0x1234) {
395 struct pci_dev
*pdev
= esp
->dev
;
396 dev_printk(KERN_INFO
, &pdev
->dev
,
397 "No valid Tekram EEprom found\n");
400 esp
->scsi_id
= EEbuf
[DC390_EE_ADAPT_SCSI_ID
];
401 esp
->num_tags
= 2 << EEbuf
[DC390_EE_TAG_CMD_NUM
];
402 if (EEbuf
[DC390_EE_MODE2
] & DC390_EE_MODE2_ACTIVE_NEGATION
)
403 esp
->config4
|= ESP_CONFIG4_RADE
| ESP_CONFIG4_RAE
;
406 static int pci_esp_probe_one(struct pci_dev
*pdev
,
407 const struct pci_device_id
*id
)
409 struct scsi_host_template
*hostt
= &scsi_esp_template
;
411 struct Scsi_Host
*shost
;
413 struct pci_esp_priv
*pep
;
415 if (pci_enable_device(pdev
)) {
416 dev_printk(KERN_INFO
, &pdev
->dev
, "cannot enable device\n");
420 if (pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
421 dev_printk(KERN_INFO
, &pdev
->dev
,
422 "failed to set 32bit DMA mask\n");
423 goto fail_disable_device
;
426 shost
= scsi_host_alloc(hostt
, sizeof(struct esp
));
428 dev_printk(KERN_INFO
, &pdev
->dev
,
429 "failed to allocate scsi host\n");
431 goto fail_disable_device
;
434 pep
= kzalloc(sizeof(struct pci_esp_priv
), GFP_KERNEL
);
436 dev_printk(KERN_INFO
, &pdev
->dev
,
437 "failed to allocate esp_priv\n");
439 goto fail_host_alloc
;
442 esp
= shost_priv(shost
);
445 esp
->ops
= &pci_esp_ops
;
447 * The am53c974 HBA has a design flaw of generating
448 * spurious DMA completion interrupts when using
449 * DMA for command submission.
451 esp
->flags
|= ESP_FLAG_USE_FIFO
;
453 * Enable CONFIG2_FENAB to allow for large DMA transfers
456 esp
->config2
|= ESP_CONFIG2_FENAB
;
460 if (pci_request_regions(pdev
, DRV_MODULE_NAME
)) {
461 dev_printk(KERN_ERR
, &pdev
->dev
,
462 "pci memory selection failed\n");
463 goto fail_priv_alloc
;
466 esp
->regs
= pci_iomap(pdev
, 0, pci_resource_len(pdev
, 0));
468 dev_printk(KERN_ERR
, &pdev
->dev
, "pci I/O map failed\n");
470 goto fail_release_regions
;
472 esp
->dma_regs
= esp
->regs
;
474 pci_set_master(pdev
);
476 esp
->command_block
= pci_alloc_consistent(pdev
, 16,
477 &esp
->command_block_dma
);
478 if (!esp
->command_block
) {
479 dev_printk(KERN_ERR
, &pdev
->dev
,
480 "failed to allocate command block\n");
482 goto fail_unmap_regs
;
485 err
= request_irq(pdev
->irq
, scsi_esp_intr
, IRQF_SHARED
,
486 DRV_MODULE_NAME
, esp
);
488 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to register IRQ\n");
489 goto fail_unmap_command_block
;
493 dc390_check_eeprom(esp
);
495 shost
->this_id
= esp
->scsi_id
;
497 shost
->irq
= pdev
->irq
;
498 shost
->io_port
= pci_resource_start(pdev
, 0);
499 shost
->n_io_port
= pci_resource_len(pdev
, 0);
500 shost
->unique_id
= shost
->io_port
;
501 esp
->scsi_id_mask
= (1 << esp
->scsi_id
);
502 /* Assume 40MHz clock */
503 esp
->cfreq
= 40000000;
505 pci_set_drvdata(pdev
, pep
);
507 err
= scsi_esp_register(esp
, &pdev
->dev
);
514 free_irq(pdev
->irq
, esp
);
515 fail_unmap_command_block
:
516 pci_free_consistent(pdev
, 16, esp
->command_block
,
517 esp
->command_block_dma
);
519 pci_iounmap(pdev
, esp
->regs
);
520 fail_release_regions
:
521 pci_release_regions(pdev
);
525 scsi_host_put(shost
);
527 pci_disable_device(pdev
);
532 static void pci_esp_remove_one(struct pci_dev
*pdev
)
534 struct pci_esp_priv
*pep
= pci_get_drvdata(pdev
);
535 struct esp
*esp
= pep
->esp
;
537 scsi_esp_unregister(esp
);
538 free_irq(pdev
->irq
, esp
);
539 pci_free_consistent(pdev
, 16, esp
->command_block
,
540 esp
->command_block_dma
);
541 pci_iounmap(pdev
, esp
->regs
);
542 pci_release_regions(pdev
);
543 pci_disable_device(pdev
);
546 scsi_host_put(esp
->host
);
549 static struct pci_device_id am53c974_pci_tbl
[] = {
550 { PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_SCSI
,
551 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
554 MODULE_DEVICE_TABLE(pci
, am53c974_pci_tbl
);
556 static struct pci_driver am53c974_driver
= {
557 .name
= DRV_MODULE_NAME
,
558 .id_table
= am53c974_pci_tbl
,
559 .probe
= pci_esp_probe_one
,
560 .remove
= pci_esp_remove_one
,
563 static int __init
am53c974_module_init(void)
565 return pci_register_driver(&am53c974_driver
);
568 static void __exit
am53c974_module_exit(void)
570 pci_unregister_driver(&am53c974_driver
);
573 MODULE_DESCRIPTION("AM53C974 SCSI driver");
574 MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
575 MODULE_LICENSE("GPL");
576 MODULE_VERSION(DRV_MODULE_VERSION
);
577 MODULE_ALIAS("tmscsim");
579 module_param(am53c974_debug
, bool, 0644);
580 MODULE_PARM_DESC(am53c974_debug
, "Enable debugging");
582 module_param(am53c974_fenab
, bool, 0444);
583 MODULE_PARM_DESC(am53c974_fenab
, "Enable 24-bit DMA transfer sizes");
585 module_init(am53c974_module_init
);
586 module_exit(am53c974_module_exit
);