drivers/scsi/hpsa_cmd.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_CMD_H
  22 #define HPSA_CMD_H
  23
  24 /* general boundary defintions */
  25 #define SENSEINFOBYTES          32 /* may vary between hbas */
  26 #define SG_ENTRIES_IN_CMD       32 /* Max SG entries excluding chain blocks */
  27 #define HPSA_SG_CHAIN           0x80000000
  28 #define HPSA_SG_LAST            0x40000000
  29 #define MAXREPLYQS              256
  30
  31 /* Command Status value */
  32 #define CMD_SUCCESS             0x0000
  33 #define CMD_TARGET_STATUS       0x0001
  34 #define CMD_DATA_UNDERRUN       0x0002
  35 #define CMD_DATA_OVERRUN        0x0003
  36 #define CMD_INVALID             0x0004
  37 #define CMD_PROTOCOL_ERR        0x0005
  38 #define CMD_HARDWARE_ERR        0x0006
  39 #define CMD_CONNECTION_LOST     0x0007
  40 #define CMD_ABORTED             0x0008
  41 #define CMD_ABORT_FAILED        0x0009
  42 #define CMD_UNSOLICITED_ABORT   0x000A
  43 #define CMD_TIMEOUT             0x000B
  44 #define CMD_UNABORTABLE         0x000C
  45 #define CMD_IOACCEL_DISABLED    0x000E
  46
  47
  48 /* Unit Attentions ASC's as defined for the MSA2012sa */
  49 #define POWER_OR_RESET                  0x29
  50 #define STATE_CHANGED                   0x2a
  51 #define UNIT_ATTENTION_CLEARED          0x2f
  52 #define LUN_FAILED                      0x3e
  53 #define REPORT_LUNS_CHANGED             0x3f
  54
  55 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  56
  57         /* These ASCQ's defined for ASC = POWER_OR_RESET */
  58 #define POWER_ON_RESET                  0x00
  59 #define POWER_ON_REBOOT                 0x01
  60 #define SCSI_BUS_RESET                  0x02
  61 #define MSA_TARGET_RESET                0x03
  62 #define CONTROLLER_FAILOVER             0x04
  63 #define TRANSCEIVER_SE                  0x05
  64 #define TRANSCEIVER_LVD                 0x06
  65
  66         /* These ASCQ's defined for ASC = STATE_CHANGED */
  67 #define RESERVATION_PREEMPTED           0x03
  68 #define ASYM_ACCESS_CHANGED             0x06
  69 #define LUN_CAPACITY_CHANGED            0x09
  70
  71 /* transfer direction */
  72 #define XFER_NONE               0x00
  73 #define XFER_WRITE              0x01
  74 #define XFER_READ               0x02
  75 #define XFER_RSVD               0x03
  76
  77 /* task attribute */
  78 #define ATTR_UNTAGGED           0x00
  79 #define ATTR_SIMPLE             0x04
  80 #define ATTR_HEADOFQUEUE        0x05
  81 #define ATTR_ORDERED            0x06
  82 #define ATTR_ACA                0x07
  83
  84 /* cdb type */
  85 #define TYPE_CMD                0x00
  86 #define TYPE_MSG                0x01
  87 #define TYPE_IOACCEL2_CMD       0x81 /* 0x81 is not used by hardware */
  88
  89 /* Message Types  */
  90 #define HPSA_TASK_MANAGEMENT    0x00
  91 #define HPSA_RESET              0x01
  92 #define HPSA_SCAN               0x02
  93 #define HPSA_NOOP               0x03
  94
  95 #define HPSA_CTLR_RESET_TYPE    0x00
  96 #define HPSA_BUS_RESET_TYPE     0x01
  97 #define HPSA_TARGET_RESET_TYPE  0x03
  98 #define HPSA_LUN_RESET_TYPE     0x04
  99 #define HPSA_NEXUS_RESET_TYPE   0x05
 100
 101 /* Task Management Functions */
 102 #define HPSA_TMF_ABORT_TASK     0x00
 103 #define HPSA_TMF_ABORT_TASK_SET 0x01
 104 #define HPSA_TMF_CLEAR_ACA      0x02
 105 #define HPSA_TMF_CLEAR_TASK_SET 0x03
 106 #define HPSA_TMF_QUERY_TASK     0x04
 107 #define HPSA_TMF_QUERY_TASK_SET 0x05
 108 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
 109
 110
 111
 112 /* config space register offsets */
 113 #define CFG_VENDORID            0x00
 114 #define CFG_DEVICEID            0x02
 115 #define CFG_I2OBAR              0x10
 116 #define CFG_MEM1BAR             0x14
 117
 118 /* i2o space register offsets */
 119 #define I2O_IBDB_SET            0x20
 120 #define I2O_IBDB_CLEAR          0x70
 121 #define I2O_INT_STATUS          0x30
 122 #define I2O_INT_MASK            0x34
 123 #define I2O_IBPOST_Q            0x40
 124 #define I2O_OBPOST_Q            0x44
 125 #define I2O_DMA1_CFG            0x214
 126
 127 /* Configuration Table */
 128 #define CFGTBL_ChangeReq        0x00000001l
 129 #define CFGTBL_AccCmds          0x00000001l
 130 #define DOORBELL_CTLR_RESET     0x00000004l
 131 #define DOORBELL_CTLR_RESET2    0x00000020l
 132 #define DOORBELL_CLEAR_EVENTS   0x00000040l
 133
 134 #define CFGTBL_Trans_Simple     0x00000002l
 135 #define CFGTBL_Trans_Performant 0x00000004l
 136 #define CFGTBL_Trans_io_accel1  0x00000080l
 137 #define CFGTBL_Trans_io_accel2  0x00000100l
 138 #define CFGTBL_Trans_use_short_tags 0x20000000l
 139 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
 140
 141 #define CFGTBL_BusType_Ultra2   0x00000001l
 142 #define CFGTBL_BusType_Ultra3   0x00000002l
 143 #define CFGTBL_BusType_Fibre1G  0x00000100l
 144 #define CFGTBL_BusType_Fibre2G  0x00000200l
 145
 146 /* VPD Inquiry types */
 147 #define HPSA_VPD_SUPPORTED_PAGES        0x00
 148 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
 149 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
 150 #define HPSA_VPD_HEADER_SZ              4
 151
 152 struct vals32 {
 153         u32   lower;
 154         u32   upper;
 155 };
 156
 157 union u64bit {
 158         struct vals32 val32;
 159         u64 val;
 160 };
 161
 162 /* FIXME this is a per controller value (barf!) */
 163 #define HPSA_MAX_LUN 1024
 164 #define HPSA_MAX_PHYS_LUN 1024
 165 #define MAX_EXT_TARGETS 32
 166 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
 167         MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
 168
 169 /* SCSI-3 Commands */
 170 #pragma pack(1)
 171
 172 #define HPSA_INQUIRY 0x12
 173 struct InquiryData {
 174         u8 data_byte[36];
 175 };
 176
 177 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
 178 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
 179 #define HPSA_REPORT_PHYS_EXTENDED 0x02
 180 #define HPSA_CISS_READ  0xc0    /* CISS Read */
 181 #define HPSA_GET_RAID_MAP 0xc8  /* CISS Get RAID Layout Map */
 182
 183 #define RAID_MAP_MAX_ENTRIES   256
 184
 185 struct raid_map_disk_data {
 186         u32   ioaccel_handle;         /**< Handle to access this disk via the
 187                                         *  I/O accelerator */
 188         u8    xor_mult[2];            /**< XOR multipliers for this position,
 189                                         *  valid for data disks only */
 190         u8    reserved[2];
 191 };
 192
 193 struct raid_map_data {
 194         u32   structure_size;           /* Size of entire structure in bytes */
 195         u32   volume_blk_size;          /* bytes / block in the volume */
 196         u64   volume_blk_cnt;           /* logical blocks on the volume */
 197         u8    phys_blk_shift;           /* Shift factor to convert between
 198                                          * units of logical blocks and physical
 199                                          * disk blocks */
 200         u8    parity_rotation_shift;    /* Shift factor to convert between units
 201                                          * of logical stripes and physical
 202                                          * stripes */
 203         u16   strip_size;               /* blocks used on each disk / stripe */
 204         u64   disk_starting_blk;        /* First disk block used in volume */
 205         u64   disk_blk_cnt;             /* disk blocks used by volume / disk */
 206         u16   data_disks_per_row;       /* data disk entries / row in the map */
 207         u16   metadata_disks_per_row;   /* mirror/parity disk entries / row
 208                                          * in the map */
 209         u16   row_cnt;                  /* rows in each layout map */
 210         u16   layout_map_count;         /* layout maps (1 map per mirror/parity
 211                                          * group) */
 212         u8    reserved[20];
 213         struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
 214 };
 215
 216 struct ReportLUNdata {
 217         u8 LUNListLength[4];
 218         u8 extended_response_flag;
 219         u8 reserved[3];
 220         u8 LUN[HPSA_MAX_LUN][8];
 221 };
 222
 223 struct ReportExtendedLUNdata {
 224         u8 LUNListLength[4];
 225         u8 extended_response_flag;
 226         u8 reserved[3];
 227         u8 LUN[HPSA_MAX_LUN][24];
 228 };
 229
 230 struct SenseSubsystem_info {
 231         u8 reserved[36];
 232         u8 portname[8];
 233         u8 reserved1[1108];
 234 };
 235
 236 /* BMIC commands */
 237 #define BMIC_READ 0x26
 238 #define BMIC_WRITE 0x27
 239 #define BMIC_CACHE_FLUSH 0xc2
 240 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
 241 #define BMIC_FLASH_FIRMWARE 0xF7
 242
 243 /* Command List Structure */
 244 union SCSI3Addr {
 245         struct {
 246                 u8 Dev;
 247                 u8 Bus:6;
 248                 u8 Mode:2;        /* b00 */
 249         } PeripDev;
 250         struct {
 251                 u8 DevLSB;
 252                 u8 DevMSB:6;
 253                 u8 Mode:2;        /* b01 */
 254         } LogDev;
 255         struct {
 256                 u8 Dev:5;
 257                 u8 Bus:3;
 258                 u8 Targ:6;
 259                 u8 Mode:2;        /* b10 */
 260         } LogUnit;
 261 };
 262
 263 struct PhysDevAddr {
 264         u32             TargetId:24;
 265         u32             Bus:6;
 266         u32             Mode:2;
 267         /* 2 level target device addr */
 268         union SCSI3Addr  Target[2];
 269 };
 270
 271 struct LogDevAddr {
 272         u32            VolId:30;
 273         u32            Mode:2;
 274         u8             reserved[4];
 275 };
 276
 277 union LUNAddr {
 278         u8               LunAddrBytes[8];
 279         union SCSI3Addr    SCSI3Lun[4];
 280         struct PhysDevAddr PhysDev;
 281         struct LogDevAddr  LogDev;
 282 };
 283
 284 struct CommandListHeader {
 285         u8              ReplyQueue;
 286         u8              SGList;
 287         u16             SGTotal;
 288         struct vals32     Tag;
 289         union LUNAddr     LUN;
 290 };
 291
 292 struct RequestBlock {
 293         u8   CDBLen;
 294         struct {
 295                 u8 Type:3;
 296                 u8 Attribute:3;
 297                 u8 Direction:2;
 298         } Type;
 299         u16  Timeout;
 300         u8   CDB[16];
 301 };
 302
 303 struct ErrDescriptor {
 304         struct vals32 Addr;
 305         u32  Len;
 306 };
 307
 308 struct SGDescriptor {
 309         struct vals32 Addr;
 310         u32  Len;
 311         u32  Ext;
 312 };
 313
 314 union MoreErrInfo {
 315         struct {
 316                 u8  Reserved[3];
 317                 u8  Type;
 318                 u32 ErrorInfo;
 319         } Common_Info;
 320         struct {
 321                 u8  Reserved[2];
 322                 u8  offense_size; /* size of offending entry */
 323                 u8  offense_num;  /* byte # of offense 0-base */
 324                 u32 offense_value;
 325         } Invalid_Cmd;
 326 };
 327 struct ErrorInfo {
 328         u8               ScsiStatus;
 329         u8               SenseLen;
 330         u16              CommandStatus;
 331         u32              ResidualCnt;
 332         union MoreErrInfo  MoreErrInfo;
 333         u8               SenseInfo[SENSEINFOBYTES];
 334 };
 335 /* Command types */
 336 #define CMD_IOCTL_PEND  0x01
 337 #define CMD_SCSI        0x03
 338 #define CMD_IOACCEL1    0x04
 339 #define CMD_IOACCEL2    0x05
 340
 341 #define DIRECT_LOOKUP_SHIFT 5
 342 #define DIRECT_LOOKUP_BIT 0x10
 343 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
 344
 345 #define HPSA_ERROR_BIT          0x02
 346 struct ctlr_info; /* defined in hpsa.h */
 347 /* The size of this structure needs to be divisible by 32
 348  * on all architectures because low 5 bits of the addresses
 349  * are used as follows:
 350  *
 351  * bit 0: to device, used to indicate "performant mode" command
 352  *        from device, indidcates error status.
 353  * bit 1-3: to device, indicates block fetch table entry for
 354  *          reducing DMA in fetching commands from host memory.
 355  * bit 4: used to indicate whether tag is "direct lookup" (index),
 356  *        or a bus address.
 357  */
 358
 359 struct CommandList {
 360         struct CommandListHeader Header;
 361         struct RequestBlock      Request;
 362         struct ErrDescriptor     ErrDesc;
 363         struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
 364         /* information associated with the command */
 365         u32                        busaddr; /* physical addr of this record */
 366         struct ErrorInfo *err_info; /* pointer to the allocated mem */
 367         struct ctlr_info           *h;
 368         int                        cmd_type;
 369         long                       cmdindex;
 370         struct list_head list;
 371         struct request *rq;
 372         struct completion *waiting;
 373         void   *scsi_cmd;
 374
 375 /* on 64 bit architectures, to get this to be 32-byte-aligned
 376  * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 377  * we need PAD_32 bytes of padding (see below).   This does that.
 378  * If it happens that 64 bit and 32 bit systems need different
 379  * padding, PAD_32 and PAD_64 can be set independently, and.
 380  * the code below will do the right thing.
 381  */
 382 #define IS_32_BIT ((8 - sizeof(long))/4)
 383 #define IS_64_BIT (!IS_32_BIT)
 384 #define PAD_32 (36)
 385 #define PAD_64 (4)
 386 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
 387         u8 pad[COMMANDLIST_PAD];
 388 };
 389
 390 /* Max S/G elements in I/O accelerator command */
 391 #define IOACCEL1_MAXSGENTRIES           24
 392 #define IOACCEL2_MAXSGENTRIES           28
 393
 394 /*
 395  * Structure for I/O accelerator (mode 1) commands.
 396  * Note that this structure must be 128-byte aligned in size.
 397  */
 398 struct io_accel1_cmd {
 399         u16 dev_handle;                 /* 0x00 - 0x01 */
 400         u8  reserved1;                  /* 0x02 */
 401         u8  function;                   /* 0x03 */
 402         u8  reserved2[8];               /* 0x04 - 0x0B */
 403         u32 err_info;                   /* 0x0C - 0x0F */
 404         u8  reserved3[2];               /* 0x10 - 0x11 */
 405         u8  err_info_len;               /* 0x12 */
 406         u8  reserved4;                  /* 0x13 */
 407         u8  sgl_offset;                 /* 0x14 */
 408         u8  reserved5[7];               /* 0x15 - 0x1B */
 409         u32 transfer_len;               /* 0x1C - 0x1F */
 410         u8  reserved6[4];               /* 0x20 - 0x23 */
 411         u16 io_flags;                   /* 0x24 - 0x25 */
 412         u8  reserved7[14];              /* 0x26 - 0x33 */
 413         u8  LUN[8];                     /* 0x34 - 0x3B */
 414         u32 control;                    /* 0x3C - 0x3F */
 415         u8  CDB[16];                    /* 0x40 - 0x4F */
 416         u8  reserved8[16];              /* 0x50 - 0x5F */
 417         u16 host_context_flags;         /* 0x60 - 0x61 */
 418         u16 timeout_sec;                /* 0x62 - 0x63 */
 419         u8  ReplyQueue;                 /* 0x64 */
 420         u8  reserved9[3];               /* 0x65 - 0x67 */
 421         struct vals32 Tag;              /* 0x68 - 0x6F */
 422         struct vals32 host_addr;        /* 0x70 - 0x77 */
 423         u8  CISS_LUN[8];                /* 0x78 - 0x7F */
 424         struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
 425 #define IOACCEL1_PAD_64 0
 426 #define IOACCEL1_PAD_32 0
 427 #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \
 428                         IS_64_BIT * IOACCEL1_PAD_64)
 429         u8 pad[IOACCEL1_PAD];
 430 };
 431
 432 #define IOACCEL1_FUNCTION_SCSIIO        0x00
 433 #define IOACCEL1_SGLOFFSET              32
 434
 435 #define IOACCEL1_IOFLAGS_IO_REQ         0x4000
 436 #define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
 437 #define IOACCEL1_IOFLAGS_CDBLEN_MAX     16
 438
 439 #define IOACCEL1_CONTROL_NODATAXFER     0x00000000
 440 #define IOACCEL1_CONTROL_DATA_OUT       0x01000000
 441 #define IOACCEL1_CONTROL_DATA_IN        0x02000000
 442 #define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
 443 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
 444 #define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
 445 #define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
 446 #define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
 447 #define IOACCEL1_CONTROL_ACA            0x00000400
 448
 449 #define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013
 450
 451 #define IOACCEL1_BUSADDR_CMDTYPE        0x00000060
 452
 453 struct ioaccel2_sg_element {
 454         u64 address;
 455         u32 length;
 456         u8 reserved[3];
 457         u8 chain_indicator;
 458 #define IOACCEL2_CHAIN 0x80
 459 };
 460
 461 /*
 462  * SCSI Response Format structure for IO Accelerator Mode 2
 463  */
 464 struct io_accel2_scsi_response {
 465         u8 IU_type;
 466 #define IOACCEL2_IU_TYPE_SRF                    0x60
 467         u8 reserved1[3];
 468         u8 req_id[4];           /* request identifier */
 469         u8 reserved2[4];
 470         u8 serv_response;               /* service response */
 471 #define IOACCEL2_SERV_RESPONSE_COMPLETE         0x000
 472 #define IOACCEL2_SERV_RESPONSE_FAILURE          0x001
 473 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE     0x002
 474 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS      0x003
 475 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED     0x004
 476 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN    0x005
 477         u8 status;                      /* status */
 478 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD       0x00
 479 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND   0x02
 480 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY       0x08
 481 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON    0x18
 482 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL   0x28
 483 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED    0x40
 484 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED     0x0E
 485         u8 data_present;                /* low 2 bits */
 486 #define IOACCEL2_NO_DATAPRESENT         0x000
 487 #define IOACCEL2_RESPONSE_DATAPRESENT   0x001
 488 #define IOACCEL2_SENSE_DATA_PRESENT     0x002
 489 #define IOACCEL2_RESERVED               0x003
 490         u8 sense_data_len;              /* sense/response data length */
 491         u8 resid_cnt[4];                /* residual count */
 492         u8 sense_data_buff[32];         /* sense/response data buffer */
 493 };
 494
 495 #define IOACCEL2_64_PAD 76
 496 #define IOACCEL2_32_PAD 76
 497 #define IOACCEL2_PAD (IS_32_BIT * IOACCEL2_32_PAD + \
 498                         IS_64_BIT * IOACCEL2_64_PAD)
 499 /*
 500  * Structure for I/O accelerator (mode 2 or m2) commands.
 501  * Note that this structure must be 128-byte aligned in size.
 502  */
 503 struct io_accel2_cmd {
 504         u8  IU_type;                    /* IU Type */
 505         u8  direction;                  /* Transfer direction, 2 bits */
 506         u8  reply_queue;                /* Reply Queue ID */
 507         u8  reserved1;                  /* Reserved */
 508         u32 scsi_nexus;                 /* Device Handle */
 509         struct vals32 Tag;              /* cciss tag */
 510         u8  cdb[16];                    /* SCSI Command Descriptor Block */
 511         u8  cciss_lun[8];               /* 8 byte SCSI address */
 512         u32 data_len;                   /* Total bytes to transfer */
 513         u8  cmd_priority_task_attr;     /* priority and task attrs */
 514 #define IOACCEL2_PRIORITY_MASK 0x78
 515 #define IOACCEL2_ATTR_MASK 0x07
 516         u8  sg_count;                   /* Number of sg elements */
 517         u8  reserved3[2];               /* Reserved */
 518         u64 err_ptr;                    /* Error Pointer */
 519         u32 err_len;                    /* Error Length*/
 520         u8 reserved4[4];                /* Reserved */
 521         struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
 522         struct io_accel2_scsi_response error_data;
 523         u8 pad[IOACCEL2_PAD];
 524 };
 525
 526 /*
 527  * defines for Mode 2 command struct
 528  * FIXME: this can't be all I need mfm
 529  */
 530 #define IOACCEL2_IU_TYPE        0x40
 531 #define IOACCEL2_IU_TMF_TYPE    0x41
 532 #define IOACCEL2_DIR_NO_DATA    0x00
 533 #define IOACCEL2_DIR_DATA_IN    0x01
 534 #define IOACCEL2_DIR_DATA_OUT   0x02
 535 /*
 536  * SCSI Task Management Request format for Accelerator Mode 2
 537  */
 538 struct hpsa_tmf_struct {
 539         u8 iu_type;             /* Information Unit Type */
 540         u8 reply_queue;         /* Reply Queue ID */
 541         u8 tmf;                 /* Task Management Function */
 542         u8 reserved1;           /* byte 3 Reserved */
 543         u32 it_nexus;           /* SCSI I-T Nexus */
 544         u8 lun_id[8];           /* LUN ID for TMF request */
 545         struct vals32 Tag;      /* cciss tag associated w/ request */
 546         struct vals32 abort_tag;/* cciss tag of SCSI cmd or task to abort */
 547         u64 error_ptr;          /* Error Pointer */
 548         u32 error_len;          /* Error Length */
 549 };
 550
 551 /* Configuration Table Structure */
 552 struct HostWrite {
 553         u32 TransportRequest;
 554         u32 command_pool_addr_hi;
 555         u32 CoalIntDelay;
 556         u32 CoalIntCount;
 557 };
 558
 559 #define SIMPLE_MODE     0x02
 560 #define PERFORMANT_MODE 0x04
 561 #define MEMQ_MODE       0x08
 562 #define IOACCEL_MODE_1  0x80
 563
 564 #define DRIVER_SUPPORT_UA_ENABLE        0x00000001
 565
 566 struct CfgTable {
 567         u8            Signature[4];
 568         u32             SpecValence;
 569         u32           TransportSupport;
 570         u32           TransportActive;
 571         struct          HostWrite HostWrite;
 572         u32           CmdsOutMax;
 573         u32           BusTypes;
 574         u32           TransMethodOffset;
 575         u8            ServerName[16];
 576         u32           HeartBeat;
 577         u32           driver_support;
 578 #define                 ENABLE_SCSI_PREFETCH 0x100
 579 #define                 ENABLE_UNIT_ATTN 0x01
 580         u32             MaxScatterGatherElements;
 581         u32             MaxLogicalUnits;
 582         u32             MaxPhysicalDevices;
 583         u32             MaxPhysicalDrivesPerLogicalUnit;
 584         u32             MaxPerformantModeCommands;
 585         u32             MaxBlockFetch;
 586         u32             PowerConservationSupport;
 587         u32             PowerConservationEnable;
 588         u32             TMFSupportFlags;
 589         u8              TMFTagMask[8];
 590         u8              reserved[0x78 - 0x70];
 591         u32             misc_fw_support; /* offset 0x78 */
 592 #define                 MISC_FW_DOORBELL_RESET (0x02)
 593 #define                 MISC_FW_DOORBELL_RESET2 (0x010)
 594 #define                 MISC_FW_RAID_OFFLOAD_BASIC (0x020)
 595 #define                 MISC_FW_EVENT_NOTIFY (0x080)
 596         u8              driver_version[32];
 597         u32             max_cached_write_size;
 598         u8              driver_scratchpad[16];
 599         u32             max_error_info_length;
 600         u32             io_accel_max_embedded_sg_count;
 601         u32             io_accel_request_size_offset;
 602         u32             event_notify;
 603 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
 604 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
 605         u32             clear_event_notify;
 606 };
 607
 608 #define NUM_BLOCKFETCH_ENTRIES 8
 609 struct TransTable_struct {
 610         u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
 611         u32            RepQSize;
 612         u32            RepQCount;
 613         u32            RepQCtrAddrLow32;
 614         u32            RepQCtrAddrHigh32;
 615 #define MAX_REPLY_QUEUES 8
 616         struct vals32  RepQAddr[MAX_REPLY_QUEUES];
 617 };
 618
 619 struct hpsa_pci_info {
 620         unsigned char   bus;
 621         unsigned char   dev_fn;
 622         unsigned short  domain;
 623         u32             board_id;
 624 };
 625
 626 #pragma pack()
 627 #endif /* HPSA_CMD_H */