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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / drivers / scsi / ipr.h
1 /*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26 #ifndef _IPR_H
27 #define _IPR_H
28
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/blk-iopoll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
38
39 /*
40 * Literals
41 */
42 #define IPR_DRIVER_VERSION "2.6.0"
43 #define IPR_DRIVER_DATE "(November 16, 2012)"
44
45 /*
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
49 */
50 #define IPR_MAX_CMD_PER_LUN 6
51 #define IPR_MAX_CMD_PER_ATA_LUN 1
52
53 /*
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
56 */
57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63
64 #define IPR_SUBS_DEV_ID_2780 0x0264
65 #define IPR_SUBS_DEV_ID_5702 0x0266
66 #define IPR_SUBS_DEV_ID_5703 0x0278
67 #define IPR_SUBS_DEV_ID_572E 0x028D
68 #define IPR_SUBS_DEV_ID_573E 0x02D3
69 #define IPR_SUBS_DEV_ID_573D 0x02D4
70 #define IPR_SUBS_DEV_ID_571A 0x02C0
71 #define IPR_SUBS_DEV_ID_571B 0x02BE
72 #define IPR_SUBS_DEV_ID_571E 0x02BF
73 #define IPR_SUBS_DEV_ID_571F 0x02D5
74 #define IPR_SUBS_DEV_ID_572A 0x02C1
75 #define IPR_SUBS_DEV_ID_572B 0x02C2
76 #define IPR_SUBS_DEV_ID_572F 0x02C3
77 #define IPR_SUBS_DEV_ID_574E 0x030A
78 #define IPR_SUBS_DEV_ID_575B 0x030D
79 #define IPR_SUBS_DEV_ID_575C 0x0338
80 #define IPR_SUBS_DEV_ID_57B3 0x033A
81 #define IPR_SUBS_DEV_ID_57B7 0x0360
82 #define IPR_SUBS_DEV_ID_57B8 0x02C2
83
84 #define IPR_SUBS_DEV_ID_57B4 0x033B
85 #define IPR_SUBS_DEV_ID_57B2 0x035F
86 #define IPR_SUBS_DEV_ID_57C0 0x0352
87 #define IPR_SUBS_DEV_ID_57C3 0x0353
88 #define IPR_SUBS_DEV_ID_57C4 0x0354
89 #define IPR_SUBS_DEV_ID_57C6 0x0357
90 #define IPR_SUBS_DEV_ID_57CC 0x035C
91
92 #define IPR_SUBS_DEV_ID_57B5 0x033C
93 #define IPR_SUBS_DEV_ID_57CE 0x035E
94 #define IPR_SUBS_DEV_ID_57B1 0x0355
95
96 #define IPR_SUBS_DEV_ID_574D 0x0356
97 #define IPR_SUBS_DEV_ID_57C8 0x035D
98
99 #define IPR_SUBS_DEV_ID_57D5 0x03FB
100 #define IPR_SUBS_DEV_ID_57D6 0x03FC
101 #define IPR_SUBS_DEV_ID_57D7 0x03FF
102 #define IPR_SUBS_DEV_ID_57D8 0x03FE
103 #define IPR_SUBS_DEV_ID_57D9 0x046D
104 #define IPR_SUBS_DEV_ID_57DA 0x04CA
105 #define IPR_SUBS_DEV_ID_57EB 0x0474
106 #define IPR_SUBS_DEV_ID_57EC 0x0475
107 #define IPR_SUBS_DEV_ID_57ED 0x0499
108 #define IPR_SUBS_DEV_ID_57EE 0x049A
109 #define IPR_SUBS_DEV_ID_57EF 0x049B
110 #define IPR_SUBS_DEV_ID_57F0 0x049C
111 #define IPR_SUBS_DEV_ID_2CCA 0x04C7
112 #define IPR_SUBS_DEV_ID_2CD2 0x04C8
113 #define IPR_SUBS_DEV_ID_2CCD 0x04C9
114 #define IPR_NAME "ipr"
115
116 /*
117 * Return codes
118 */
119 #define IPR_RC_JOB_CONTINUE 1
120 #define IPR_RC_JOB_RETURN 2
121
122 /*
123 * IOASCs
124 */
125 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
126 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
127 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
128 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
129 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
130 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
131 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
132 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
133 #define IPR_IOASC_HW_CMD_FAILED 0x046E0000
134 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
135 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
136 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
137 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
138 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
139 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
140 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
141
142 #define IPR_FIRST_DRIVER_IOASC 0x10000000
143 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
144 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
145
146 /* Driver data flags */
147 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
148 #define IPR_USE_PCI_WARM_RESET 0x00000002
149
150 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
151 #define IPR_NUM_LOG_HCAMS 2
152 #define IPR_NUM_CFG_CHG_HCAMS 2
153 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
154
155 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
156 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
157
158 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
159 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
160 #define IPR_VSET_BUS 0xff
161 #define IPR_IOA_BUS 0xff
162 #define IPR_IOA_TARGET 0xff
163 #define IPR_IOA_LUN 0xff
164 #define IPR_MAX_NUM_BUSES 16
165
166 #define IPR_NUM_RESET_RELOAD_RETRIES 3
167
168 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
169 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
170 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
171
172 #define IPR_MAX_COMMANDS 100
173 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
174 IPR_NUM_INTERNAL_CMD_BLKS)
175
176 #define IPR_MAX_PHYSICAL_DEVS 192
177 #define IPR_DEFAULT_SIS64_DEVS 1024
178 #define IPR_MAX_SIS64_DEVS 4096
179
180 #define IPR_MAX_SGLIST 64
181 #define IPR_IOA_MAX_SECTORS 32767
182 #define IPR_VSET_MAX_SECTORS 512
183 #define IPR_MAX_CDB_LEN 16
184 #define IPR_MAX_HRRQ_RETRIES 3
185
186 #define IPR_DEFAULT_BUS_WIDTH 16
187 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
188 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
189 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
190 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
191
192 #define IPR_IOA_RES_HANDLE 0xffffffff
193 #define IPR_INVALID_RES_HANDLE 0
194 #define IPR_IOA_RES_ADDR 0x00ffffff
195
196 /*
197 * Adapter Commands
198 */
199 #define IPR_QUERY_RSRC_STATE 0xC2
200 #define IPR_RESET_DEVICE 0xC3
201 #define IPR_RESET_TYPE_SELECT 0x80
202 #define IPR_LUN_RESET 0x40
203 #define IPR_TARGET_RESET 0x20
204 #define IPR_BUS_RESET 0x10
205 #define IPR_ATA_PHY_RESET 0x80
206 #define IPR_ID_HOST_RR_Q 0xC4
207 #define IPR_QUERY_IOA_CONFIG 0xC5
208 #define IPR_CANCEL_ALL_REQUESTS 0xCE
209 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
210 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
211 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
212 #define IPR_SET_SUPPORTED_DEVICES 0xFB
213 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
214 #define IPR_IOA_SHUTDOWN 0xF7
215 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
216
217 /*
218 * Timeouts
219 */
220 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
221 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
222 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
223 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
224 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
225 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
226 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
227 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
228 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
229 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
230 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
231 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
232 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
233 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
234 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
235 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
236 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
237 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
238 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
239 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
240 #define IPR_DUMP_DELAY_SECONDS 4
241 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
242
243 /*
244 * SCSI Literals
245 */
246 #define IPR_VENDOR_ID_LEN 8
247 #define IPR_PROD_ID_LEN 16
248 #define IPR_SERIAL_NUM_LEN 8
249
250 /*
251 * Hardware literals
252 */
253 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
254 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
255 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
256 #define IPR_GET_FMT2_BAR_SEL(mbx) \
257 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
258 #define IPR_SDT_FMT2_BAR0_SEL 0x0
259 #define IPR_SDT_FMT2_BAR1_SEL 0x1
260 #define IPR_SDT_FMT2_BAR2_SEL 0x2
261 #define IPR_SDT_FMT2_BAR3_SEL 0x3
262 #define IPR_SDT_FMT2_BAR4_SEL 0x4
263 #define IPR_SDT_FMT2_BAR5_SEL 0x5
264 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
265 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
266 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
267 #define IPR_DOORBELL 0x82800000
268 #define IPR_RUNTIME_RESET 0x40000000
269
270 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
271 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
272 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
273 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
274 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
275 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
276 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
277
278 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
279 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
280 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
281 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
282 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
283 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
284 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
285 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
286 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
287 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
288 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
289
290 #define IPR_PCII_ERROR_INTERRUPTS \
291 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
292 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
293
294 #define IPR_PCII_OPER_INTERRUPTS \
295 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
296
297 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
298 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
299 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
300
301 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
302 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
303
304 /*
305 * Dump literals
306 */
307 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
308 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
309 #define IPR_FMT2_NUM_SDT_ENTRIES 511
310 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
311 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
312 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
313
314 /*
315 * Misc literals
316 */
317 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
318 #define IPR_MAX_MSIX_VECTORS 0x10
319 #define IPR_MAX_HRRQ_NUM 0x10
320 #define IPR_INIT_HRRQ 0x0
321
322 /*
323 * Adapter interface types
324 */
325
326 struct ipr_res_addr {
327 u8 reserved;
328 u8 bus;
329 u8 target;
330 u8 lun;
331 #define IPR_GET_PHYS_LOC(res_addr) \
332 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
333 }__attribute__((packed, aligned (4)));
334
335 struct ipr_std_inq_vpids {
336 u8 vendor_id[IPR_VENDOR_ID_LEN];
337 u8 product_id[IPR_PROD_ID_LEN];
338 }__attribute__((packed));
339
340 struct ipr_vpd {
341 struct ipr_std_inq_vpids vpids;
342 u8 sn[IPR_SERIAL_NUM_LEN];
343 }__attribute__((packed));
344
345 struct ipr_ext_vpd {
346 struct ipr_vpd vpd;
347 __be32 wwid[2];
348 }__attribute__((packed));
349
350 struct ipr_ext_vpd64 {
351 struct ipr_vpd vpd;
352 __be32 wwid[4];
353 }__attribute__((packed));
354
355 struct ipr_std_inq_data {
356 u8 peri_qual_dev_type;
357 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
358 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
359
360 u8 removeable_medium_rsvd;
361 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
362
363 #define IPR_IS_DASD_DEVICE(std_inq) \
364 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
365 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
366
367 #define IPR_IS_SES_DEVICE(std_inq) \
368 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
369
370 u8 version;
371 u8 aen_naca_fmt;
372 u8 additional_len;
373 u8 sccs_rsvd;
374 u8 bq_enc_multi;
375 u8 sync_cmdq_flags;
376
377 struct ipr_std_inq_vpids vpids;
378
379 u8 ros_rsvd_ram_rsvd[4];
380
381 u8 serial_num[IPR_SERIAL_NUM_LEN];
382 }__attribute__ ((packed));
383
384 #define IPR_RES_TYPE_AF_DASD 0x00
385 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
386 #define IPR_RES_TYPE_VOLUME_SET 0x02
387 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
388 #define IPR_RES_TYPE_GENERIC_ATA 0x04
389 #define IPR_RES_TYPE_ARRAY 0x05
390 #define IPR_RES_TYPE_IOAFP 0xff
391
392 struct ipr_config_table_entry {
393 u8 proto;
394 #define IPR_PROTO_SATA 0x02
395 #define IPR_PROTO_SATA_ATAPI 0x03
396 #define IPR_PROTO_SAS_STP 0x06
397 #define IPR_PROTO_SAS_STP_ATAPI 0x07
398 u8 array_id;
399 u8 flags;
400 #define IPR_IS_IOA_RESOURCE 0x80
401 u8 rsvd_subtype;
402
403 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
404 #define IPR_QUEUE_FROZEN_MODEL 0
405 #define IPR_QUEUE_NACA_MODEL 1
406
407 struct ipr_res_addr res_addr;
408 __be32 res_handle;
409 __be32 lun_wwn[2];
410 struct ipr_std_inq_data std_inq_data;
411 }__attribute__ ((packed, aligned (4)));
412
413 struct ipr_config_table_entry64 {
414 u8 res_type;
415 u8 proto;
416 u8 vset_num;
417 u8 array_id;
418 __be16 flags;
419 __be16 res_flags;
420 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
421 __be32 res_handle;
422 u8 dev_id_type;
423 u8 reserved[3];
424 __be64 dev_id;
425 __be64 lun;
426 __be64 lun_wwn[2];
427 #define IPR_MAX_RES_PATH_LENGTH 48
428 __be64 res_path;
429 struct ipr_std_inq_data std_inq_data;
430 u8 reserved2[4];
431 __be64 reserved3[2];
432 u8 reserved4[8];
433 }__attribute__ ((packed, aligned (8)));
434
435 struct ipr_config_table_hdr {
436 u8 num_entries;
437 u8 flags;
438 #define IPR_UCODE_DOWNLOAD_REQ 0x10
439 __be16 reserved;
440 }__attribute__((packed, aligned (4)));
441
442 struct ipr_config_table_hdr64 {
443 __be16 num_entries;
444 __be16 reserved;
445 u8 flags;
446 u8 reserved2[11];
447 }__attribute__((packed, aligned (4)));
448
449 struct ipr_config_table {
450 struct ipr_config_table_hdr hdr;
451 struct ipr_config_table_entry dev[0];
452 }__attribute__((packed, aligned (4)));
453
454 struct ipr_config_table64 {
455 struct ipr_config_table_hdr64 hdr64;
456 struct ipr_config_table_entry64 dev[0];
457 }__attribute__((packed, aligned (8)));
458
459 struct ipr_config_table_entry_wrapper {
460 union {
461 struct ipr_config_table_entry *cfgte;
462 struct ipr_config_table_entry64 *cfgte64;
463 } u;
464 };
465
466 struct ipr_hostrcb_cfg_ch_not {
467 union {
468 struct ipr_config_table_entry cfgte;
469 struct ipr_config_table_entry64 cfgte64;
470 } u;
471 u8 reserved[936];
472 }__attribute__((packed, aligned (4)));
473
474 struct ipr_supported_device {
475 __be16 data_length;
476 u8 reserved;
477 u8 num_records;
478 struct ipr_std_inq_vpids vpids;
479 u8 reserved2[16];
480 }__attribute__((packed, aligned (4)));
481
482 struct ipr_hrr_queue {
483 struct ipr_ioa_cfg *ioa_cfg;
484 __be32 *host_rrq;
485 dma_addr_t host_rrq_dma;
486 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
487 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
488 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
489 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
490 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
491 volatile __be32 *hrrq_start;
492 volatile __be32 *hrrq_end;
493 volatile __be32 *hrrq_curr;
494
495 struct list_head hrrq_free_q;
496 struct list_head hrrq_pending_q;
497 spinlock_t _lock;
498 spinlock_t *lock;
499
500 volatile u32 toggle_bit;
501 u32 size;
502 u32 min_cmd_id;
503 u32 max_cmd_id;
504 u8 allow_interrupts:1;
505 u8 ioa_is_dead:1;
506 u8 allow_cmds:1;
507 u8 removing_ioa:1;
508
509 struct blk_iopoll iopoll;
510 };
511
512 /* Command packet structure */
513 struct ipr_cmd_pkt {
514 u8 reserved; /* Reserved by IOA */
515 u8 hrrq_id;
516 u8 request_type;
517 #define IPR_RQTYPE_SCSICDB 0x00
518 #define IPR_RQTYPE_IOACMD 0x01
519 #define IPR_RQTYPE_HCAM 0x02
520 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
521
522 u8 reserved2;
523
524 u8 flags_hi;
525 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
526 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
527 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
528 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
529 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
530
531 u8 flags_lo;
532 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
533 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
534 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
535 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
536 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
537 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
538 #define IPR_FLAGS_LO_ACA_TASK 0x08
539
540 u8 cdb[16];
541 __be16 timeout;
542 }__attribute__ ((packed, aligned(4)));
543
544 struct ipr_ioarcb_ata_regs { /* 22 bytes */
545 u8 flags;
546 #define IPR_ATA_FLAG_PACKET_CMD 0x80
547 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
548 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
549 u8 reserved[3];
550
551 __be16 data;
552 u8 feature;
553 u8 nsect;
554 u8 lbal;
555 u8 lbam;
556 u8 lbah;
557 u8 device;
558 u8 command;
559 u8 reserved2[3];
560 u8 hob_feature;
561 u8 hob_nsect;
562 u8 hob_lbal;
563 u8 hob_lbam;
564 u8 hob_lbah;
565 u8 ctl;
566 }__attribute__ ((packed, aligned(2)));
567
568 struct ipr_ioadl_desc {
569 __be32 flags_and_data_len;
570 #define IPR_IOADL_FLAGS_MASK 0xff000000
571 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
572 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
573 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
574 #define IPR_IOADL_FLAGS_READ 0x48000000
575 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
576 #define IPR_IOADL_FLAGS_WRITE 0x68000000
577 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
578 #define IPR_IOADL_FLAGS_LAST 0x01000000
579
580 __be32 address;
581 }__attribute__((packed, aligned (8)));
582
583 struct ipr_ioadl64_desc {
584 __be32 flags;
585 __be32 data_len;
586 __be64 address;
587 }__attribute__((packed, aligned (16)));
588
589 struct ipr_ata64_ioadl {
590 struct ipr_ioarcb_ata_regs regs;
591 u16 reserved[5];
592 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
593 }__attribute__((packed, aligned (16)));
594
595 struct ipr_ioarcb_add_data {
596 union {
597 struct ipr_ioarcb_ata_regs regs;
598 struct ipr_ioadl_desc ioadl[5];
599 __be32 add_cmd_parms[10];
600 } u;
601 }__attribute__ ((packed, aligned (4)));
602
603 struct ipr_ioarcb_sis64_add_addr_ecb {
604 __be64 ioasa_host_pci_addr;
605 __be64 data_ioadl_addr;
606 __be64 reserved;
607 __be32 ext_control_buf[4];
608 }__attribute__((packed, aligned (8)));
609
610 /* IOA Request Control Block 128 bytes */
611 struct ipr_ioarcb {
612 union {
613 __be32 ioarcb_host_pci_addr;
614 __be64 ioarcb_host_pci_addr64;
615 } a;
616 __be32 res_handle;
617 __be32 host_response_handle;
618 __be32 reserved1;
619 __be32 reserved2;
620 __be32 reserved3;
621
622 __be32 data_transfer_length;
623 __be32 read_data_transfer_length;
624 __be32 write_ioadl_addr;
625 __be32 ioadl_len;
626 __be32 read_ioadl_addr;
627 __be32 read_ioadl_len;
628
629 __be32 ioasa_host_pci_addr;
630 __be16 ioasa_len;
631 __be16 reserved4;
632
633 struct ipr_cmd_pkt cmd_pkt;
634
635 __be16 add_cmd_parms_offset;
636 __be16 add_cmd_parms_len;
637
638 union {
639 struct ipr_ioarcb_add_data add_data;
640 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
641 } u;
642
643 }__attribute__((packed, aligned (4)));
644
645 struct ipr_ioasa_vset {
646 __be32 failing_lba_hi;
647 __be32 failing_lba_lo;
648 __be32 reserved;
649 }__attribute__((packed, aligned (4)));
650
651 struct ipr_ioasa_af_dasd {
652 __be32 failing_lba;
653 __be32 reserved[2];
654 }__attribute__((packed, aligned (4)));
655
656 struct ipr_ioasa_gpdd {
657 u8 end_state;
658 u8 bus_phase;
659 __be16 reserved;
660 __be32 ioa_data[2];
661 }__attribute__((packed, aligned (4)));
662
663 struct ipr_ioasa_gata {
664 u8 error;
665 u8 nsect; /* Interrupt reason */
666 u8 lbal;
667 u8 lbam;
668 u8 lbah;
669 u8 device;
670 u8 status;
671 u8 alt_status; /* ATA CTL */
672 u8 hob_nsect;
673 u8 hob_lbal;
674 u8 hob_lbam;
675 u8 hob_lbah;
676 }__attribute__((packed, aligned (4)));
677
678 struct ipr_auto_sense {
679 __be16 auto_sense_len;
680 __be16 ioa_data_len;
681 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
682 };
683
684 struct ipr_ioasa_hdr {
685 __be32 ioasc;
686 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
687 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
688 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
689 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
690
691 __be16 ret_stat_len; /* Length of the returned IOASA */
692
693 __be16 avail_stat_len; /* Total Length of status available. */
694
695 __be32 residual_data_len; /* number of bytes in the host data */
696 /* buffers that were not used by the IOARCB command. */
697
698 __be32 ilid;
699 #define IPR_NO_ILID 0
700 #define IPR_DRIVER_ILID 0xffffffff
701
702 __be32 fd_ioasc;
703
704 __be32 fd_phys_locator;
705
706 __be32 fd_res_handle;
707
708 __be32 ioasc_specific; /* status code specific field */
709 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
710 #define IPR_AUTOSENSE_VALID 0x40000000
711 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
712 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
713 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
714 #define IPR_FIELD_POINTER_MASK 0x0000ffff
715
716 }__attribute__((packed, aligned (4)));
717
718 struct ipr_ioasa {
719 struct ipr_ioasa_hdr hdr;
720
721 union {
722 struct ipr_ioasa_vset vset;
723 struct ipr_ioasa_af_dasd dasd;
724 struct ipr_ioasa_gpdd gpdd;
725 struct ipr_ioasa_gata gata;
726 } u;
727
728 struct ipr_auto_sense auto_sense;
729 }__attribute__((packed, aligned (4)));
730
731 struct ipr_ioasa64 {
732 struct ipr_ioasa_hdr hdr;
733 u8 fd_res_path[8];
734
735 union {
736 struct ipr_ioasa_vset vset;
737 struct ipr_ioasa_af_dasd dasd;
738 struct ipr_ioasa_gpdd gpdd;
739 struct ipr_ioasa_gata gata;
740 } u;
741
742 struct ipr_auto_sense auto_sense;
743 }__attribute__((packed, aligned (4)));
744
745 struct ipr_mode_parm_hdr {
746 u8 length;
747 u8 medium_type;
748 u8 device_spec_parms;
749 u8 block_desc_len;
750 }__attribute__((packed));
751
752 struct ipr_mode_pages {
753 struct ipr_mode_parm_hdr hdr;
754 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
755 }__attribute__((packed));
756
757 struct ipr_mode_page_hdr {
758 u8 ps_page_code;
759 #define IPR_MODE_PAGE_PS 0x80
760 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
761 u8 page_length;
762 }__attribute__ ((packed));
763
764 struct ipr_dev_bus_entry {
765 struct ipr_res_addr res_addr;
766 u8 flags;
767 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
768 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
769 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
770 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
771 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
772 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
773 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
774
775 u8 scsi_id;
776 u8 bus_width;
777 u8 extended_reset_delay;
778 #define IPR_EXTENDED_RESET_DELAY 7
779
780 __be32 max_xfer_rate;
781
782 u8 spinup_delay;
783 u8 reserved3;
784 __be16 reserved4;
785 }__attribute__((packed, aligned (4)));
786
787 struct ipr_mode_page28 {
788 struct ipr_mode_page_hdr hdr;
789 u8 num_entries;
790 u8 entry_length;
791 struct ipr_dev_bus_entry bus[0];
792 }__attribute__((packed));
793
794 struct ipr_mode_page24 {
795 struct ipr_mode_page_hdr hdr;
796 u8 flags;
797 #define IPR_ENABLE_DUAL_IOA_AF 0x80
798 }__attribute__((packed));
799
800 struct ipr_ioa_vpd {
801 struct ipr_std_inq_data std_inq_data;
802 u8 ascii_part_num[12];
803 u8 reserved[40];
804 u8 ascii_plant_code[4];
805 }__attribute__((packed));
806
807 struct ipr_inquiry_page3 {
808 u8 peri_qual_dev_type;
809 u8 page_code;
810 u8 reserved1;
811 u8 page_length;
812 u8 ascii_len;
813 u8 reserved2[3];
814 u8 load_id[4];
815 u8 major_release;
816 u8 card_type;
817 u8 minor_release[2];
818 u8 ptf_number[4];
819 u8 patch_number[4];
820 }__attribute__((packed));
821
822 struct ipr_inquiry_cap {
823 u8 peri_qual_dev_type;
824 u8 page_code;
825 u8 reserved1;
826 u8 page_length;
827 u8 ascii_len;
828 u8 reserved2;
829 u8 sis_version[2];
830 u8 cap;
831 #define IPR_CAP_DUAL_IOA_RAID 0x80
832 u8 reserved3[15];
833 }__attribute__((packed));
834
835 #define IPR_INQUIRY_PAGE0_ENTRIES 20
836 struct ipr_inquiry_page0 {
837 u8 peri_qual_dev_type;
838 u8 page_code;
839 u8 reserved1;
840 u8 len;
841 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
842 }__attribute__((packed));
843
844 struct ipr_hostrcb_device_data_entry {
845 struct ipr_vpd vpd;
846 struct ipr_res_addr dev_res_addr;
847 struct ipr_vpd new_vpd;
848 struct ipr_vpd ioa_last_with_dev_vpd;
849 struct ipr_vpd cfc_last_with_dev_vpd;
850 __be32 ioa_data[5];
851 }__attribute__((packed, aligned (4)));
852
853 struct ipr_hostrcb_device_data_entry_enhanced {
854 struct ipr_ext_vpd vpd;
855 u8 ccin[4];
856 struct ipr_res_addr dev_res_addr;
857 struct ipr_ext_vpd new_vpd;
858 u8 new_ccin[4];
859 struct ipr_ext_vpd ioa_last_with_dev_vpd;
860 struct ipr_ext_vpd cfc_last_with_dev_vpd;
861 }__attribute__((packed, aligned (4)));
862
863 struct ipr_hostrcb64_device_data_entry_enhanced {
864 struct ipr_ext_vpd vpd;
865 u8 ccin[4];
866 u8 res_path[8];
867 struct ipr_ext_vpd new_vpd;
868 u8 new_ccin[4];
869 struct ipr_ext_vpd ioa_last_with_dev_vpd;
870 struct ipr_ext_vpd cfc_last_with_dev_vpd;
871 }__attribute__((packed, aligned (4)));
872
873 struct ipr_hostrcb_array_data_entry {
874 struct ipr_vpd vpd;
875 struct ipr_res_addr expected_dev_res_addr;
876 struct ipr_res_addr dev_res_addr;
877 }__attribute__((packed, aligned (4)));
878
879 struct ipr_hostrcb64_array_data_entry {
880 struct ipr_ext_vpd vpd;
881 u8 ccin[4];
882 u8 expected_res_path[8];
883 u8 res_path[8];
884 }__attribute__((packed, aligned (4)));
885
886 struct ipr_hostrcb_array_data_entry_enhanced {
887 struct ipr_ext_vpd vpd;
888 u8 ccin[4];
889 struct ipr_res_addr expected_dev_res_addr;
890 struct ipr_res_addr dev_res_addr;
891 }__attribute__((packed, aligned (4)));
892
893 struct ipr_hostrcb_type_ff_error {
894 __be32 ioa_data[758];
895 }__attribute__((packed, aligned (4)));
896
897 struct ipr_hostrcb_type_01_error {
898 __be32 seek_counter;
899 __be32 read_counter;
900 u8 sense_data[32];
901 __be32 ioa_data[236];
902 }__attribute__((packed, aligned (4)));
903
904 struct ipr_hostrcb_type_21_error {
905 __be32 wwn[4];
906 u8 res_path[8];
907 u8 primary_problem_desc[32];
908 u8 second_problem_desc[32];
909 __be32 sense_data[8];
910 __be32 cdb[4];
911 __be32 residual_trans_length;
912 __be32 length_of_error;
913 __be32 ioa_data[236];
914 }__attribute__((packed, aligned (4)));
915
916 struct ipr_hostrcb_type_02_error {
917 struct ipr_vpd ioa_vpd;
918 struct ipr_vpd cfc_vpd;
919 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
920 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
921 __be32 ioa_data[3];
922 }__attribute__((packed, aligned (4)));
923
924 struct ipr_hostrcb_type_12_error {
925 struct ipr_ext_vpd ioa_vpd;
926 struct ipr_ext_vpd cfc_vpd;
927 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
928 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
929 __be32 ioa_data[3];
930 }__attribute__((packed, aligned (4)));
931
932 struct ipr_hostrcb_type_03_error {
933 struct ipr_vpd ioa_vpd;
934 struct ipr_vpd cfc_vpd;
935 __be32 errors_detected;
936 __be32 errors_logged;
937 u8 ioa_data[12];
938 struct ipr_hostrcb_device_data_entry dev[3];
939 }__attribute__((packed, aligned (4)));
940
941 struct ipr_hostrcb_type_13_error {
942 struct ipr_ext_vpd ioa_vpd;
943 struct ipr_ext_vpd cfc_vpd;
944 __be32 errors_detected;
945 __be32 errors_logged;
946 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
947 }__attribute__((packed, aligned (4)));
948
949 struct ipr_hostrcb_type_23_error {
950 struct ipr_ext_vpd ioa_vpd;
951 struct ipr_ext_vpd cfc_vpd;
952 __be32 errors_detected;
953 __be32 errors_logged;
954 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
955 }__attribute__((packed, aligned (4)));
956
957 struct ipr_hostrcb_type_04_error {
958 struct ipr_vpd ioa_vpd;
959 struct ipr_vpd cfc_vpd;
960 u8 ioa_data[12];
961 struct ipr_hostrcb_array_data_entry array_member[10];
962 __be32 exposed_mode_adn;
963 __be32 array_id;
964 struct ipr_vpd incomp_dev_vpd;
965 __be32 ioa_data2;
966 struct ipr_hostrcb_array_data_entry array_member2[8];
967 struct ipr_res_addr last_func_vset_res_addr;
968 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
969 u8 protection_level[8];
970 }__attribute__((packed, aligned (4)));
971
972 struct ipr_hostrcb_type_14_error {
973 struct ipr_ext_vpd ioa_vpd;
974 struct ipr_ext_vpd cfc_vpd;
975 __be32 exposed_mode_adn;
976 __be32 array_id;
977 struct ipr_res_addr last_func_vset_res_addr;
978 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
979 u8 protection_level[8];
980 __be32 num_entries;
981 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
982 }__attribute__((packed, aligned (4)));
983
984 struct ipr_hostrcb_type_24_error {
985 struct ipr_ext_vpd ioa_vpd;
986 struct ipr_ext_vpd cfc_vpd;
987 u8 reserved[2];
988 u8 exposed_mode_adn;
989 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
990 u8 array_id;
991 u8 last_res_path[8];
992 u8 protection_level[8];
993 struct ipr_ext_vpd64 array_vpd;
994 u8 description[16];
995 u8 reserved2[3];
996 u8 num_entries;
997 struct ipr_hostrcb64_array_data_entry array_member[32];
998 }__attribute__((packed, aligned (4)));
999
1000 struct ipr_hostrcb_type_07_error {
1001 u8 failure_reason[64];
1002 struct ipr_vpd vpd;
1003 u32 data[222];
1004 }__attribute__((packed, aligned (4)));
1005
1006 struct ipr_hostrcb_type_17_error {
1007 u8 failure_reason[64];
1008 struct ipr_ext_vpd vpd;
1009 u32 data[476];
1010 }__attribute__((packed, aligned (4)));
1011
1012 struct ipr_hostrcb_config_element {
1013 u8 type_status;
1014 #define IPR_PATH_CFG_TYPE_MASK 0xF0
1015 #define IPR_PATH_CFG_NOT_EXIST 0x00
1016 #define IPR_PATH_CFG_IOA_PORT 0x10
1017 #define IPR_PATH_CFG_EXP_PORT 0x20
1018 #define IPR_PATH_CFG_DEVICE_PORT 0x30
1019 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1020
1021 #define IPR_PATH_CFG_STATUS_MASK 0x0F
1022 #define IPR_PATH_CFG_NO_PROB 0x00
1023 #define IPR_PATH_CFG_DEGRADED 0x01
1024 #define IPR_PATH_CFG_FAILED 0x02
1025 #define IPR_PATH_CFG_SUSPECT 0x03
1026 #define IPR_PATH_NOT_DETECTED 0x04
1027 #define IPR_PATH_INCORRECT_CONN 0x05
1028
1029 u8 cascaded_expander;
1030 u8 phy;
1031 u8 link_rate;
1032 #define IPR_PHY_LINK_RATE_MASK 0x0F
1033
1034 __be32 wwid[2];
1035 }__attribute__((packed, aligned (4)));
1036
1037 struct ipr_hostrcb64_config_element {
1038 __be16 length;
1039 u8 descriptor_id;
1040 #define IPR_DESCRIPTOR_MASK 0xC0
1041 #define IPR_DESCRIPTOR_SIS64 0x00
1042
1043 u8 reserved;
1044 u8 type_status;
1045
1046 u8 reserved2[2];
1047 u8 link_rate;
1048
1049 u8 res_path[8];
1050 __be32 wwid[2];
1051 }__attribute__((packed, aligned (8)));
1052
1053 struct ipr_hostrcb_fabric_desc {
1054 __be16 length;
1055 u8 ioa_port;
1056 u8 cascaded_expander;
1057 u8 phy;
1058 u8 path_state;
1059 #define IPR_PATH_ACTIVE_MASK 0xC0
1060 #define IPR_PATH_NO_INFO 0x00
1061 #define IPR_PATH_ACTIVE 0x40
1062 #define IPR_PATH_NOT_ACTIVE 0x80
1063
1064 #define IPR_PATH_STATE_MASK 0x0F
1065 #define IPR_PATH_STATE_NO_INFO 0x00
1066 #define IPR_PATH_HEALTHY 0x01
1067 #define IPR_PATH_DEGRADED 0x02
1068 #define IPR_PATH_FAILED 0x03
1069
1070 __be16 num_entries;
1071 struct ipr_hostrcb_config_element elem[1];
1072 }__attribute__((packed, aligned (4)));
1073
1074 struct ipr_hostrcb64_fabric_desc {
1075 __be16 length;
1076 u8 descriptor_id;
1077
1078 u8 reserved[2];
1079 u8 path_state;
1080
1081 u8 reserved2[2];
1082 u8 res_path[8];
1083 u8 reserved3[6];
1084 __be16 num_entries;
1085 struct ipr_hostrcb64_config_element elem[1];
1086 }__attribute__((packed, aligned (8)));
1087
1088 #define for_each_hrrq(hrrq, ioa_cfg) \
1089 for (hrrq = (ioa_cfg)->hrrq; \
1090 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1091
1092 #define for_each_fabric_cfg(fabric, cfg) \
1093 for (cfg = (fabric)->elem; \
1094 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1095 cfg++)
1096
1097 struct ipr_hostrcb_type_20_error {
1098 u8 failure_reason[64];
1099 u8 reserved[3];
1100 u8 num_entries;
1101 struct ipr_hostrcb_fabric_desc desc[1];
1102 }__attribute__((packed, aligned (4)));
1103
1104 struct ipr_hostrcb_type_30_error {
1105 u8 failure_reason[64];
1106 u8 reserved[3];
1107 u8 num_entries;
1108 struct ipr_hostrcb64_fabric_desc desc[1];
1109 }__attribute__((packed, aligned (4)));
1110
1111 struct ipr_hostrcb_error {
1112 __be32 fd_ioasc;
1113 struct ipr_res_addr fd_res_addr;
1114 __be32 fd_res_handle;
1115 __be32 prc;
1116 union {
1117 struct ipr_hostrcb_type_ff_error type_ff_error;
1118 struct ipr_hostrcb_type_01_error type_01_error;
1119 struct ipr_hostrcb_type_02_error type_02_error;
1120 struct ipr_hostrcb_type_03_error type_03_error;
1121 struct ipr_hostrcb_type_04_error type_04_error;
1122 struct ipr_hostrcb_type_07_error type_07_error;
1123 struct ipr_hostrcb_type_12_error type_12_error;
1124 struct ipr_hostrcb_type_13_error type_13_error;
1125 struct ipr_hostrcb_type_14_error type_14_error;
1126 struct ipr_hostrcb_type_17_error type_17_error;
1127 struct ipr_hostrcb_type_20_error type_20_error;
1128 } u;
1129 }__attribute__((packed, aligned (4)));
1130
1131 struct ipr_hostrcb64_error {
1132 __be32 fd_ioasc;
1133 __be32 ioa_fw_level;
1134 __be32 fd_res_handle;
1135 __be32 prc;
1136 __be64 fd_dev_id;
1137 __be64 fd_lun;
1138 u8 fd_res_path[8];
1139 __be64 time_stamp;
1140 u8 reserved[16];
1141 union {
1142 struct ipr_hostrcb_type_ff_error type_ff_error;
1143 struct ipr_hostrcb_type_12_error type_12_error;
1144 struct ipr_hostrcb_type_17_error type_17_error;
1145 struct ipr_hostrcb_type_21_error type_21_error;
1146 struct ipr_hostrcb_type_23_error type_23_error;
1147 struct ipr_hostrcb_type_24_error type_24_error;
1148 struct ipr_hostrcb_type_30_error type_30_error;
1149 } u;
1150 }__attribute__((packed, aligned (8)));
1151
1152 struct ipr_hostrcb_raw {
1153 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1154 }__attribute__((packed, aligned (4)));
1155
1156 struct ipr_hcam {
1157 u8 op_code;
1158 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1159 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1160
1161 u8 notify_type;
1162 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1163 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1164 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1165 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1166 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1167
1168 u8 notifications_lost;
1169 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1170 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1171
1172 u8 flags;
1173 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1174 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1175
1176 u8 overlay_id;
1177 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1178 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1179 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1180 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1181 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1182 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1183 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1184 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1185 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1186 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1187 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1188 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1189 #define IPR_HOST_RCB_OVERLAY_ID_21 0x21
1190 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1191 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1192 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1193 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1194 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1195
1196 u8 reserved1[3];
1197 __be32 ilid;
1198 __be32 time_since_last_ioa_reset;
1199 __be32 reserved2;
1200 __be32 length;
1201
1202 union {
1203 struct ipr_hostrcb_error error;
1204 struct ipr_hostrcb64_error error64;
1205 struct ipr_hostrcb_cfg_ch_not ccn;
1206 struct ipr_hostrcb_raw raw;
1207 } u;
1208 }__attribute__((packed, aligned (4)));
1209
1210 struct ipr_hostrcb {
1211 struct ipr_hcam hcam;
1212 dma_addr_t hostrcb_dma;
1213 struct list_head queue;
1214 struct ipr_ioa_cfg *ioa_cfg;
1215 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1216 };
1217
1218 /* IPR smart dump table structures */
1219 struct ipr_sdt_entry {
1220 __be32 start_token;
1221 __be32 end_token;
1222 u8 reserved[4];
1223
1224 u8 flags;
1225 #define IPR_SDT_ENDIAN 0x80
1226 #define IPR_SDT_VALID_ENTRY 0x20
1227
1228 u8 resv;
1229 __be16 priority;
1230 }__attribute__((packed, aligned (4)));
1231
1232 struct ipr_sdt_header {
1233 __be32 state;
1234 __be32 num_entries;
1235 __be32 num_entries_used;
1236 __be32 dump_size;
1237 }__attribute__((packed, aligned (4)));
1238
1239 struct ipr_sdt {
1240 struct ipr_sdt_header hdr;
1241 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1242 }__attribute__((packed, aligned (4)));
1243
1244 struct ipr_uc_sdt {
1245 struct ipr_sdt_header hdr;
1246 struct ipr_sdt_entry entry[1];
1247 }__attribute__((packed, aligned (4)));
1248
1249 /*
1250 * Driver types
1251 */
1252 struct ipr_bus_attributes {
1253 u8 bus;
1254 u8 qas_enabled;
1255 u8 bus_width;
1256 u8 reserved;
1257 u32 max_xfer_rate;
1258 };
1259
1260 struct ipr_sata_port {
1261 struct ipr_ioa_cfg *ioa_cfg;
1262 struct ata_port *ap;
1263 struct ipr_resource_entry *res;
1264 struct ipr_ioasa_gata ioasa;
1265 };
1266
1267 struct ipr_resource_entry {
1268 u8 needs_sync_complete:1;
1269 u8 in_erp:1;
1270 u8 add_to_ml:1;
1271 u8 del_from_ml:1;
1272 u8 resetting_device:1;
1273 u8 reset_occurred:1;
1274
1275 u32 bus; /* AKA channel */
1276 u32 target; /* AKA id */
1277 u32 lun;
1278 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1279 #define IPR_VSET_VIRTUAL_BUS 0x2
1280 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1281
1282 #define IPR_GET_RES_PHYS_LOC(res) \
1283 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1284
1285 u8 ata_class;
1286
1287 u8 flags;
1288 __be16 res_flags;
1289
1290 u8 type;
1291
1292 u8 qmodel;
1293 struct ipr_std_inq_data std_inq_data;
1294
1295 __be32 res_handle;
1296 __be64 dev_id;
1297 __be64 lun_wwn;
1298 struct scsi_lun dev_lun;
1299 u8 res_path[8];
1300
1301 struct ipr_ioa_cfg *ioa_cfg;
1302 struct scsi_device *sdev;
1303 struct ipr_sata_port *sata_port;
1304 struct list_head queue;
1305 }; /* struct ipr_resource_entry */
1306
1307 struct ipr_resource_hdr {
1308 u16 num_entries;
1309 u16 reserved;
1310 };
1311
1312 struct ipr_misc_cbs {
1313 struct ipr_ioa_vpd ioa_vpd;
1314 struct ipr_inquiry_page0 page0_data;
1315 struct ipr_inquiry_page3 page3_data;
1316 struct ipr_inquiry_cap cap;
1317 struct ipr_mode_pages mode_pages;
1318 struct ipr_supported_device supp_dev;
1319 };
1320
1321 struct ipr_interrupt_offsets {
1322 unsigned long set_interrupt_mask_reg;
1323 unsigned long clr_interrupt_mask_reg;
1324 unsigned long clr_interrupt_mask_reg32;
1325 unsigned long sense_interrupt_mask_reg;
1326 unsigned long sense_interrupt_mask_reg32;
1327 unsigned long clr_interrupt_reg;
1328 unsigned long clr_interrupt_reg32;
1329
1330 unsigned long sense_interrupt_reg;
1331 unsigned long sense_interrupt_reg32;
1332 unsigned long ioarrin_reg;
1333 unsigned long sense_uproc_interrupt_reg;
1334 unsigned long sense_uproc_interrupt_reg32;
1335 unsigned long set_uproc_interrupt_reg;
1336 unsigned long set_uproc_interrupt_reg32;
1337 unsigned long clr_uproc_interrupt_reg;
1338 unsigned long clr_uproc_interrupt_reg32;
1339
1340 unsigned long init_feedback_reg;
1341
1342 unsigned long dump_addr_reg;
1343 unsigned long dump_data_reg;
1344
1345 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1346 unsigned long endian_swap_reg;
1347 };
1348
1349 struct ipr_interrupts {
1350 void __iomem *set_interrupt_mask_reg;
1351 void __iomem *clr_interrupt_mask_reg;
1352 void __iomem *clr_interrupt_mask_reg32;
1353 void __iomem *sense_interrupt_mask_reg;
1354 void __iomem *sense_interrupt_mask_reg32;
1355 void __iomem *clr_interrupt_reg;
1356 void __iomem *clr_interrupt_reg32;
1357
1358 void __iomem *sense_interrupt_reg;
1359 void __iomem *sense_interrupt_reg32;
1360 void __iomem *ioarrin_reg;
1361 void __iomem *sense_uproc_interrupt_reg;
1362 void __iomem *sense_uproc_interrupt_reg32;
1363 void __iomem *set_uproc_interrupt_reg;
1364 void __iomem *set_uproc_interrupt_reg32;
1365 void __iomem *clr_uproc_interrupt_reg;
1366 void __iomem *clr_uproc_interrupt_reg32;
1367
1368 void __iomem *init_feedback_reg;
1369
1370 void __iomem *dump_addr_reg;
1371 void __iomem *dump_data_reg;
1372
1373 void __iomem *endian_swap_reg;
1374 };
1375
1376 struct ipr_chip_cfg_t {
1377 u32 mailbox;
1378 u16 max_cmds;
1379 u8 cache_line_size;
1380 u8 clear_isr;
1381 u32 iopoll_weight;
1382 struct ipr_interrupt_offsets regs;
1383 };
1384
1385 struct ipr_chip_t {
1386 u16 vendor;
1387 u16 device;
1388 u16 intr_type;
1389 #define IPR_USE_LSI 0x00
1390 #define IPR_USE_MSI 0x01
1391 #define IPR_USE_MSIX 0x02
1392 u16 sis_type;
1393 #define IPR_SIS32 0x00
1394 #define IPR_SIS64 0x01
1395 u16 bist_method;
1396 #define IPR_PCI_CFG 0x00
1397 #define IPR_MMIO 0x01
1398 const struct ipr_chip_cfg_t *cfg;
1399 };
1400
1401 enum ipr_shutdown_type {
1402 IPR_SHUTDOWN_NORMAL = 0x00,
1403 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1404 IPR_SHUTDOWN_ABBREV = 0x80,
1405 IPR_SHUTDOWN_NONE = 0x100
1406 };
1407
1408 struct ipr_trace_entry {
1409 u32 time;
1410
1411 u8 op_code;
1412 u8 ata_op_code;
1413 u8 type;
1414 #define IPR_TRACE_START 0x00
1415 #define IPR_TRACE_FINISH 0xff
1416 u8 cmd_index;
1417
1418 __be32 res_handle;
1419 union {
1420 u32 ioasc;
1421 u32 add_data;
1422 u32 res_addr;
1423 } u;
1424 };
1425
1426 struct ipr_sglist {
1427 u32 order;
1428 u32 num_sg;
1429 u32 num_dma_sg;
1430 u32 buffer_len;
1431 struct scatterlist scatterlist[1];
1432 };
1433
1434 enum ipr_sdt_state {
1435 INACTIVE,
1436 WAIT_FOR_DUMP,
1437 GET_DUMP,
1438 READ_DUMP,
1439 ABORT_DUMP,
1440 DUMP_OBTAINED
1441 };
1442
1443 /* Per-controller data */
1444 struct ipr_ioa_cfg {
1445 char eye_catcher[8];
1446 #define IPR_EYECATCHER "iprcfg"
1447
1448 struct list_head queue;
1449
1450 u8 in_reset_reload:1;
1451 u8 in_ioa_bringdown:1;
1452 u8 ioa_unit_checked:1;
1453 u8 dump_taken:1;
1454 u8 scan_done:1;
1455 u8 needs_hard_reset:1;
1456 u8 dual_raid:1;
1457 u8 needs_warm_reset:1;
1458 u8 msi_received:1;
1459 u8 sis64:1;
1460 u8 dump_timeout:1;
1461 u8 cfg_locked:1;
1462 u8 clear_isr:1;
1463 u8 probe_done:1;
1464
1465 u8 revid;
1466
1467 /*
1468 * Bitmaps for SIS64 generated target values
1469 */
1470 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1471 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1472 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1473
1474 u16 type; /* CCIN of the card */
1475
1476 u8 log_level;
1477 #define IPR_MAX_LOG_LEVEL 4
1478 #define IPR_DEFAULT_LOG_LEVEL 2
1479
1480 #define IPR_NUM_TRACE_INDEX_BITS 8
1481 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1482 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1483 char trace_start[8];
1484 #define IPR_TRACE_START_LABEL "trace"
1485 struct ipr_trace_entry *trace;
1486 atomic_t trace_index;
1487
1488 char cfg_table_start[8];
1489 #define IPR_CFG_TBL_START "cfg"
1490 union {
1491 struct ipr_config_table *cfg_table;
1492 struct ipr_config_table64 *cfg_table64;
1493 } u;
1494 dma_addr_t cfg_table_dma;
1495 u32 cfg_table_size;
1496 u32 max_devs_supported;
1497
1498 char resource_table_label[8];
1499 #define IPR_RES_TABLE_LABEL "res_tbl"
1500 struct ipr_resource_entry *res_entries;
1501 struct list_head free_res_q;
1502 struct list_head used_res_q;
1503
1504 char ipr_hcam_label[8];
1505 #define IPR_HCAM_LABEL "hcams"
1506 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1507 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1508 struct list_head hostrcb_free_q;
1509 struct list_head hostrcb_pending_q;
1510
1511 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1512 u32 hrrq_num;
1513 atomic_t hrrq_index;
1514 u16 identify_hrrq_index;
1515
1516 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1517
1518 unsigned int transop_timeout;
1519 const struct ipr_chip_cfg_t *chip_cfg;
1520 const struct ipr_chip_t *ipr_chip;
1521
1522 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1523 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1524 void __iomem *ioa_mailbox;
1525 struct ipr_interrupts regs;
1526
1527 u16 saved_pcix_cmd_reg;
1528 u16 reset_retries;
1529
1530 u32 errors_logged;
1531 u32 doorbell;
1532
1533 struct Scsi_Host *host;
1534 struct pci_dev *pdev;
1535 struct ipr_sglist *ucode_sglist;
1536 u8 saved_mode_page_len;
1537
1538 struct work_struct work_q;
1539
1540 wait_queue_head_t reset_wait_q;
1541 wait_queue_head_t msi_wait_q;
1542 wait_queue_head_t eeh_wait_q;
1543
1544 struct ipr_dump *dump;
1545 enum ipr_sdt_state sdt_state;
1546
1547 struct ipr_misc_cbs *vpd_cbs;
1548 dma_addr_t vpd_cbs_dma;
1549
1550 struct dma_pool *ipr_cmd_pool;
1551
1552 struct ipr_cmnd *reset_cmd;
1553 int (*reset) (struct ipr_cmnd *);
1554
1555 struct ata_host ata_host;
1556 char ipr_cmd_label[8];
1557 #define IPR_CMD_LABEL "ipr_cmd"
1558 u32 max_cmds;
1559 struct ipr_cmnd **ipr_cmnd_list;
1560 dma_addr_t *ipr_cmnd_list_dma;
1561
1562 u16 intr_flag;
1563 unsigned int nvectors;
1564
1565 struct {
1566 unsigned short vec;
1567 char desc[22];
1568 } vectors_info[IPR_MAX_MSIX_VECTORS];
1569
1570 u32 iopoll_weight;
1571
1572 }; /* struct ipr_ioa_cfg */
1573
1574 struct ipr_cmnd {
1575 struct ipr_ioarcb ioarcb;
1576 union {
1577 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1578 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1579 struct ipr_ata64_ioadl ata_ioadl;
1580 } i;
1581 union {
1582 struct ipr_ioasa ioasa;
1583 struct ipr_ioasa64 ioasa64;
1584 } s;
1585 struct list_head queue;
1586 struct scsi_cmnd *scsi_cmd;
1587 struct ata_queued_cmd *qc;
1588 struct completion completion;
1589 struct timer_list timer;
1590 void (*fast_done) (struct ipr_cmnd *);
1591 void (*done) (struct ipr_cmnd *);
1592 int (*job_step) (struct ipr_cmnd *);
1593 int (*job_step_failed) (struct ipr_cmnd *);
1594 u16 cmd_index;
1595 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1596 dma_addr_t sense_buffer_dma;
1597 unsigned short dma_use_sg;
1598 dma_addr_t dma_addr;
1599 struct ipr_cmnd *sibling;
1600 union {
1601 enum ipr_shutdown_type shutdown_type;
1602 struct ipr_hostrcb *hostrcb;
1603 unsigned long time_left;
1604 unsigned long scratch;
1605 struct ipr_resource_entry *res;
1606 struct scsi_device *sdev;
1607 } u;
1608
1609 struct completion *eh_comp;
1610 struct ipr_hrr_queue *hrrq;
1611 struct ipr_ioa_cfg *ioa_cfg;
1612 };
1613
1614 struct ipr_ses_table_entry {
1615 char product_id[17];
1616 char compare_product_id_byte[17];
1617 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1618 };
1619
1620 struct ipr_dump_header {
1621 u32 eye_catcher;
1622 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1623 u32 len;
1624 u32 num_entries;
1625 u32 first_entry_offset;
1626 u32 status;
1627 #define IPR_DUMP_STATUS_SUCCESS 0
1628 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1629 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1630 u32 os;
1631 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1632 u32 driver_name;
1633 #define IPR_DUMP_DRIVER_NAME 0x49505232
1634 }__attribute__((packed, aligned (4)));
1635
1636 struct ipr_dump_entry_header {
1637 u32 eye_catcher;
1638 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1639 u32 len;
1640 u32 num_elems;
1641 u32 offset;
1642 u32 data_type;
1643 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1644 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1645 u32 id;
1646 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1647 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1648 #define IPR_DUMP_TRACE_ID 0x54524143
1649 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1650 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1651 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1652 #define IPR_DUMP_PEND_OPS 0x414F5053
1653 u32 status;
1654 }__attribute__((packed, aligned (4)));
1655
1656 struct ipr_dump_location_entry {
1657 struct ipr_dump_entry_header hdr;
1658 u8 location[20];
1659 }__attribute__((packed));
1660
1661 struct ipr_dump_trace_entry {
1662 struct ipr_dump_entry_header hdr;
1663 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1664 }__attribute__((packed, aligned (4)));
1665
1666 struct ipr_dump_version_entry {
1667 struct ipr_dump_entry_header hdr;
1668 u8 version[sizeof(IPR_DRIVER_VERSION)];
1669 };
1670
1671 struct ipr_dump_ioa_type_entry {
1672 struct ipr_dump_entry_header hdr;
1673 u32 type;
1674 u32 fw_version;
1675 };
1676
1677 struct ipr_driver_dump {
1678 struct ipr_dump_header hdr;
1679 struct ipr_dump_version_entry version_entry;
1680 struct ipr_dump_location_entry location_entry;
1681 struct ipr_dump_ioa_type_entry ioa_type_entry;
1682 struct ipr_dump_trace_entry trace_entry;
1683 }__attribute__((packed));
1684
1685 struct ipr_ioa_dump {
1686 struct ipr_dump_entry_header hdr;
1687 struct ipr_sdt sdt;
1688 __be32 **ioa_data;
1689 u32 reserved;
1690 u32 next_page_index;
1691 u32 page_offset;
1692 u32 format;
1693 }__attribute__((packed, aligned (4)));
1694
1695 struct ipr_dump {
1696 struct kref kref;
1697 struct ipr_ioa_cfg *ioa_cfg;
1698 struct ipr_driver_dump driver_dump;
1699 struct ipr_ioa_dump ioa_dump;
1700 };
1701
1702 struct ipr_error_table_t {
1703 u32 ioasc;
1704 int log_ioasa;
1705 int log_hcam;
1706 char *error;
1707 };
1708
1709 struct ipr_software_inq_lid_info {
1710 __be32 load_id;
1711 __be32 timestamp[3];
1712 }__attribute__((packed, aligned (4)));
1713
1714 struct ipr_ucode_image_header {
1715 __be32 header_length;
1716 __be32 lid_table_offset;
1717 u8 major_release;
1718 u8 card_type;
1719 u8 minor_release[2];
1720 u8 reserved[20];
1721 char eyecatcher[16];
1722 __be32 num_lids;
1723 struct ipr_software_inq_lid_info lid[1];
1724 }__attribute__((packed, aligned (4)));
1725
1726 /*
1727 * Macros
1728 */
1729 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1730
1731 #ifdef CONFIG_SCSI_IPR_TRACE
1732 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1733 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1734 #else
1735 #define ipr_create_trace_file(kobj, attr) 0
1736 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1737 #endif
1738
1739 #ifdef CONFIG_SCSI_IPR_DUMP
1740 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1741 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1742 #else
1743 #define ipr_create_dump_file(kobj, attr) 0
1744 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1745 #endif
1746
1747 /*
1748 * Error logging macros
1749 */
1750 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1751 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1752 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1753
1754 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1755 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1756 bus, target, lun, ##__VA_ARGS__)
1757
1758 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1759 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1760
1761 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1762 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1763 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1764
1765 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1766 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1767
1768 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1769 { \
1770 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1771 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1772 } else { \
1773 ipr_err(fmt": %d:%d:%d:%d\n", \
1774 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1775 (res).bus, (res).target, (res).lun); \
1776 } \
1777 }
1778
1779 #define ipr_hcam_err(hostrcb, fmt, ...) \
1780 { \
1781 if (ipr_is_device(hostrcb)) { \
1782 if ((hostrcb)->ioa_cfg->sis64) { \
1783 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1784 ipr_format_res_path(hostrcb->ioa_cfg, \
1785 hostrcb->hcam.u.error64.fd_res_path, \
1786 hostrcb->rp_buffer, \
1787 sizeof(hostrcb->rp_buffer)), \
1788 __VA_ARGS__); \
1789 } else { \
1790 ipr_ra_err((hostrcb)->ioa_cfg, \
1791 (hostrcb)->hcam.u.error.fd_res_addr, \
1792 fmt, __VA_ARGS__); \
1793 } \
1794 } else { \
1795 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1796 } \
1797 }
1798
1799 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1800 __FILE__, __func__, __LINE__)
1801
1802 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1803 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1804
1805 #define ipr_err_separator \
1806 ipr_err("----------------------------------------------------------\n")
1807
1808
1809 /*
1810 * Inlines
1811 */
1812
1813 /**
1814 * ipr_is_ioa_resource - Determine if a resource is the IOA
1815 * @res: resource entry struct
1816 *
1817 * Return value:
1818 * 1 if IOA / 0 if not IOA
1819 **/
1820 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1821 {
1822 return res->type == IPR_RES_TYPE_IOAFP;
1823 }
1824
1825 /**
1826 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1827 * @res: resource entry struct
1828 *
1829 * Return value:
1830 * 1 if AF DASD / 0 if not AF DASD
1831 **/
1832 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1833 {
1834 return res->type == IPR_RES_TYPE_AF_DASD ||
1835 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1836 }
1837
1838 /**
1839 * ipr_is_vset_device - Determine if a resource is a VSET
1840 * @res: resource entry struct
1841 *
1842 * Return value:
1843 * 1 if VSET / 0 if not VSET
1844 **/
1845 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1846 {
1847 return res->type == IPR_RES_TYPE_VOLUME_SET;
1848 }
1849
1850 /**
1851 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1852 * @res: resource entry struct
1853 *
1854 * Return value:
1855 * 1 if GSCSI / 0 if not GSCSI
1856 **/
1857 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1858 {
1859 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1860 }
1861
1862 /**
1863 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1864 * @res: resource entry struct
1865 *
1866 * Return value:
1867 * 1 if SCSI disk / 0 if not SCSI disk
1868 **/
1869 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1870 {
1871 if (ipr_is_af_dasd_device(res) ||
1872 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1873 return 1;
1874 else
1875 return 0;
1876 }
1877
1878 /**
1879 * ipr_is_gata - Determine if a resource is a generic ATA resource
1880 * @res: resource entry struct
1881 *
1882 * Return value:
1883 * 1 if GATA / 0 if not GATA
1884 **/
1885 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1886 {
1887 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1888 }
1889
1890 /**
1891 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1892 * @res: resource entry struct
1893 *
1894 * Return value:
1895 * 1 if NACA queueing model / 0 if not NACA queueing model
1896 **/
1897 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1898 {
1899 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1900 return 1;
1901 return 0;
1902 }
1903
1904 /**
1905 * ipr_is_device - Determine if the hostrcb structure is related to a device
1906 * @hostrcb: host resource control blocks struct
1907 *
1908 * Return value:
1909 * 1 if AF / 0 if not AF
1910 **/
1911 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1912 {
1913 struct ipr_res_addr *res_addr;
1914 u8 *res_path;
1915
1916 if (hostrcb->ioa_cfg->sis64) {
1917 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1918 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1919 res_path[0] == 0x81) && res_path[2] != 0xFF)
1920 return 1;
1921 } else {
1922 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1923
1924 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1925 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1926 return 1;
1927 }
1928 return 0;
1929 }
1930
1931 /**
1932 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1933 * @sdt_word: SDT address
1934 *
1935 * Return value:
1936 * 1 if format 2 / 0 if not
1937 **/
1938 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1939 {
1940 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1941
1942 switch (bar_sel) {
1943 case IPR_SDT_FMT2_BAR0_SEL:
1944 case IPR_SDT_FMT2_BAR1_SEL:
1945 case IPR_SDT_FMT2_BAR2_SEL:
1946 case IPR_SDT_FMT2_BAR3_SEL:
1947 case IPR_SDT_FMT2_BAR4_SEL:
1948 case IPR_SDT_FMT2_BAR5_SEL:
1949 case IPR_SDT_FMT2_EXP_ROM_SEL:
1950 return 1;
1951 };
1952
1953 return 0;
1954 }
1955
1956 #ifndef writeq
1957 static inline void writeq(u64 val, void __iomem *addr)
1958 {
1959 writel(((u32) (val >> 32)), addr);
1960 writel(((u32) (val)), (addr + 4));
1961 }
1962 #endif
1963
1964 #endif /* _IPR_H */
Linux kernel - Deliverables
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