drivers/scsi/isci/core/scu_registers.h

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #ifndef _SCU_REGISTERS_H_
  57 #define _SCU_REGISTERS_H_
  58
  59 /**
  60  * This file contains the constants and structures for the SCU memory mapped
  61  *    registers.
  62  *
  63  *
  64  */
  65
  66 #include "scu_viit_data.h"
  67
  68
  69 /* Generate a value for an SCU register */
  70 #define SCU_GEN_VALUE(name, value) \
  71         (((value) << name ## _SHIFT) & (name ## _MASK))
  72
  73 /*
  74  * Generate a bit value for an SCU register
  75  * Make sure that the register MASK is just a single bit */
  76 #define SCU_GEN_BIT(name) \
  77         SCU_GEN_VALUE(name, ((u32)1))
  78
  79 #define SCU_SET_BIT(name, reg_value) \
  80         ((reg_value) | SCU_GEN_BIT(name))
  81
  82 #define SCU_CLEAR_BIT(name, reg_value) \
  83         ((reg_value)$ ~(SCU_GEN_BIT(name)))
  84
  85 /*
  86  * *****************************************************************************
  87  * Unions for bitfield definitions of SCU Registers
  88  * SMU Post Context Port
  89  * ***************************************************************************** */
  90 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT         (0)
  91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK          (0x00000FFF)
  92 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT    (12)
  93 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK     (0x0000F000)
  94 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT       (16)
  95 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK        (0x00030000)
  96 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT       (18)
  97 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK        (0x00FC0000)
  98 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK               (0xFF000000)
  99
 100 #define SMU_PCP_GEN_VAL(name, value) \
 101         SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)
 102
 103 /* ***************************************************************************** */
 104 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT       (31)
 105 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK        (0x80000000)
 106 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT    (1)
 107 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK     (0x00000002)
 108 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT      (0)
 109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK       (0x00000001)
 110 #define SMU_INTERRUPT_STATUS_RESERVED_MASK          (0x7FFFFFFC)
 111
 112 #define SMU_ISR_GEN_BIT(name) \
 113         SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)
 114
 115 #define SMU_ISR_QUEUE_ERROR   SMU_ISR_GEN_BIT(QUEUE_ERROR)
 116 #define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND)
 117 #define SMU_ISR_COMPLETION    SMU_ISR_GEN_BIT(COMPLETION)
 118
 119 /* ***************************************************************************** */
 120 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT         (31)
 121 #define SMU_INTERRUPT_MASK_COMPLETION_MASK          (0x80000000)
 122 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT      (1)
 123 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK       (0x00000002)
 124 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT        (0)
 125 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK         (0x00000001)
 126 #define SMU_INTERRUPT_MASK_RESERVED_MASK            (0x7FFFFFFC)
 127
 128 #define SMU_IMR_GEN_BIT(name) \
 129         SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)
 130
 131 #define SMU_IMR_QUEUE_ERROR   SMU_IMR_GEN_BIT(QUEUE_ERROR)
 132 #define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND)
 133 #define SMU_IMR_COMPLETION    SMU_IMR_GEN_BIT(COMPLETION)
 134
 135 /* ***************************************************************************** */
 136 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT    (0)
 137 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK     (0x0000001F)
 138 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT   (8)
 139 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK    (0x0000FF00)
 140 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK  (0xFFFF00E0)
 141
 142 #define SMU_ICC_GEN_VAL(name, value) \
 143         SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)
 144
 145 /* ***************************************************************************** */
 146 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT      (0)
 147 #define SMU_TASK_CONTEXT_RANGE_START_MASK       (0x00000FFF)
 148 #define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT     (16)
 149 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK      (0x0FFF0000)
 150 #define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT     (31)
 151 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK      (0x80000000)
 152 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK    (0x7000F000)
 153
 154 #define SMU_TCR_GEN_VAL(name, value) \
 155         SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)
 156
 157 #define SMU_TCR_GEN_BIT(name, value) \
 158         SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)
 159
 160 /* ***************************************************************************** */
 161
 162 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT          (0)
 163 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK           (0x00003FFF)
 164 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT        (15)
 165 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK         (0x00008000)
 166 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT    (16)
 167 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK     (0x03FF0000)
 168 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT  (26)
 169 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK   (0x04000000)
 170 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK          (0xF8004000)
 171
 172 #define SMU_CQPR_GEN_VAL(name, value) \
 173         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)
 174
 175 #define SMU_CQPR_GEN_BIT(name) \
 176         SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)
 177
 178 /* ***************************************************************************** */
 179
 180 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT          (0)
 181 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK           (0x00003FFF)
 182 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT        (15)
 183 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK         (0x00008000)
 184 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT    (16)
 185 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK     (0x03FF0000)
 186 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT  (26)
 187 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK   (0x04000000)
 188 #define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT           (30)
 189 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK            (0x40000000)
 190 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT     (31)
 191 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK      (0x80000000)
 192 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK          (0x38004000)
 193
 194 #define SMU_CQGR_GEN_VAL(name, value) \
 195         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)
 196
 197 #define SMU_CQGR_GEN_BIT(name) \
 198         SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)
 199
 200 #define SMU_CQGR_CYCLE_BIT \
 201         SMU_CQGR_GEN_BIT(CYCLE_BIT)
 202
 203 #define SMU_CQGR_EVENT_CYCLE_BIT \
 204         SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)
 205
 206 #define SMU_CQGR_GET_POINTER_SET(value) \
 207         SMU_CQGR_GEN_VAL(POINTER, value)
 208
 209
 210 /* ***************************************************************************** */
 211 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT  (0)
 212 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK   (0x00003FFF)
 213 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT  (16)
 214 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK   (0x03FF0000)
 215 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK      (0xFC00C000)
 216
 217 #define SMU_CQC_GEN_VAL(name, value) \
 218         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)
 219
 220 #define SMU_CQC_QUEUE_LIMIT_SET(value) \
 221         SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)
 222
 223 #define SMU_CQC_EVENT_LIMIT_SET(value) \
 224         SMU_CQC_GEN_VAL(EVENT_LIMIT, value)
 225
 226
 227 /* ***************************************************************************** */
 228 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT    (0)
 229 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK     (0x00000FFF)
 230 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT    (12)
 231 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK     (0x00007000)
 232 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT   (15)
 233 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK    (0x07FF8000)
 234 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT   (27)
 235 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK    (0x08000000)
 236 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK   (0xF0000000)
 237
 238 #define SMU_DCC_GEN_VAL(name, value) \
 239         SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)
 240
 241 #define SMU_DCC_GET_MAX_PEG(value) \
 242         (\
 243                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \
 244                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
 245         )
 246
 247 #define SMU_DCC_GET_MAX_LP(value) \
 248         (\
 249                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
 250                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
 251         )
 252
 253 #define SMU_DCC_GET_MAX_TC(value) \
 254         (\
 255                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
 256                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \
 257         )
 258
 259 #define SMU_DCC_GET_MAX_RNC(value) \
 260         (\
 261                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
 262                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \
 263         )
 264
 265 /* -------------------------------------------------------------------------- */
 266
 267 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT      (0)
 268 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK       (0x00000001)
 269 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT    (1)
 270 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK     (0x00000002)
 271 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT     (16)
 272 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK      (0x00010000)
 273 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT   (17)
 274 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK    (0x00020000)
 275 #define SMU_CONTROL_STATUS_RESERVED_MASK                        (0xFFFCFFFC)
 276
 277 #define SMU_SMUCSR_GEN_BIT(name) \
 278         SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)
 279
 280 #define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
 281         (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))
 282
 283 #define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED   \
 284         (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))
 285
 286 #define SCU_RAM_INIT_COMPLETED \
 287         (\
 288                 SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
 289                 | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
 290         )
 291
 292 /* -------------------------------------------------------------------------- */
 293
 294 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT  (0)
 295 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK   (0x00000001)
 296 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT  (1)
 297 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK   (0x00000002)
 298 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT  (2)
 299 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK   (0x00000004)
 300 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT  (3)
 301 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK   (0x00000008)
 302 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT  (8)
 303 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK   (0x00000100)
 304 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT  (9)
 305 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK   (0x00000200)
 306 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT  (10)
 307 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK   (0x00000400)
 308 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT  (11)
 309 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK   (0x00000800)
 310
 311 #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \
 312         ((1 << (pe)) << ((peg) * 8))
 313
 314 #define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
 315         (\
 316                 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
 317                 | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \
 318                 | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \
 319                 | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \
 320         )
 321
 322 #define SMU_RESET_ALL_PROTOCOL_ENGINES() \
 323         (\
 324                 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
 325                 | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \
 326         )
 327
 328 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT  (16)
 329 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK   (0x00010000)
 330 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT  (17)
 331 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK   (0x00020000)
 332 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT  (18)
 333 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK   (0x00040000)
 334 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT  (19)
 335 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK   (0x00080000)
 336
 337 #define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \
 338         ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)
 339
 340 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT      (20)
 341 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK       (0x00100000)
 342 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT      (21)
 343 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK       (0x00200000)
 344 #define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT       (22)
 345 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK        (0x00400000)
 346
 347 /*
 348  * It seems to make sense that if you are going to reset the protocol
 349  * engine group that you would also reset all of the protocol engines */
 350 #define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \
 351         (\
 352                 (1 << ((peg) + 20)) \
 353                 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
 354                 | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \
 355                 | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
 356         )
 357
 358 #define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \
 359         (\
 360                 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
 361                 | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \
 362         )
 363
 364 #define SMU_RESET_SCU()  (0xFFFFFFFF)
 365
 366
 367
 368 /* ***************************************************************************** */
 369 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT              (0)
 370 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK               (0x00000FFF)
 371 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT                (16)
 372 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK                 (0x0FFF0000)
 373 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT    (31)
 374 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK     (0x80000000)
 375 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK               (0x7000F000)
 376
 377 #define SMU_TCA_GEN_VAL(name, value) \
 378         SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)
 379
 380 #define SMU_TCA_GEN_BIT(name) \
 381         SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)
 382
 383 /* ***************************************************************************** */
 384 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT   (0)
 385 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK    (0x00000FFF)
 386 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK      (0xFFFFF000)
 387
 388 #define SCU_UFQC_GEN_VAL(name, value) \
 389         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)
 390
 391 #define SCU_UFQC_QUEUE_SIZE_SET(value) \
 392         SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
 393
 394 /* ***************************************************************************** */
 395 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT      (0)
 396 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK       (0x00000FFF)
 397 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT    (12)
 398 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK     (0x00001000)
 399 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK      (0xFFFFE000)
 400
 401 #define SCU_UFQPP_GEN_VAL(name, value) \
 402         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)
 403
 404 #define SCU_UFQPP_GEN_BIT(name) \
 405         SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)
 406
 407 /*
 408  * *****************************************************************************
 409  * * SDMA Registers
 410  * ***************************************************************************** */
 411 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT      (0)
 412 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK       (0x00000FFF)
 413 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT    (12)
 414 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK     (12)
 415 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT   (31)
 416 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK    (0x80000000)
 417 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK      (0x7FFFE000)
 418
 419 #define SCU_UFQGP_GEN_VAL(name, value) \
 420         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)
 421
 422 #define SCU_UFQGP_GEN_BIT(name) \
 423         SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)
 424
 425 #define SCU_UFQGP_CYCLE_BIT(value) \
 426         SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)
 427
 428 #define SCU_UFQGP_GET_POINTER(value) \
 429         SCU_UFQGP_GEN_VALUE(POINTER, value)
 430
 431 #define SCU_UFQGP_ENABLE(value) \
 432         (SCU_UFQGP_GEN_BIT(ENABLE) | value)
 433
 434 #define SCU_UFQGP_DISABLE(value) \
 435         (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
 436
 437 #define SCU_UFQGP_VALUE(bit, value) \
 438         (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))
 439
 440 /* ***************************************************************************** */
 441 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT                               (0)
 442 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK                                (0x0000FFFF)
 443 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (16)
 444 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00010000)
 445 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT                            (17)
 446 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK                             (0x00020000)
 447 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT                   (18)
 448 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK                    (0x00040000)
 449 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT               (19)
 450 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK                (0x00080000)
 451 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT     (20)
 452 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK      (0x00100000)
 453 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT        (21)
 454 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK         (0x00200000)
 455 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT                        (22)
 456 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK                         (0x00400000)
 457 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK                                        (0xFF800000)
 458
 459 #define SCU_PDMACR_GEN_VALUE(name, value) \
 460         SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)
 461
 462 #define SCU_PDMACR_GEN_BIT(name) \
 463         SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)
 464
 465 #define SCU_PDMACR_BE_GEN_BIT(name) \
 466         SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)
 467
 468 /* ***************************************************************************** */
 469 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (8)
 470 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00000100)
 471
 472 #define SCU_CDMACR_GEN_BIT(name) \
 473         SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)
 474
 475 /*
 476  * *****************************************************************************
 477  * * SCU Link Layer Registers
 478  * ***************************************************************************** */
 479 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT             (0)
 480 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK              (0x000000FF)
 481 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT           (8)
 482 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK            (0x0000FF00)
 483 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT   (16)
 484 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK    (0x00FF0000)
 485 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT  (24)
 486 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK   (0xFF000000)
 487 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK             (0x00000000)
 488 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK              (0x7D00676F)
 489 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK             (0x00FF0000)
 490
 491 #define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \
 492         SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)
 493
 494
 495 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT            (2)
 496 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK             (0x00000004)
 497 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT  (4)
 498 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK   (0x00000010)
 499 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT     (5)
 500 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK      (0x00000020)
 501 #define SCU_LINK_STATUS_RESERVED_MASK                       (0xFFFFFFCD)
 502
 503 #define SCU_SAS_LLSTA_GEN_BIT(name) \
 504         SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)
 505
 506
 507 /* TODO: Where is the SATA_PSELTOV register? */
 508
 509 /*
 510  * *****************************************************************************
 511  * * SCU SAS Maximum Arbitration Wait Time Timeout Register
 512  * ***************************************************************************** */
 513 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT       (0)
 514 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK        (0x00007FFF)
 515 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT       (15)
 516 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK        (0x00008000)
 517
 518 #define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \
 519         SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)
 520
 521 #define SCU_SAS_MAWTTOV_GEN_BIT(name) \
 522         SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)
 523
 524
 525 /*
 526  * TODO: Where is the SAS_LNKTOV regsiter?
 527  * TODO: Where is the SAS_PHYTOV register? */
 528
 529 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT            (1)
 530 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK             (0x00000002)
 531 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT            (2)
 532 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK             (0x00000004)
 533 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT            (3)
 534 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK             (0x00000008)
 535 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT          (8)
 536 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK           (0x00000100)
 537 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT         (9)
 538 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK          (0x00000200)
 539 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT         (10)
 540 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK          (0x00000400)
 541 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT         (11)
 542 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK          (0x00000800)
 543 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT           (16)
 544 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK            (0x000F0000)
 545 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT    (24)
 546 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK     (0x0F000000)
 547 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT           (28)
 548 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK            (0x70000000)
 549 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK               (0x80F0F1F1)
 550
 551 #define SCU_SAS_TIID_GEN_VAL(name, value) \
 552         SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)
 553
 554 #define SCU_SAS_TIID_GEN_BIT(name) \
 555         SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)
 556
 557 /* SAS Identify Frame PHY Identifier Register */
 558 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT      (16)
 559 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK       (0x00010000)
 560 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT   (17)
 561 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK    (0x00020000)
 562 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT  (18)
 563 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK   (0x00040000)
 564 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT                       (24)
 565 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK                        (0xFF000000)
 566 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK                  (0x00F800FF)
 567
 568 #define SCU_SAS_TIPID_GEN_VALUE(name, value) \
 569         SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)
 570
 571 #define SCU_SAS_TIPID_GEN_BIT(name) \
 572         SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)
 573
 574
 575 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT                     (4)
 576 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK                      (0x00000010)
 577 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT                          (6)
 578 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK                           (0x00000040)
 579 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT                   (7)
 580 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK                    (0x00000080)
 581 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT                 (8)
 582 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK                  (0x00000100)
 583 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT            (9)
 584 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK             (0x00000200)
 585 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT             (11)
 586 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK              (0x00000800)
 587 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT                    (12)
 588 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK                     (0x00001000)
 589 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT      (13)
 590 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK       (0x00002000)
 591 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT                          (14)
 592 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK                           (0x00004000)
 593 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT                          (15)
 594 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK                           (0x00008000)
 595 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT        (23)
 596 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK         (0x00800000)
 597 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT              (27)
 598 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK               (0x08000000)
 599 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT    (28)
 600 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK     (0x10000000)
 601 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT                           (29)
 602 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK                            (0x20000000)
 603 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT                    (30)
 604 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK                     (0x40000000)
 605 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT                   (31)
 606 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK                    (0x80000000)
 607 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK                             (0x0100000F)
 608 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK                              (0x4180100F)
 609 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK                             (0x00000000)
 610
 611 #define SCU_SAS_PCFG_GEN_BIT(name) \
 612         SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
 613
 614
 615 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT    (0)
 616 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK     (0x0003FFFF)
 617 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT   (31)
 618 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK    (0x80000000)
 619 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK  (0x7FFC0000)
 620
 621 #define SCU_ENSPINUP_GEN_VAL(name, value) \
 622         SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)
 623
 624 #define SCU_ENSPINUP_GEN_BIT(name) \
 625         SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)
 626
 627
 628 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT     (1)
 629 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK      (0x00000002)
 630 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT       (4)
 631 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK        (0x000000F0)
 632 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT     (8)
 633 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK      (0x00000100)
 634 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT      (9)
 635 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK       (0x00000201)
 636 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT     (10)
 637 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK      (0x00000401)
 638 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT      (11)
 639 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK       (0x00000801)
 640 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT     (12)
 641 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK      (0x00001001)
 642 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT      (13)
 643 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK       (0x00002001)
 644 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT   (31)
 645 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK    (0x80000000)
 646 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK        (0x00003F01)
 647 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK       (0x00000001)
 648 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK       (0x7FFFC00D)
 649
 650 #define SCU_SAS_PHYCAP_GEN_VAL(name, value) \
 651         SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)
 652
 653 #define SCU_SAS_PHYCAP_GEN_BIT(name) \
 654         SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)
 655
 656
 657 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT  (0)
 658 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK   (0x000000FF)
 659 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT         (31)
 660 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK          (0x80000000)
 661 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK                          (0x7FFFFF00)
 662
 663 #define SCU_PSZGCR_GEN_VAL(name, value) \
 664         SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)
 665
 666 #define SCU_PSZGCR_GEN_BIT(name) \
 667         SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)
 668
 669 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT        (1)
 670 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK         (0x00000002)
 671 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT      (2)
 672 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK       (0x00000004)
 673 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT        (4)
 674 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK         (0x00000010)
 675 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT      (5)
 676 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK       (0x00000020)
 677 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16)
 678 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK  (0x00030000)
 679 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT      (19)
 680 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK       (0x00080000)
 681 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20)
 682 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK  (0x00300000)
 683 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT      (23)
 684 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK       (0x00800000)
 685 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24)
 686 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK  (0x03000000)
 687 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT      (27)
 688 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK       (0x08000000)
 689 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28)
 690 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK  (0x30000000)
 691 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT      (31)
 692 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK       (0x80000000)
 693 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK             (0x4444FFC9)
 694
 695 #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \
 696         SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)
 697
 698 #define SCU_PEG_SCUVZECR_GEN_BIT(name) \
 699         SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)
 700
 701
 702 /*
 703  * *****************************************************************************
 704  * * Port Task Scheduler registers shift and mask values
 705  * ***************************************************************************** */
 706 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT     (0)
 707 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK      (0x0000FFFF)
 708 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT         (16)
 709 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK          (0x00FF0000)
 710 #define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT          (24)
 711 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK           (0x01000000)
 712 #define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT           (25)
 713 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK            (0x02000000)
 714 #define SCU_PTSG_CONTROL_DEFAULT_MASK               (0x00020002)
 715 #define SCU_PTSG_CONTROL_REQUIRED_MASK              (0x00000000)
 716 #define SCU_PTSG_CONTROL_RESERVED_MASK              (0xFC000000)
 717
 718 #define SCU_PTSGCR_GEN_VAL(name, val) \
 719         SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)
 720
 721 #define SCU_PTSGCR_GEN_BIT(name) \
 722         SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)
 723
 724
 725 /* ***************************************************************************** */
 726 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT          (0)
 727 #define SCU_PTSG_REAL_TIME_CLOCK_MASK           (0x0000FFFF)
 728 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK  (0xFFFF0000)
 729
 730 #define SCU_RTCR_GEN_VAL(name, val) \
 731         SCU_GEN_VALUE(SCU_PTSG_ ## name, val)
 732
 733
 734 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT  (0)
 735 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK   (0x00FFFFFF)
 736 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK          (0xFF000000)
 737
 738 #define SCU_RTCCR_GEN_VAL(name, val) \
 739         SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)
 740
 741
 742 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT  (0)
 743 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK   (0x00000001)
 744 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT   (1)
 745 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK    (0x00000002)
 746 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK  (0xFFFFFFFC)
 747
 748 #define SCU_PTSxCR_GEN_BIT(name) \
 749         SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)
 750
 751
 752 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT             (0)
 753 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK              (0x00000001)
 754 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT    (1)
 755 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK     (0x00000002)
 756 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT             (2)
 757 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK              (0x00000004)
 758 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK                   (0xFFFFFFF8)
 759
 760 #define SCU_PTSxSR_GEN_BIT(name) \
 761         SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)
 762
 763
 764 /*
 765  * *****************************************************************************
 766  * * SGPIO Register shift and mask values
 767  * ***************************************************************************** */
 768 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT                    (0)
 769 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK                     (0x00000001)
 770 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT       (1)
 771 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK        (0x00000002)
 772 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2)
 773 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK  (0x00000004)
 774 #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT                  (15)
 775 #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK                   (0x00008000)
 776 #define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK                   (0xFFFF7FF8)
 777
 778 #define SCU_SGICRx_GEN_BIT(name) \
 779         SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_ ## name)
 780
 781 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT      (0)
 782 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK       (0x0000000F)
 783 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT      (4)
 784 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK       (0x000000F0)
 785 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT      (8)
 786 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK       (0x00000F00)
 787 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT      (12)
 788 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK       (0x0000F000)
 789 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000)
 790
 791 #define SCU_SGPBRx_GEN_VAL(name, value) \
 792         SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_ ## name, value)
 793
 794 #define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT        (0)
 795 #define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK         (0x00000003)
 796 #define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT        (4)
 797 #define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK         (0x00000030)
 798 #define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT        (8)
 799 #define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK         (0x00000300)
 800 #define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT        (12)
 801 #define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK         (0x00003000)
 802 #define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK   (0xFFFF8888)
 803
 804 #define SCU_SGSDLRx_GEN_VAL(name, value) \
 805         SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)
 806
 807 #define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT        (0)
 808 #define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK         (0x00000003)
 809 #define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT        (4)
 810 #define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK         (0x00000030)
 811 #define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT        (8)
 812 #define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK         (0x00000300)
 813 #define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT        (12)
 814 #define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK         (0x00003000)
 815 #define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK   (0xFFFF8888)
 816
 817 #define SCU_SGSDURx_GEN_VAL(name, value) \
 818         SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)
 819
 820 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT      (0)
 821 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK       (0x00000003)
 822 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT      (4)
 823 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK       (0x00000030)
 824 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT      (8)
 825 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK       (0x00000300)
 826 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT      (12)
 827 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK       (0x00003000)
 828 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888)
 829
 830 #define SCU_SGSIDLRx_GEN_VAL(name, value) \
 831         SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)
 832
 833 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT      (0)
 834 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK       (0x00000003)
 835 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT      (4)
 836 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK       (0x00000030)
 837 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT      (8)
 838 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK       (0x00000300)
 839 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT      (12)
 840 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK       (0x00003000)
 841 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888)
 842
 843 #define SCU_SGSIDURx_GEN_VAL(name, value) \
 844         SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)
 845
 846 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT            (0)
 847 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK             (0x0000000F)
 848 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK    (0xFFFFFFF0)
 849
 850 #define SCU_SGVSCR_GEN_VAL(value) \
 851         SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE ## name, value)
 852
 853 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT           (0)
 854 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK            (0x00000003)
 855 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT    (2)
 856 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK     (0x00000004)
 857 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT      (3)
 858 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK       (0x00000008)
 859 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT           (4)
 860 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK            (0x00000030)
 861 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT    (6)
 862 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK     (0x00000040)
 863 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT      (7)
 864 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK       (0x00000080)
 865 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT           (8)
 866 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK            (0x00000300)
 867 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT    (10)
 868 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK     (0x00000400)
 869 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT      (11)
 870 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK       (0x00000800)
 871 #define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK               (0xFFFFF000)
 872
 873 #define SCU_SGODSR_GEN_VAL(name, value) \
 874         SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name, value)
 875
 876 #define SCU_SGODSR_GEN_BIT(name) \
 877         SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name)
 878
 879 /*
 880  * *****************************************************************************
 881  * * SMU Registers
 882  * ***************************************************************************** */
 883
 884 /*
 885  * ----------------------------------------------------------------------------
 886  * SMU Registers
 887  * These registers are based off of BAR0
 888  *
 889  * To calculate the offset for other functions use
 890  *       BAR0 + FN# * SystemPageSize * 2
 891  *
 892  * The TCA is only accessable from FN#0 (Physical Function) and each
 893  * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
 894  *    TCA0 for FN#0 is at BAR0 + 0x0400
 895  *    TCA1 for FN#1 is at BAR0 + 0x0404
 896  *    etc.
 897  * ----------------------------------------------------------------------------
 898  * Accessable to all FN#s */
 899 #define SCU_SMU_PCP_OFFSET          0x0000
 900 #define SCU_SMU_AMR_OFFSET          0x0004
 901 #define SCU_SMU_ISR_OFFSET          0x0010
 902 #define SCU_SMU_IMR_OFFSET          0x0014
 903 #define SCU_SMU_ICC_OFFSET          0x0018
 904 #define SCU_SMU_HTTLBAR_OFFSET      0x0020
 905 #define SCU_SMU_HTTUBAR_OFFSET      0x0024
 906 #define SCU_SMU_TCR_OFFSET          0x0028
 907 #define SCU_SMU_CQLBAR_OFFSET       0x0030
 908 #define SCU_SMU_CQUBAR_OFFSET       0x0034
 909 #define SCU_SMU_CQPR_OFFSET         0x0040
 910 #define SCU_SMU_CQGR_OFFSET         0x0044
 911 #define SCU_SMU_CQC_OFFSET          0x0048
 912 /* Accessable to FN#0 only */
 913 #define SCU_SMU_RNCLBAR_OFFSET      0x0080
 914 #define SCU_SMU_RNCUBAR_OFFSET      0x0084
 915 #define SCU_SMU_DCC_OFFSET          0x0090
 916 #define SCU_SMU_DFC_OFFSET          0x0094
 917 #define SCU_SMU_SMUCSR_OFFSET       0x0098
 918 #define SCU_SMU_SCUSRCR_OFFSET      0x009C
 919 #define SCU_SMU_SMAW_OFFSET         0x00A0
 920 #define SCU_SMU_SMDW_OFFSET         0x00A4
 921 /* Accessable to FN#0 only */
 922 #define SCU_SMU_TCA_OFFSET          0x0400
 923 /* Accessable to all FN#s */
 924 #define SCU_SMU_MT_MLAR0_OFFSET     0x2000
 925 #define SCU_SMU_MT_MUAR0_OFFSET     0x2004
 926 #define SCU_SMU_MT_MDR0_OFFSET      0x2008
 927 #define SCU_SMU_MT_VCR0_OFFSET      0x200C
 928 #define SCU_SMU_MT_MLAR1_OFFSET     0x2010
 929 #define SCU_SMU_MT_MUAR1_OFFSET     0x2014
 930 #define SCU_SMU_MT_MDR1_OFFSET      0x2018
 931 #define SCU_SMU_MT_VCR1_OFFSET      0x201C
 932 #define SCU_SMU_MPBA_OFFSET         0x3000
 933
 934 /**
 935  * struct smu_registers - These are the SMU registers
 936  *
 937  *
 938  */
 939 struct smu_registers {
 940 /* 0x0000 PCP */
 941         u32 post_context_port;
 942 /* 0x0004 AMR */
 943         u32 address_modifier;
 944         u32 reserved_08;
 945         u32 reserved_0C;
 946 /* 0x0010 ISR */
 947         u32 interrupt_status;
 948 /* 0x0014 IMR */
 949         u32 interrupt_mask;
 950 /* 0x0018 ICC */
 951         u32 interrupt_coalesce_control;
 952         u32 reserved_1C;
 953 /* 0x0020 HTTLBAR */
 954         u32 host_task_table_lower;
 955 /* 0x0024 HTTUBAR */
 956         u32 host_task_table_upper;
 957 /* 0x0028 TCR */
 958         u32 task_context_range;
 959         u32 reserved_2C;
 960 /* 0x0030 CQLBAR */
 961         u32 completion_queue_lower;
 962 /* 0x0034 CQUBAR */
 963         u32 completion_queue_upper;
 964         u32 reserved_38;
 965         u32 reserved_3C;
 966 /* 0x0040 CQPR */
 967         u32 completion_queue_put;
 968 /* 0x0044 CQGR */
 969         u32 completion_queue_get;
 970 /* 0x0048 CQC */
 971         u32 completion_queue_control;
 972         u32 reserved_4C;
 973         u32 reserved_5x[4];
 974         u32 reserved_6x[4];
 975         u32 reserved_7x[4];
 976 /*
 977  * Accessable to FN#0 only
 978  * 0x0080 RNCLBAR */
 979         u32 remote_node_context_lower;
 980 /* 0x0084 RNCUBAR */
 981         u32 remote_node_context_upper;
 982         u32 reserved_88;
 983         u32 reserved_8C;
 984 /* 0x0090 DCC */
 985         u32 device_context_capacity;
 986 /* 0x0094 DFC */
 987         u32 device_function_capacity;
 988 /* 0x0098 SMUCSR */
 989         u32 control_status;
 990 /* 0x009C SCUSRCR */
 991         u32 soft_reset_control;
 992 /* 0x00A0 SMAW */
 993         u32 mmr_address_window;
 994 /* 0x00A4 SMDW */
 995         u32 mmr_data_window;
 996         u32 reserved_A8;
 997         u32 reserved_AC;
 998 /* A whole bunch of reserved space */
 999         u32 reserved_Bx[4];
1000         u32 reserved_Cx[4];
1001         u32 reserved_Dx[4];
1002         u32 reserved_Ex[4];
1003         u32 reserved_Fx[4];
1004         u32 reserved_1xx[64];
1005         u32 reserved_2xx[64];
1006         u32 reserved_3xx[64];
1007 /*
1008  * Accessable to FN#0 only
1009  * 0x0400 TCA */
1010         u32 task_context_assignment[256];
1011 /* MSI-X registers not included */
1012 };
1013
1014 /*
1015  * *****************************************************************************
1016  * SDMA Registers
1017  * ***************************************************************************** */
1018 #define SCU_SDMA_BASE               0x6000
1019 #define SCU_SDMA_PUFATLHAR_OFFSET   0x0000
1020 #define SCU_SDMA_PUFATUHAR_OFFSET   0x0004
1021 #define SCU_SDMA_UFLHBAR_OFFSET     0x0008
1022 #define SCU_SDMA_UFUHBAR_OFFSET     0x000C
1023 #define SCU_SDMA_UFQC_OFFSET        0x0010
1024 #define SCU_SDMA_UFQPP_OFFSET       0x0014
1025 #define SCU_SDMA_UFQGP_OFFSET       0x0018
1026 #define SCU_SDMA_PDMACR_OFFSET      0x001C
1027 #define SCU_SDMA_CDMACR_OFFSET      0x0080
1028
1029 /**
1030  * struct scu_sdma_registers - These are the SCU SDMA Registers
1031  *
1032  *
1033  */
1034 struct scu_sdma_registers {
1035 /* 0x0000 PUFATLHAR */
1036         u32 uf_address_table_lower;
1037 /* 0x0004 PUFATUHAR */
1038         u32 uf_address_table_upper;
1039 /* 0x0008 UFLHBAR */
1040         u32 uf_header_base_address_lower;
1041 /* 0x000C UFUHBAR */
1042         u32 uf_header_base_address_upper;
1043 /* 0x0010 UFQC */
1044         u32 unsolicited_frame_queue_control;
1045 /* 0x0014 UFQPP */
1046         u32 unsolicited_frame_put_pointer;
1047 /* 0x0018 UFQGP */
1048         u32 unsolicited_frame_get_pointer;
1049 /* 0x001C PDMACR */
1050         u32 pdma_configuration;
1051 /* Reserved until offset 0x80 */
1052         u32 reserved_0020_007C[0x18];
1053 /* 0x0080 CDMACR */
1054         u32 cdma_configuration;
1055 /* Remainder SDMA register space */
1056         u32 reserved_0084_0400[0xDF];
1057
1058 };
1059
1060 /*
1061  * *****************************************************************************
1062  * * SCU Link Registers
1063  * ***************************************************************************** */
1064 #define SCU_PEG0_OFFSET    0x0000
1065 #define SCU_PEG1_OFFSET    0x8000
1066
1067 #define SCU_TL0_OFFSET     0x0000
1068 #define SCU_TL1_OFFSET     0x0400
1069 #define SCU_TL2_OFFSET     0x0800
1070 #define SCU_TL3_OFFSET     0x0C00
1071
1072 #define SCU_LL_OFFSET      0x0080
1073 #define SCU_LL0_OFFSET     (SCU_TL0_OFFSET + SCU_LL_OFFSET)
1074 #define SCU_LL1_OFFSET     (SCU_TL1_OFFSET + SCU_LL_OFFSET)
1075 #define SCU_LL2_OFFSET     (SCU_TL2_OFFSET + SCU_LL_OFFSET)
1076 #define SCU_LL3_OFFSET     (SCU_TL3_OFFSET + SCU_LL_OFFSET)
1077
1078 /* Transport Layer Offsets (PEG + TL) */
1079 #define SCU_TLCR_OFFSET         0x0000
1080 #define SCU_TLADTR_OFFSET       0x0004
1081 #define SCU_TLTTMR_OFFSET       0x0008
1082 #define SCU_TLEECR0_OFFSET      0x000C
1083 #define SCU_STPTLDARNI_OFFSET   0x0010
1084
1085
1086 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT    (0)
1087 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK     (0x00000001)
1088 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1)
1089 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK  (0x00000002)
1090 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT     (3)
1091 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK      (0x00000008)
1092 #define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT         (4)
1093 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK          (0x00000010)
1094 #define SCU_TLCR_RESERVED_MASK                     (0xFFFFFFEB)
1095
1096 #define SCU_TLCR_GEN_BIT(name) \
1097         SCU_GEN_BIT(SCU_TLCR_ ## name)
1098
1099 /**
1100  * struct scu_transport_layer_registers - These are the SCU Transport Layer
1101  *    registers
1102  *
1103  *
1104  */
1105 struct scu_transport_layer_registers {
1106         /* 0x0000 TLCR */
1107         u32 control;
1108         /* 0x0004 TLADTR */
1109         u32 arbitration_delay_timer;
1110         /* 0x0008 TLTTMR */
1111         u32 timer_test_mode;
1112         /* 0x000C reserved */
1113         u32 reserved_0C;
1114         /* 0x0010 STPTLDARNI */
1115         u32 stp_rni;
1116         /* 0x0014 TLFEWPORCTRL */
1117         u32 tlfe_wpo_read_control;
1118         /* 0x0018 TLFEWPORDATA */
1119         u32 tlfe_wpo_read_data;
1120         /* 0x001C RXTLSSCSR1 */
1121         u32 rxtl_single_step_control_status_1;
1122         /* 0x0020 RXTLSSCSR2 */
1123         u32 rxtl_single_step_control_status_2;
1124         /* 0x0024 AWTRDDCR */
1125         u32 tlfe_awt_retry_delay_debug_control;
1126         /* Remainder of TL memory space */
1127         u32 reserved_0028_007F[0x16];
1128
1129 };
1130
1131 /* Protocol Engine Group Registers */
1132 #define SCU_SCUVZECRx_OFFSET        0x1080
1133
1134 /* Link Layer Offsets (PEG + TL + LL) */
1135 #define SCU_SAS_SPDTOV_OFFSET       0x0000
1136 #define SCU_SAS_LLSTA_OFFSET        0x0004
1137 #define SCU_SATA_PSELTOV_OFFSET     0x0008
1138 #define SCU_SAS_TIMETOV_OFFSET      0x0010
1139 #define SCU_SAS_LOSTOT_OFFSET       0x0014
1140 #define SCU_SAS_LNKTOV_OFFSET       0x0018
1141 #define SCU_SAS_PHYTOV_OFFSET       0x001C
1142 #define SCU_SAS_AFERCNT_OFFSET      0x0020
1143 #define SCU_SAS_WERCNT_OFFSET       0x0024
1144 #define SCU_SAS_TIID_OFFSET         0x0028
1145 #define SCU_SAS_TIDNH_OFFSET        0x002C
1146 #define SCU_SAS_TIDNL_OFFSET        0x0030
1147 #define SCU_SAS_TISSAH_OFFSET       0x0034
1148 #define SCU_SAS_TISSAL_OFFSET       0x0038
1149 #define SCU_SAS_TIPID_OFFSET        0x003C
1150 #define SCU_SAS_TIRES2_OFFSET       0x0040
1151 #define SCU_SAS_ADRSTA_OFFSET       0x0044
1152 #define SCU_SAS_MAWTTOV_OFFSET      0x0048
1153 #define SCU_SAS_FRPLDFIL_OFFSET     0x0054
1154 #define SCU_SAS_RFCNT_OFFSET        0x0060
1155 #define SCU_SAS_TFCNT_OFFSET        0x0064
1156 #define SCU_SAS_RFDCNT_OFFSET       0x0068
1157 #define SCU_SAS_TFDCNT_OFFSET       0x006C
1158 #define SCU_SAS_LERCNT_OFFSET       0x0070
1159 #define SCU_SAS_RDISERRCNT_OFFSET   0x0074
1160 #define SCU_SAS_CRERCNT_OFFSET      0x0078
1161 #define SCU_STPCTL_OFFSET           0x007C
1162 #define SCU_SAS_PCFG_OFFSET         0x0080
1163 #define SCU_SAS_CLKSM_OFFSET        0x0084
1164 #define SCU_SAS_TXCOMWAKE_OFFSET    0x0088
1165 #define SCU_SAS_TXCOMINIT_OFFSET    0x008C
1166 #define SCU_SAS_TXCOMSAS_OFFSET     0x0090
1167 #define SCU_SAS_COMINIT_OFFSET      0x0094
1168 #define SCU_SAS_COMWAKE_OFFSET      0x0098
1169 #define SCU_SAS_COMSAS_OFFSET       0x009C
1170 #define SCU_SAS_SFERCNT_OFFSET      0x00A0
1171 #define SCU_SAS_CDFERCNT_OFFSET     0x00A4
1172 #define SCU_SAS_DNFERCNT_OFFSET     0x00A8
1173 #define SCU_SAS_PRSTERCNT_OFFSET    0x00AC
1174 #define SCU_SAS_CNTCTL_OFFSET       0x00B0
1175 #define SCU_SAS_SSPTOV_OFFSET       0x00B4
1176 #define SCU_FTCTL_OFFSET            0x00B8
1177 #define SCU_FRCTL_OFFSET            0x00BC
1178 #define SCU_FTWMRK_OFFSET           0x00C0
1179 #define SCU_ENSPINUP_OFFSET         0x00C4
1180 #define SCU_SAS_TRNTOV_OFFSET       0x00C8
1181 #define SCU_SAS_PHYCAP_OFFSET       0x00CC
1182 #define SCU_SAS_PHYCTL_OFFSET       0x00D0
1183 #define SCU_SAS_LLCTL_OFFSET        0x00D8
1184 #define SCU_AFE_XCVRCR_OFFSET       0x00DC
1185 #define SCU_AFE_LUTCR_OFFSET        0x00E0
1186
1187 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT                  (0)
1188 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK                   (0x00000003)
1189 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1                   (0)
1190 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2                   (1)
1191 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3                   (2)
1192 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT            (2)
1193 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK             (0x000003FC)
1194 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT   (16)
1195 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK    (0x00010000)
1196 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17)
1197 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK  (0x00020000)
1198 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT       (24)
1199 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK        (0xFF000000)
1200 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED                             (0x00FCFC00)
1201
1202 #define SCU_SAS_LLCTL_GEN_VAL(name, value) \
1203         SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)
1204
1205 #define SCU_SAS_LLCTL_GEN_BIT(name) \
1206         SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)
1207
1208
1209 /* #define SCU_FRXHECR_DCNT_OFFSET      0x00B0 */
1210 #define SCU_PSZGCR_OFFSET           0x00E4
1211 #define SCU_SAS_RECPHYCAP_OFFSET    0x00E8
1212 /* #define SCU_TX_LUTSEL_OFFSET         0x00B8 */
1213
1214 #define SCU_SAS_PTxC_OFFSET         0x00D4 /* Same offset as SAS_TCTSTM */
1215
1216 /**
1217  * struct scu_link_layer_registers - SCU Link Layer Registers
1218  *
1219  *
1220  */
1221 struct scu_link_layer_registers {
1222 /* 0x0000 SAS_SPDTOV */
1223         u32 speed_negotiation_timers;
1224 /* 0x0004 SAS_LLSTA */
1225         u32 link_layer_status;
1226 /* 0x0008 SATA_PSELTOV */
1227         u32 port_selector_timeout;
1228         u32 reserved0C;
1229 /* 0x0010 SAS_TIMETOV */
1230         u32 timeout_unit_value;
1231 /* 0x0014 SAS_RCDTOV */
1232         u32 rcd_timeout;
1233 /* 0x0018 SAS_LNKTOV */
1234         u32 link_timer_timeouts;
1235 /* 0x001C SAS_PHYTOV */
1236         u32 sas_phy_timeouts;
1237 /* 0x0020 SAS_AFERCNT */
1238         u32 received_address_frame_error_counter;
1239 /* 0x0024 SAS_WERCNT */
1240         u32 invalid_dword_counter;
1241 /* 0x0028 SAS_TIID */
1242         u32 transmit_identification;
1243 /* 0x002C SAS_TIDNH */
1244         u32 sas_device_name_high;
1245 /* 0x0030 SAS_TIDNL */
1246         u32 sas_device_name_low;
1247 /* 0x0034 SAS_TISSAH */
1248         u32 source_sas_address_high;
1249 /* 0x0038 SAS_TISSAL */
1250         u32 source_sas_address_low;
1251 /* 0x003C SAS_TIPID */
1252         u32 identify_frame_phy_id;
1253 /* 0x0040 SAS_TIRES2 */
1254         u32 identify_frame_reserved;
1255 /* 0x0044 SAS_ADRSTA */
1256         u32 received_address_frame;
1257 /* 0x0048 SAS_MAWTTOV */
1258         u32 maximum_arbitration_wait_timer_timeout;
1259 /* 0x004C SAS_PTxC */
1260         u32 transmit_primitive;
1261 /* 0x0050 SAS_RORES */
1262         u32 error_counter_event_notification_control;
1263 /* 0x0054 SAS_FRPLDFIL */
1264         u32 frxq_payload_fill_threshold;
1265 /* 0x0058 SAS_LLHANG_TOT */
1266         u32 link_layer_hang_detection_timeout;
1267         u32 reserved_5C;
1268 /* 0x0060 SAS_RFCNT */
1269         u32 received_frame_count;
1270 /* 0x0064 SAS_TFCNT */
1271         u32 transmit_frame_count;
1272 /* 0x0068 SAS_RFDCNT */
1273         u32 received_dword_count;
1274 /* 0x006C SAS_TFDCNT */
1275         u32 transmit_dword_count;
1276 /* 0x0070 SAS_LERCNT */
1277         u32 loss_of_sync_error_count;
1278 /* 0x0074 SAS_RDISERRCNT */
1279         u32 running_disparity_error_count;
1280 /* 0x0078 SAS_CRERCNT */
1281         u32 received_frame_crc_error_count;
1282 /* 0x007C STPCTL */
1283         u32 stp_control;
1284 /* 0x0080 SAS_PCFG */
1285         u32 phy_configuration;
1286 /* 0x0084 SAS_CLKSM */
1287         u32 clock_skew_management;
1288 /* 0x0088 SAS_TXCOMWAKE */
1289         u32 transmit_comwake_signal;
1290 /* 0x008C SAS_TXCOMINIT */
1291         u32 transmit_cominit_signal;
1292 /* 0x0090 SAS_TXCOMSAS */
1293         u32 transmit_comsas_signal;
1294 /* 0x0094 SAS_COMINIT */
1295         u32 cominit_control;
1296 /* 0x0098 SAS_COMWAKE */
1297         u32 comwake_control;
1298 /* 0x009C SAS_COMSAS */
1299         u32 comsas_control;
1300 /* 0x00A0 SAS_SFERCNT */
1301         u32 received_short_frame_count;
1302 /* 0x00A4 SAS_CDFERCNT */
1303         u32 received_frame_without_credit_count;
1304 /* 0x00A8 SAS_DNFERCNT */
1305         u32 received_frame_after_done_count;
1306 /* 0x00AC SAS_PRSTERCNT */
1307         u32 phy_reset_problem_count;
1308 /* 0x00B0 SAS_CNTCTL */
1309         u32 counter_control;
1310 /* 0x00B4 SAS_SSPTOV */
1311         u32 ssp_timer_timeout_values;
1312 /* 0x00B8 FTCTL */
1313         u32 ftx_control;
1314 /* 0x00BC FRCTL */
1315         u32 frx_control;
1316 /* 0x00C0 FTWMRK */
1317         u32 ftx_watermark;
1318 /* 0x00C4 ENSPINUP */
1319         u32 notify_enable_spinup_control;
1320 /* 0x00C8 SAS_TRNTOV */
1321         u32 sas_training_sequence_timer_values;
1322 /* 0x00CC SAS_PHYCAP */
1323         u32 phy_capabilities;
1324 /* 0x00D0 SAS_PHYCTL */
1325         u32 phy_control;
1326         u32 reserved_d4;
1327 /* 0x00D8 LLCTL */
1328         u32 link_layer_control;
1329 /* 0x00DC AFE_XCVRCR */
1330         u32 afe_xcvr_control;
1331 /* 0x00E0 AFE_LUTCR */
1332         u32 afe_lookup_table_control;
1333 /* 0x00E4 PSZGCR */
1334         u32 phy_source_zone_group_control;
1335 /* 0x00E8 SAS_RECPHYCAP */
1336         u32 receive_phycap;
1337         u32 reserved_ec;
1338 /* 0x00F0 SNAFERXRSTCTL */
1339         u32 speed_negotiation_afe_rx_reset_control;
1340 /* 0x00F4 SAS_SSIPMCTL */
1341         u32 power_management_control;
1342 /* 0x00F8 SAS_PSPREQ_PRIM */
1343         u32 sas_pm_partial_request_primitive;
1344 /* 0x00FC SAS_PSSREQ_PRIM */
1345         u32 sas_pm_slumber_request_primitive;
1346 /* 0x0100 SAS_PPSACK_PRIM */
1347         u32 sas_pm_ack_primitive_register;
1348 /* 0x0104 SAS_PSNAK_PRIM */
1349         u32 sas_pm_nak_primitive_register;
1350 /* 0x0108 SAS_SSIPMTOV */
1351         u32 sas_primitive_timeout;
1352         u32 reserved_10c;
1353 /* 0x0110 - 0x011C PLAPRDCTRLxREG */
1354         u32 pla_product_control[4];
1355 /* 0x0120 PLAPRDSUMREG */
1356         u32 pla_product_sum;
1357 /* 0x0124 PLACONTROLREG */
1358         u32 pla_control;
1359 /* Remainder of memory space 896 bytes */
1360         u32 reserved_0128_037f[0x96];
1361
1362 };
1363
1364 /*
1365  * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
1366  *   u32   primitive_transmit_control; */
1367
1368 /*
1369  * ----------------------------------------------------------------------------
1370  * SGPIO
1371  * ---------------------------------------------------------------------------- */
1372 #define SCU_SGPIO_OFFSET         0x1400
1373
1374 /* #define SCU_SGPIO_OFFSET         0x6000   // later moves to 0x1400 see HSD 652625 */
1375 #define SCU_SGPIO_SGICR_OFFSET   0x0000
1376 #define SCU_SGPIO_SGPBR_OFFSET   0x0004
1377 #define SCU_SGPIO_SGSDLR_OFFSET  0x0008
1378 #define SCU_SGPIO_SGSDUR_OFFSET  0x000C
1379 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
1380 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
1381 #define SCU_SGPIO_SGVSCR_OFFSET  0x0018
1382 /* Address from 0x0820 to 0x083C */
1383 #define SCU_SGPIO_SGODSR_OFFSET  0x0020
1384
1385 /**
1386  * struct scu_sgpio_registers - SCU SGPIO Registers
1387  *
1388  *
1389  */
1390 struct scu_sgpio_registers {
1391 /* 0x0000 SGPIO_SGICR */
1392         u32 interface_control;
1393 /* 0x0004 SGPIO_SGPBR */
1394         u32 blink_rate;
1395 /* 0x0008 SGPIO_SGSDLR */
1396         u32 start_drive_lower;
1397 /* 0x000C SGPIO_SGSDUR */
1398         u32 start_drive_upper;
1399 /* 0x0010 SGPIO_SGSIDLR */
1400         u32 serial_input_lower;
1401 /* 0x0014 SGPIO_SGSIDUR */
1402         u32 serial_input_upper;
1403 /* 0x0018 SGPIO_SGVSCR */
1404         u32 vendor_specific_code;
1405 /* 0x0020 SGPIO_SGODSR */
1406         u32 ouput_data_select[8];
1407 /* Remainder of memory space 256 bytes */
1408         u32 reserved_1444_14ff[0x31];
1409
1410 };
1411
1412 /*
1413  * *****************************************************************************
1414  * * Defines for VIIT entry offsets
1415  * * Access additional entries by SCU_VIIT_BASE + index * 0x10
1416  * ***************************************************************************** */
1417 #define     SCU_VIIT_BASE     0x1c00
1418
1419 struct SCU_VIIT_REGISTERS {
1420         u32 registers[256];
1421 };
1422
1423 /*
1424  * *****************************************************************************
1425  * * SCU PORT TASK SCHEDULER REGISTERS
1426  * ***************************************************************************** */
1427
1428 #define SCU_PTSG_BASE               0x1000
1429
1430 #define SCU_PTSG_PTSGCR_OFFSET      0x0000
1431 #define SCU_PTSG_RTCR_OFFSET        0x0004
1432 #define SCU_PTSG_RTCCR_OFFSET       0x0008
1433 #define SCU_PTSG_PTS0CR_OFFSET      0x0010
1434 #define SCU_PTSG_PTS0SR_OFFSET      0x0014
1435 #define SCU_PTSG_PTS1CR_OFFSET      0x0018
1436 #define SCU_PTSG_PTS1SR_OFFSET      0x001C
1437 #define SCU_PTSG_PTS2CR_OFFSET      0x0020
1438 #define SCU_PTSG_PTS2SR_OFFSET      0x0024
1439 #define SCU_PTSG_PTS3CR_OFFSET      0x0028
1440 #define SCU_PTSG_PTS3SR_OFFSET      0x002C
1441 #define SCU_PTSG_PCSPE0CR_OFFSET    0x0030
1442 #define SCU_PTSG_PCSPE1CR_OFFSET    0x0034
1443 #define SCU_PTSG_PCSPE2CR_OFFSET    0x0038
1444 #define SCU_PTSG_PCSPE3CR_OFFSET    0x003C
1445 #define SCU_PTSG_ETMTSCCR_OFFSET    0x0040
1446 #define SCU_PTSG_ETMRNSCCR_OFFSET   0x0044
1447
1448 /**
1449  * struct scu_port_task_scheduler_registers - These are the control/stats pairs
1450  *    for each Port Task Scheduler.
1451  *
1452  *
1453  */
1454 struct scu_port_task_scheduler_registers {
1455         u32 control;
1456         u32 status;
1457 };
1458
1459 typedef u32 SCU_PORT_PE_CONFIGURATION_REGISTER_T;
1460
1461 /**
1462  * struct scu_port_task_scheduler_group_registers - These are the PORT Task
1463  *    Scheduler registers
1464  *
1465  *
1466  */
1467 struct scu_port_task_scheduler_group_registers {
1468 /* 0x0000 PTSGCR */
1469         u32 control;
1470 /* 0x0004 RTCR */
1471         u32 real_time_clock;
1472 /* 0x0008 RTCCR */
1473         u32 real_time_clock_control;
1474 /* 0x000C */
1475         u32 reserved_0C;
1476 /*
1477  * 0x0010 PTS0CR
1478  * 0x0014 PTS0SR
1479  * 0x0018 PTS1CR
1480  * 0x001C PTS1SR
1481  * 0x0020 PTS2CR
1482  * 0x0024 PTS2SR
1483  * 0x0028 PTS3CR
1484  * 0x002C PTS3SR */
1485         struct scu_port_task_scheduler_registers port[4];
1486 /*
1487  * 0x0030 PCSPE0CR
1488  * 0x0034 PCSPE1CR
1489  * 0x0038 PCSPE2CR
1490  * 0x003C PCSPE3CR */
1491         SCU_PORT_PE_CONFIGURATION_REGISTER_T protocol_engine[4];
1492 /* 0x0040 ETMTSCCR */
1493         u32 tc_scanning_interval_control;
1494 /* 0x0044 ETMRNSCCR */
1495         u32 rnc_scanning_interval_control;
1496 /* Remainder of memory space 128 bytes */
1497         u32 reserved_1048_107f[0x0E];
1498
1499 };
1500
1501 #define SCU_PTSG_SCUVZECR_OFFSET        0x003C
1502
1503 /*
1504  * *****************************************************************************
1505  * * AFE REGISTERS
1506  * ***************************************************************************** */
1507 #define SCU_AFE_MMR_BASE                  0xE000
1508
1509 /*
1510  * AFE 0 is at offset 0x0800
1511  * AFE 1 is at offset 0x0900
1512  * AFE 2 is at offset 0x0a00
1513  * AFE 3 is at offset 0x0b00 */
1514 struct scu_afe_transceiver {
1515         /* 0x0000 AFE_XCVR_CTRL0 */
1516         u32 afe_xcvr_control0;
1517         /* 0x0004 AFE_XCVR_CTRL1 */
1518         u32 afe_xcvr_control1;
1519         /* 0x0008 */
1520         u32 reserved_0008;
1521         /* 0x000c afe_dfx_rx_control0 */
1522         u32 afe_dfx_rx_control0;
1523         /* 0x0010 AFE_DFX_RX_CTRL1 */
1524         u32 afe_dfx_rx_control1;
1525         /* 0x0014 */
1526         u32 reserved_0014;
1527         /* 0x0018 AFE_DFX_RX_STS0 */
1528         u32 afe_dfx_rx_status0;
1529         /* 0x001c AFE_DFX_RX_STS1 */
1530         u32 afe_dfx_rx_status1;
1531         /* 0x0020 */
1532         u32 reserved_0020;
1533         /* 0x0024 AFE_TX_CTRL */
1534         u32 afe_tx_control;
1535         /* 0x0028 AFE_TX_AMP_CTRL0 */
1536         u32 afe_tx_amp_control0;
1537         /* 0x002c AFE_TX_AMP_CTRL1 */
1538         u32 afe_tx_amp_control1;
1539         /* 0x0030 AFE_TX_AMP_CTRL2 */
1540         u32 afe_tx_amp_control2;
1541         /* 0x0034 AFE_TX_AMP_CTRL3 */
1542         u32 afe_tx_amp_control3;
1543         /* 0x0038 afe_tx_ssc_control */
1544         u32 afe_tx_ssc_control;
1545         /* 0x003c */
1546         u32 reserved_003c;
1547         /* 0x0040 AFE_RX_SSC_CTRL0 */
1548         u32 afe_rx_ssc_control0;
1549         /* 0x0044 AFE_RX_SSC_CTRL1 */
1550         u32 afe_rx_ssc_control1;
1551         /* 0x0048 AFE_RX_SSC_CTRL2 */
1552         u32 afe_rx_ssc_control2;
1553         /* 0x004c AFE_RX_EQ_STS0 */
1554         u32 afe_rx_eq_status0;
1555         /* 0x0050 AFE_RX_EQ_STS1 */
1556         u32 afe_rx_eq_status1;
1557         /* 0x0054 AFE_RX_CDR_STS */
1558         u32 afe_rx_cdr_status;
1559         /* 0x0058 */
1560         u32 reserved_0058;
1561         /* 0x005c AFE_CHAN_CTRL */
1562         u32 afe_channel_control;
1563         /* 0x0060-0x006c */
1564         u32 reserved_0060_006c[0x04];
1565         /* 0x0070 AFE_XCVR_EC_STS0 */
1566         u32 afe_xcvr_error_capture_status0;
1567         /* 0x0074 AFE_XCVR_EC_STS1 */
1568         u32 afe_xcvr_error_capture_status1;
1569         /* 0x0078 AFE_XCVR_EC_STS2 */
1570         u32 afe_xcvr_error_capture_status2;
1571         /* 0x007c afe_xcvr_ec_status3 */
1572         u32 afe_xcvr_error_capture_status3;
1573         /* 0x0080 AFE_XCVR_EC_STS4 */
1574         u32 afe_xcvr_error_capture_status4;
1575         /* 0x0084 AFE_XCVR_EC_STS5 */
1576         u32 afe_xcvr_error_capture_status5;
1577         /* 0x0088-0x00fc */
1578         u32 reserved_008c_00fc[0x1e];
1579 };
1580
1581 /**
1582  * struct scu_afe_registers - AFE Regsiters
1583  *
1584  *
1585  */
1586 /* Uaoa AFE registers */
1587 struct scu_afe_registers {
1588         /* 0Xe000 AFE_BIAS_CTRL */
1589         u32 afe_bias_control;
1590         u32 reserved_0004;
1591         /* 0x0008 AFE_PLL_CTRL0 */
1592         u32 afe_pll_control0;
1593         /* 0x000c AFE_PLL_CTRL1 */
1594         u32 afe_pll_control1;
1595         /* 0x0010 AFE_PLL_CTRL2 */
1596         u32 afe_pll_control2;
1597         /* 0x0014 AFE_CB_STS */
1598         u32 afe_common_block_status;
1599         /* 0x0018-0x007c */
1600         u32 reserved_18_7c[0x1a];
1601         /* 0x0080 AFE_PMSN_MCTRL0 */
1602         u32 afe_pmsn_master_control0;
1603         /* 0x0084 AFE_PMSN_MCTRL1 */
1604         u32 afe_pmsn_master_control1;
1605         /* 0x0088 AFE_PMSN_MCTRL2 */
1606         u32 afe_pmsn_master_control2;
1607         /* 0x008C-0x00fc */
1608         u32 reserved_008c_00fc[0x1D];
1609         /* 0x0100 AFE_DFX_MST_CTRL0 */
1610         u32 afe_dfx_master_control0;
1611         /* 0x0104 AFE_DFX_MST_CTRL1 */
1612         u32 afe_dfx_master_control1;
1613         /* 0x0108 AFE_DFX_DCL_CTRL */
1614         u32 afe_dfx_dcl_control;
1615         /* 0x010c AFE_DFX_DMON_CTRL */
1616         u32 afe_dfx_digital_monitor_control;
1617         /* 0x0110 AFE_DFX_AMONP_CTRL */
1618         u32 afe_dfx_analog_p_monitor_control;
1619         /* 0x0114 AFE_DFX_AMONN_CTRL */
1620         u32 afe_dfx_analog_n_monitor_control;
1621         /* 0x0118 AFE_DFX_NTL_STS */
1622         u32 afe_dfx_ntl_status;
1623         /* 0x011c AFE_DFX_FIFO_STS0 */
1624         u32 afe_dfx_fifo_status0;
1625         /* 0x0120 AFE_DFX_FIFO_STS1 */
1626         u32 afe_dfx_fifo_status1;
1627         /* 0x0124 AFE_DFX_MPAT_CTRL */
1628         u32 afe_dfx_master_pattern_control;
1629         /* 0x0128 AFE_DFX_P0_CTRL */
1630         u32 afe_dfx_p0_control;
1631         /* 0x012c-0x01a8 AFE_DFX_P0_DRx */
1632         u32 afe_dfx_p0_data[32];
1633         /* 0x01ac */
1634         u32 reserved_01ac;
1635         /* 0x01b0-0x020c AFE_DFX_P0_IRx */
1636         u32 afe_dfx_p0_instruction[24];
1637         /* 0x0210 */
1638         u32 reserved_0210;
1639         /* 0x0214 AFE_DFX_P1_CTRL */
1640         u32 afe_dfx_p1_control;
1641         /* 0x0218-0x245 AFE_DFX_P1_DRx */
1642         u32 afe_dfx_p1_data[16];
1643         /* 0x0258-0x029c */
1644         u32 reserved_0258_029c[0x12];
1645         /* 0x02a0-0x02bc AFE_DFX_P1_IRx */
1646         u32 afe_dfx_p1_instruction[8];
1647         /* 0x02c0-0x2fc */
1648         u32 reserved_02c0_02fc[0x10];
1649         /* 0x0300 AFE_DFX_TX_PMSN_CTRL */
1650         u32 afe_dfx_tx_pmsn_control;
1651         /* 0x0304 AFE_DFX_RX_PMSN_CTRL */
1652         u32 afe_dfx_rx_pmsn_control;
1653         u32 reserved_0308;
1654         /* 0x030c AFE_DFX_NOA_CTRL0 */
1655         u32 afe_dfx_noa_control0;
1656         /* 0x0310 AFE_DFX_NOA_CTRL1 */
1657         u32 afe_dfx_noa_control1;
1658         /* 0x0314 AFE_DFX_NOA_CTRL2 */
1659         u32 afe_dfx_noa_control2;
1660         /* 0x0318 AFE_DFX_NOA_CTRL3 */
1661         u32 afe_dfx_noa_control3;
1662         /* 0x031c AFE_DFX_NOA_CTRL4 */
1663         u32 afe_dfx_noa_control4;
1664         /* 0x0320 AFE_DFX_NOA_CTRL5 */
1665         u32 afe_dfx_noa_control5;
1666         /* 0x0324 AFE_DFX_NOA_CTRL6 */
1667         u32 afe_dfx_noa_control6;
1668         /* 0x0328 AFE_DFX_NOA_CTRL7 */
1669         u32 afe_dfx_noa_control7;
1670         /* 0x032c-0x07fc */
1671         u32 reserved_032c_07fc[0x135];
1672
1673         /* 0x0800-0x0bfc */
1674         struct scu_afe_transceiver scu_afe_xcvr[4];
1675
1676         /* 0x0c00-0x0ffc */
1677         u32 reserved_0c00_0ffc[0x0100];
1678 };
1679
1680 struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS {
1681         u32 table[0xE0];
1682 };
1683
1684
1685 struct SCU_VIIT_IIT {
1686         u32 table[256];
1687 };
1688
1689 /**
1690  * Placeholder for the ZONE Partition Table information ZONING will not be
1691  *    included in the 1.1 release.
1692  *
1693  *
1694  */
1695 struct SCU_ZONE_PARTITION_TABLE {
1696         u32 table[2048];
1697 };
1698
1699 /**
1700  * Placeholder for the CRAM register since I am not sure if we need to
1701  *    read/write to these registers as yet.
1702  *
1703  *
1704  */
1705 struct SCU_COMPLETION_RAM {
1706         u32 ram[128];
1707 };
1708
1709 /**
1710  * Placeholder for the FBRAM registers since I am not sure if we need to
1711  *    read/write to these registers as yet.
1712  *
1713  *
1714  */
1715 struct SCU_FRAME_BUFFER_RAM {
1716         u32 ram[128];
1717 };
1718
1719 #define SCU_SCRATCH_RAM_SIZE_IN_DWORDS  256
1720
1721 /**
1722  * Placeholder for the scratch RAM registers.
1723  *
1724  *
1725  */
1726 struct SCU_SCRATCH_RAM {
1727         u32 ram[SCU_SCRATCH_RAM_SIZE_IN_DWORDS];
1728 };
1729
1730 /**
1731  * Placeholder since I am not yet sure what these registers are here for.
1732  *
1733  *
1734  */
1735 struct NOA_PROTOCOL_ENGINE_PARTITION {
1736         u32 reserved[64];
1737 };
1738
1739 /**
1740  * Placeholder since I am not yet sure what these registers are here for.
1741  *
1742  *
1743  */
1744 struct NOA_HUB_PARTITION {
1745         u32 reserved[64];
1746 };
1747
1748 /**
1749  * Placeholder since I am not yet sure what these registers are here for.
1750  *
1751  *
1752  */
1753 struct NOA_HOST_INTERFACE_PARTITION {
1754         u32 reserved[64];
1755 };
1756
1757 /**
1758  * struct TRANSPORT_LINK_LAYER_PAIR - The SCU Hardware pairs up the TL
1759  *    registers with the LL registers so we must place them adjcent to make the
1760  *    array of registers in the PEG.
1761  *
1762  *
1763  */
1764 struct TRANSPORT_LINK_LAYER_PAIR {
1765         struct scu_transport_layer_registers tl;
1766         struct scu_link_layer_registers ll;
1767 };
1768
1769 /**
1770  * struct SCU_PEG_REGISTERS - SCU Protocol Engine Memory mapped register space.
1771  *     These registers are unique to each protocol engine group.  There can be
1772  *    at most two PEG for a single SCU part.
1773  *
1774  *
1775  */
1776 struct SCU_PEG_REGISTERS {
1777         struct TRANSPORT_LINK_LAYER_PAIR pe[4];
1778         struct scu_port_task_scheduler_group_registers ptsg;
1779         struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS peg;
1780         struct scu_sgpio_registers sgpio;
1781         u32 reserved_01500_1BFF[0x1C0];
1782         struct scu_viit_entry viit[64];
1783         struct SCU_ZONE_PARTITION_TABLE zpt0;
1784         struct SCU_ZONE_PARTITION_TABLE zpt1;
1785 };
1786
1787 /**
1788  * struct scu_registers - SCU regsiters including both PEG registers if we turn
1789  *    on that compile option. All of these registers are in the memory mapped
1790  *    space returned from BAR1.
1791  *
1792  *
1793  */
1794 struct scu_registers {
1795         /* 0x0000 - PEG 0 */
1796         struct SCU_PEG_REGISTERS peg0;
1797
1798         /* 0x6000 - SDMA and Miscellaneous */
1799         struct scu_sdma_registers sdma;
1800         struct SCU_COMPLETION_RAM cram;
1801         struct SCU_FRAME_BUFFER_RAM fbram;
1802         u32 reserved_6800_69FF[0x80];
1803         struct NOA_PROTOCOL_ENGINE_PARTITION noa_pe;
1804         struct NOA_HUB_PARTITION noa_hub;
1805         struct NOA_HOST_INTERFACE_PARTITION noa_if;
1806         u32 reserved_6d00_7fff[0x4c0];
1807
1808         /* 0x8000 - PEG 1 */
1809         struct SCU_PEG_REGISTERS peg1;
1810
1811         /* 0xE000 - AFE Registers */
1812         struct scu_afe_registers afe;
1813
1814         /* 0xF000 - reserved */
1815         u32 reserved_f000_211fff[0x80c00];
1816
1817         /* 0x212000 - scratch RAM */
1818         struct SCU_SCRATCH_RAM scratch_ram;
1819
1820 };
1821
1822
1823 #endif   /* _SCU_REGISTERS_HEADER_ */