2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2003-2012 LSI Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * FILE: megaraid_sas.h
22 * Authors: LSI Corporation
24 * Send feedback to: <megaraidlinux@lsi.com>
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
30 #ifndef LSI_MEGARAID_SAS_H
31 #define LSI_MEGARAID_SAS_H
34 * MegaRAID SAS Driver meta data
36 #define MEGASAS_VERSION "06.506.00.00-rc1"
37 #define MEGASAS_RELDATE "Feb. 9, 2013"
38 #define MEGASAS_EXT_VERSION "Sat. Feb. 9 17:00:00 PDT 2013"
43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
51 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
52 #define PCI_DEVICE_ID_LSI_FURY 0x005f
55 * =====================================
56 * MegaRAID SAS MFI firmware definitions
57 * =====================================
61 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
62 * protocol between the software and firmware. Commands are issued using
67 * FW posts its state in upper 4 bits of outbound_msg_0 register
69 #define MFI_STATE_MASK 0xF0000000
70 #define MFI_STATE_UNDEFINED 0x00000000
71 #define MFI_STATE_BB_INIT 0x10000000
72 #define MFI_STATE_FW_INIT 0x40000000
73 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
74 #define MFI_STATE_FW_INIT_2 0x70000000
75 #define MFI_STATE_DEVICE_SCAN 0x80000000
76 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
77 #define MFI_STATE_FLUSH_CACHE 0xA0000000
78 #define MFI_STATE_READY 0xB0000000
79 #define MFI_STATE_OPERATIONAL 0xC0000000
80 #define MFI_STATE_FAULT 0xF0000000
81 #define MFI_RESET_REQUIRED 0x00000001
82 #define MFI_RESET_ADAPTER 0x00000002
83 #define MEGAMFI_FRAME_SIZE 64
86 * During FW init, clear pending cmds & reset state using inbound_msg_0
88 * ABORT : Abort all pending cmds
89 * READY : Move from OPERATIONAL to READY state; discard queue info
90 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
91 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
92 * HOTPLUG : Resume from Hotplug
93 * MFI_STOP_ADP : Send signal to FW to stop processing
95 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
96 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
97 #define DIAG_WRITE_ENABLE (0x00000080)
98 #define DIAG_RESET_ADAPTER (0x00000004)
100 #define MFI_ADP_RESET 0x00000040
101 #define MFI_INIT_ABORT 0x00000001
102 #define MFI_INIT_READY 0x00000002
103 #define MFI_INIT_MFIMODE 0x00000004
104 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
105 #define MFI_INIT_HOTPLUG 0x00000010
106 #define MFI_STOP_ADP 0x00000020
107 #define MFI_RESET_FLAGS MFI_INIT_READY| \
114 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
115 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
116 #define MFI_FRAME_SGL32 0x0000
117 #define MFI_FRAME_SGL64 0x0002
118 #define MFI_FRAME_SENSE32 0x0000
119 #define MFI_FRAME_SENSE64 0x0004
120 #define MFI_FRAME_DIR_NONE 0x0000
121 #define MFI_FRAME_DIR_WRITE 0x0008
122 #define MFI_FRAME_DIR_READ 0x0010
123 #define MFI_FRAME_DIR_BOTH 0x0018
124 #define MFI_FRAME_IEEE 0x0020
127 * Definition for cmd_status
129 #define MFI_CMD_STATUS_POLL_MODE 0xFF
132 * MFI command opcodes
134 #define MFI_CMD_INIT 0x00
135 #define MFI_CMD_LD_READ 0x01
136 #define MFI_CMD_LD_WRITE 0x02
137 #define MFI_CMD_LD_SCSI_IO 0x03
138 #define MFI_CMD_PD_SCSI_IO 0x04
139 #define MFI_CMD_DCMD 0x05
140 #define MFI_CMD_ABORT 0x06
141 #define MFI_CMD_SMP 0x07
142 #define MFI_CMD_STP 0x08
143 #define MFI_CMD_INVALID 0xff
145 #define MR_DCMD_CTRL_GET_INFO 0x01010000
146 #define MR_DCMD_LD_GET_LIST 0x03010000
148 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
149 #define MR_FLUSH_CTRL_CACHE 0x01
150 #define MR_FLUSH_DISK_CACHE 0x02
152 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
153 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
154 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
156 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
157 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
158 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
159 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
161 #define MR_DCMD_CLUSTER 0x08000000
162 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
163 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
164 #define MR_DCMD_PD_LIST_QUERY 0x02010100
167 * MFI command completion codes
171 MFI_STAT_INVALID_CMD
= 0x01,
172 MFI_STAT_INVALID_DCMD
= 0x02,
173 MFI_STAT_INVALID_PARAMETER
= 0x03,
174 MFI_STAT_INVALID_SEQUENCE_NUMBER
= 0x04,
175 MFI_STAT_ABORT_NOT_POSSIBLE
= 0x05,
176 MFI_STAT_APP_HOST_CODE_NOT_FOUND
= 0x06,
177 MFI_STAT_APP_IN_USE
= 0x07,
178 MFI_STAT_APP_NOT_INITIALIZED
= 0x08,
179 MFI_STAT_ARRAY_INDEX_INVALID
= 0x09,
180 MFI_STAT_ARRAY_ROW_NOT_EMPTY
= 0x0a,
181 MFI_STAT_CONFIG_RESOURCE_CONFLICT
= 0x0b,
182 MFI_STAT_DEVICE_NOT_FOUND
= 0x0c,
183 MFI_STAT_DRIVE_TOO_SMALL
= 0x0d,
184 MFI_STAT_FLASH_ALLOC_FAIL
= 0x0e,
185 MFI_STAT_FLASH_BUSY
= 0x0f,
186 MFI_STAT_FLASH_ERROR
= 0x10,
187 MFI_STAT_FLASH_IMAGE_BAD
= 0x11,
188 MFI_STAT_FLASH_IMAGE_INCOMPLETE
= 0x12,
189 MFI_STAT_FLASH_NOT_OPEN
= 0x13,
190 MFI_STAT_FLASH_NOT_STARTED
= 0x14,
191 MFI_STAT_FLUSH_FAILED
= 0x15,
192 MFI_STAT_HOST_CODE_NOT_FOUNT
= 0x16,
193 MFI_STAT_LD_CC_IN_PROGRESS
= 0x17,
194 MFI_STAT_LD_INIT_IN_PROGRESS
= 0x18,
195 MFI_STAT_LD_LBA_OUT_OF_RANGE
= 0x19,
196 MFI_STAT_LD_MAX_CONFIGURED
= 0x1a,
197 MFI_STAT_LD_NOT_OPTIMAL
= 0x1b,
198 MFI_STAT_LD_RBLD_IN_PROGRESS
= 0x1c,
199 MFI_STAT_LD_RECON_IN_PROGRESS
= 0x1d,
200 MFI_STAT_LD_WRONG_RAID_LEVEL
= 0x1e,
201 MFI_STAT_MAX_SPARES_EXCEEDED
= 0x1f,
202 MFI_STAT_MEMORY_NOT_AVAILABLE
= 0x20,
203 MFI_STAT_MFC_HW_ERROR
= 0x21,
204 MFI_STAT_NO_HW_PRESENT
= 0x22,
205 MFI_STAT_NOT_FOUND
= 0x23,
206 MFI_STAT_NOT_IN_ENCL
= 0x24,
207 MFI_STAT_PD_CLEAR_IN_PROGRESS
= 0x25,
208 MFI_STAT_PD_TYPE_WRONG
= 0x26,
209 MFI_STAT_PR_DISABLED
= 0x27,
210 MFI_STAT_ROW_INDEX_INVALID
= 0x28,
211 MFI_STAT_SAS_CONFIG_INVALID_ACTION
= 0x29,
212 MFI_STAT_SAS_CONFIG_INVALID_DATA
= 0x2a,
213 MFI_STAT_SAS_CONFIG_INVALID_PAGE
= 0x2b,
214 MFI_STAT_SAS_CONFIG_INVALID_TYPE
= 0x2c,
215 MFI_STAT_SCSI_DONE_WITH_ERROR
= 0x2d,
216 MFI_STAT_SCSI_IO_FAILED
= 0x2e,
217 MFI_STAT_SCSI_RESERVATION_CONFLICT
= 0x2f,
218 MFI_STAT_SHUTDOWN_FAILED
= 0x30,
219 MFI_STAT_TIME_NOT_SET
= 0x31,
220 MFI_STAT_WRONG_STATE
= 0x32,
221 MFI_STAT_LD_OFFLINE
= 0x33,
222 MFI_STAT_PEER_NOTIFICATION_REJECTED
= 0x34,
223 MFI_STAT_PEER_NOTIFICATION_FAILED
= 0x35,
224 MFI_STAT_RESERVATION_IN_PROGRESS
= 0x36,
225 MFI_STAT_I2C_ERRORS_DETECTED
= 0x37,
226 MFI_STAT_PCI_ERRORS_DETECTED
= 0x38,
227 MFI_STAT_CONFIG_SEQ_MISMATCH
= 0x67,
229 MFI_STAT_INVALID_STATUS
= 0xFF
233 * Number of mailbox bytes in DCMD message frame
235 #define MFI_MBOX_SIZE 12
239 MR_EVT_CLASS_DEBUG
= -2,
240 MR_EVT_CLASS_PROGRESS
= -1,
241 MR_EVT_CLASS_INFO
= 0,
242 MR_EVT_CLASS_WARNING
= 1,
243 MR_EVT_CLASS_CRITICAL
= 2,
244 MR_EVT_CLASS_FATAL
= 3,
245 MR_EVT_CLASS_DEAD
= 4,
251 MR_EVT_LOCALE_LD
= 0x0001,
252 MR_EVT_LOCALE_PD
= 0x0002,
253 MR_EVT_LOCALE_ENCL
= 0x0004,
254 MR_EVT_LOCALE_BBU
= 0x0008,
255 MR_EVT_LOCALE_SAS
= 0x0010,
256 MR_EVT_LOCALE_CTRL
= 0x0020,
257 MR_EVT_LOCALE_CONFIG
= 0x0040,
258 MR_EVT_LOCALE_CLUSTER
= 0x0080,
259 MR_EVT_LOCALE_ALL
= 0xffff,
266 MR_EVT_ARGS_CDB_SENSE
,
268 MR_EVT_ARGS_LD_COUNT
,
270 MR_EVT_ARGS_LD_OWNER
,
271 MR_EVT_ARGS_LD_LBA_PD_LBA
,
273 MR_EVT_ARGS_LD_STATE
,
274 MR_EVT_ARGS_LD_STRIP
,
278 MR_EVT_ARGS_PD_LBA_LD
,
280 MR_EVT_ARGS_PD_STATE
,
287 MR_EVT_ARGS_PD_SPARE
,
288 MR_EVT_ARGS_PD_INDEX
,
289 MR_EVT_ARGS_DIAG_PASS
,
290 MR_EVT_ARGS_DIAG_FAIL
,
291 MR_EVT_ARGS_PD_LBA_LBA
,
292 MR_EVT_ARGS_PORT_PHY
,
293 MR_EVT_ARGS_PD_MISSING
,
294 MR_EVT_ARGS_PD_ADDRESS
,
296 MR_EVT_ARGS_CONNECTOR
,
299 MR_EVT_ARGS_PD_PATHINFO
,
300 MR_EVT_ARGS_PD_POWER_STATE
,
305 * define constants for device list query options
307 enum MR_PD_QUERY_TYPE
{
308 MR_PD_QUERY_TYPE_ALL
= 0,
309 MR_PD_QUERY_TYPE_STATE
= 1,
310 MR_PD_QUERY_TYPE_POWER_STATE
= 2,
311 MR_PD_QUERY_TYPE_MEDIA_TYPE
= 3,
312 MR_PD_QUERY_TYPE_SPEED
= 4,
313 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST
= 5,
316 #define MR_EVT_CFG_CLEARED 0x0004
317 #define MR_EVT_LD_STATE_CHANGE 0x0051
318 #define MR_EVT_PD_INSERTED 0x005b
319 #define MR_EVT_PD_REMOVED 0x0070
320 #define MR_EVT_LD_CREATED 0x008a
321 #define MR_EVT_LD_DELETED 0x008b
322 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
323 #define MR_EVT_LD_OFFLINE 0x00fc
324 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
325 #define MAX_LOGICAL_DRIVES 64
328 MR_PD_STATE_UNCONFIGURED_GOOD
= 0x00,
329 MR_PD_STATE_UNCONFIGURED_BAD
= 0x01,
330 MR_PD_STATE_HOT_SPARE
= 0x02,
331 MR_PD_STATE_OFFLINE
= 0x10,
332 MR_PD_STATE_FAILED
= 0x11,
333 MR_PD_STATE_REBUILD
= 0x14,
334 MR_PD_STATE_ONLINE
= 0x18,
335 MR_PD_STATE_COPYBACK
= 0x20,
336 MR_PD_STATE_SYSTEM
= 0x40,
341 * defines the physical drive address structure
343 struct MR_PD_ADDRESS
{
354 u8 enclConnectorIndex
;
359 u8 connectedPortBitmap
;
360 u8 connectedPortNumbers
;
366 * defines the physical drive list structure
371 struct MR_PD_ADDRESS addr
[1];
374 struct megasas_pd_list
{
381 * defines the logical drive reference structure
393 * defines the logical drive list structure
403 } ldList
[MAX_LOGICAL_DRIVES
];
407 * SAS controller properties
409 struct megasas_ctrl_prop
{
412 u16 pred_fail_poll_interval
;
413 u16 intr_throttle_count
;
414 u16 intr_throttle_timeouts
;
420 u8 cache_flush_interval
;
426 u8 disable_auto_rebuild
;
427 u8 disable_battery_warn
;
429 u16 ecc_bucket_leak_rate
;
430 u8 restore_hotspare_on_insertion
;
431 u8 expose_encl_devices
;
432 u8 maintainPdFailHistory
;
433 u8 disallowHostRequestReordering
;
436 u8 disableAutoDetectBackplane
;
441 * Add properties that can be controlled by
442 * a bit in the following structure.
445 u32 copyBackDisabled
: 1;
446 u32 SMARTerEnabled
: 1;
447 u32 prCorrectUnconfiguredAreas
: 1;
450 u32 SSDSMARTerEnabled
: 1;
451 u32 SSDPatrolReadEnabled
: 1;
452 u32 enableSpinDownUnconfigured
: 1;
453 u32 autoEnhancedImport
: 1;
454 u32 enableSecretKeyControl
: 1;
455 u32 disableOnlineCtrlReset
: 1;
456 u32 allowBootWithPinnedCache
: 1;
457 u32 disableSpinDownHS
: 1;
468 * SAS controller information
470 struct megasas_ctrl_info
{
473 * PCI device information
483 } __attribute__ ((packed
)) pci
;
486 * Host interface information
499 } __attribute__ ((packed
)) host_interface
;
502 * Device (backend) interface information
515 } __attribute__ ((packed
)) device_interface
;
518 * List of components residing in flash. All str are null terminated
520 u32 image_check_word
;
521 u32 image_component_count
;
530 } __attribute__ ((packed
)) image_component
[8];
533 * List of flash components that have been flashed on the card, but
534 * are not in use, pending reset of the adapter. This list will be
535 * empty if a flash operation has not occurred. All stings are null
538 u32 pending_image_component_count
;
547 } __attribute__ ((packed
)) pending_image_component
[8];
554 char product_name
[80];
558 * Other physical/controller/operation information. Indicates the
559 * presence of the hardware
569 } __attribute__ ((packed
)) hw_present
;
574 * Maximum data transfer sizes
576 u16 max_concurrent_cmds
;
578 u32 max_request_size
;
581 * Logical and physical device counts
583 u16 ld_present_count
;
584 u16 ld_degraded_count
;
585 u16 ld_offline_count
;
587 u16 pd_present_count
;
588 u16 pd_disk_present_count
;
589 u16 pd_disk_pred_failure_count
;
590 u16 pd_disk_failed_count
;
593 * Memory size information
602 u16 mem_correctable_error_count
;
603 u16 mem_uncorrectable_error_count
;
606 * Cluster information
608 u8 cluster_permitted
;
612 * Additional max data transfer sizes
614 u16 max_strips_per_io
;
617 * Controller capabilities structures
628 } __attribute__ ((packed
)) raid_levels
;
638 u32 cluster_supported
:1;
640 u32 spanning_allowed
:1;
641 u32 dedicated_hotspares
:1;
642 u32 revertible_hotspares
:1;
643 u32 foreign_config_import
:1;
644 u32 self_diagnostic
:1;
645 u32 mixed_redundancy_arr
:1;
646 u32 global_hot_spares
:1;
649 } __attribute__ ((packed
)) adapter_operations
;
657 u32 disk_cache_policy
:1;
660 } __attribute__ ((packed
)) ld_operations
;
668 } __attribute__ ((packed
)) stripe_sz_ops
;
677 } __attribute__ ((packed
)) pd_operations
;
681 u32 ctrl_supports_sas
:1;
682 u32 ctrl_supports_sata
:1;
683 u32 allow_mix_in_encl
:1;
684 u32 allow_mix_in_ld
:1;
685 u32 allow_sata_in_cluster
:1;
688 } __attribute__ ((packed
)) pd_mix_support
;
691 * Define ECC single-bit-error bucket information
697 * Include the controller properties (changeable items)
699 struct megasas_ctrl_prop properties
;
702 * Define FW pkg version (set in envt v'bles on OEM basis)
704 char package_version
[0x60];
706 u8 pad
[0x800 - 0x6a0];
711 * ===============================
712 * MegaRAID SAS driver definitions
713 * ===============================
715 #define MEGASAS_MAX_PD_CHANNELS 2
716 #define MEGASAS_MAX_LD_CHANNELS 2
717 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
718 MEGASAS_MAX_LD_CHANNELS)
719 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
720 #define MEGASAS_DEFAULT_INIT_ID -1
721 #define MEGASAS_MAX_LUN 8
722 #define MEGASAS_MAX_LD 64
723 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
724 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
725 MEGASAS_MAX_DEV_PER_CHANNEL)
726 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
727 MEGASAS_MAX_DEV_PER_CHANNEL)
729 #define MEGASAS_MAX_SECTORS (2*1024)
730 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
731 #define MEGASAS_DBG_LVL 1
733 #define MEGASAS_FW_BUSY 1
737 #define PTHRU_FRAME 1
740 * When SCSI mid-layer calls driver's reset routine, driver waits for
741 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
742 * that the driver cannot _actually_ abort or reset pending commands. While
743 * it is waiting for the commands to complete, it prints a diagnostic message
744 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
746 #define MEGASAS_RESET_WAIT_TIME 180
747 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
748 #define MEGASAS_RESET_NOTICE_INTERVAL 5
749 #define MEGASAS_IOCTL_CMD 0
750 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
751 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
754 * FW reports the maximum of number of commands that it can accept (maximum
755 * commands that can be outstanding) at any time. The driver must report a
756 * lower number to the mid layer because it can issue a few internal commands
757 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
760 #define MEGASAS_INT_CMDS 32
761 #define MEGASAS_SKINNY_INT_CMDS 5
763 #define MEGASAS_MAX_MSIX_QUEUES 16
765 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
766 * SGLs based on the size of dma_addr_t
768 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
770 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
772 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
773 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
774 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
776 #define MFI_OB_INTR_STATUS_MASK 0x00000002
777 #define MFI_POLL_TIMEOUT_SECS 60
779 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
780 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
781 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
782 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
783 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
785 #define MFI_1068_PCSR_OFFSET 0x84
786 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
787 #define MFI_1068_FW_READY 0xDDDD0000
789 * register set for both 1068 and 1078 controllers
790 * structure extended for 1078 registers
793 struct megasas_register_set
{
794 u32 doorbell
; /*0000h*/
795 u32 fusion_seq_offset
; /*0004h*/
796 u32 fusion_host_diag
; /*0008h*/
797 u32 reserved_01
; /*000Ch*/
799 u32 inbound_msg_0
; /*0010h*/
800 u32 inbound_msg_1
; /*0014h*/
801 u32 outbound_msg_0
; /*0018h*/
802 u32 outbound_msg_1
; /*001Ch*/
804 u32 inbound_doorbell
; /*0020h*/
805 u32 inbound_intr_status
; /*0024h*/
806 u32 inbound_intr_mask
; /*0028h*/
808 u32 outbound_doorbell
; /*002Ch*/
809 u32 outbound_intr_status
; /*0030h*/
810 u32 outbound_intr_mask
; /*0034h*/
812 u32 reserved_1
[2]; /*0038h*/
814 u32 inbound_queue_port
; /*0040h*/
815 u32 outbound_queue_port
; /*0044h*/
817 u32 reserved_2
[9]; /*0048h*/
818 u32 reply_post_host_index
; /*006Ch*/
819 u32 reserved_2_2
[12]; /*0070h*/
821 u32 outbound_doorbell_clear
; /*00A0h*/
823 u32 reserved_3
[3]; /*00A4h*/
825 u32 outbound_scratch_pad
; /*00B0h*/
826 u32 outbound_scratch_pad_2
; /*00B4h*/
828 u32 reserved_4
[2]; /*00B8h*/
830 u32 inbound_low_queue_port
; /*00C0h*/
832 u32 inbound_high_queue_port
; /*00C4h*/
834 u32 reserved_5
; /*00C8h*/
835 u32 res_6
[11]; /*CCh*/
838 u32 index_registers
[807]; /*00CCh*/
839 } __attribute__ ((packed
));
841 struct megasas_sge32
{
846 } __attribute__ ((packed
));
848 struct megasas_sge64
{
853 } __attribute__ ((packed
));
855 struct megasas_sge_skinny
{
863 struct megasas_sge32 sge32
[1];
864 struct megasas_sge64 sge64
[1];
865 struct megasas_sge_skinny sge_skinny
[1];
867 } __attribute__ ((packed
));
869 struct megasas_header
{
872 u8 sense_len
; /*01h */
873 u8 cmd_status
; /*02h */
874 u8 scsi_status
; /*03h */
876 u8 target_id
; /*04h */
879 u8 sge_count
; /*07h */
881 u32 context
; /*08h */
885 u16 timeout
; /*12h */
886 u32 data_xferlen
; /*14h */
888 } __attribute__ ((packed
));
890 union megasas_sgl_frame
{
892 struct megasas_sge32 sge32
[8];
893 struct megasas_sge64 sge64
[5];
895 } __attribute__ ((packed
));
897 struct megasas_init_frame
{
900 u8 reserved_0
; /*01h */
901 u8 cmd_status
; /*02h */
903 u8 reserved_1
; /*03h */
904 u32 reserved_2
; /*04h */
906 u32 context
; /*08h */
910 u16 reserved_3
; /*12h */
911 u32 data_xfer_len
; /*14h */
913 u32 queue_info_new_phys_addr_lo
; /*18h */
914 u32 queue_info_new_phys_addr_hi
; /*1Ch */
915 u32 queue_info_old_phys_addr_lo
; /*20h */
916 u32 queue_info_old_phys_addr_hi
; /*24h */
918 u32 reserved_4
[6]; /*28h */
920 } __attribute__ ((packed
));
922 struct megasas_init_queue_info
{
924 u32 init_flags
; /*00h */
925 u32 reply_queue_entries
; /*04h */
927 u32 reply_queue_start_phys_addr_lo
; /*08h */
928 u32 reply_queue_start_phys_addr_hi
; /*0Ch */
929 u32 producer_index_phys_addr_lo
; /*10h */
930 u32 producer_index_phys_addr_hi
; /*14h */
931 u32 consumer_index_phys_addr_lo
; /*18h */
932 u32 consumer_index_phys_addr_hi
; /*1Ch */
934 } __attribute__ ((packed
));
936 struct megasas_io_frame
{
939 u8 sense_len
; /*01h */
940 u8 cmd_status
; /*02h */
941 u8 scsi_status
; /*03h */
943 u8 target_id
; /*04h */
944 u8 access_byte
; /*05h */
945 u8 reserved_0
; /*06h */
946 u8 sge_count
; /*07h */
948 u32 context
; /*08h */
952 u16 timeout
; /*12h */
953 u32 lba_count
; /*14h */
955 u32 sense_buf_phys_addr_lo
; /*18h */
956 u32 sense_buf_phys_addr_hi
; /*1Ch */
958 u32 start_lba_lo
; /*20h */
959 u32 start_lba_hi
; /*24h */
961 union megasas_sgl sgl
; /*28h */
963 } __attribute__ ((packed
));
965 struct megasas_pthru_frame
{
968 u8 sense_len
; /*01h */
969 u8 cmd_status
; /*02h */
970 u8 scsi_status
; /*03h */
972 u8 target_id
; /*04h */
975 u8 sge_count
; /*07h */
977 u32 context
; /*08h */
981 u16 timeout
; /*12h */
982 u32 data_xfer_len
; /*14h */
984 u32 sense_buf_phys_addr_lo
; /*18h */
985 u32 sense_buf_phys_addr_hi
; /*1Ch */
988 union megasas_sgl sgl
; /*30h */
990 } __attribute__ ((packed
));
992 struct megasas_dcmd_frame
{
995 u8 reserved_0
; /*01h */
996 u8 cmd_status
; /*02h */
997 u8 reserved_1
[4]; /*03h */
998 u8 sge_count
; /*07h */
1000 u32 context
; /*08h */
1004 u16 timeout
; /*12h */
1006 u32 data_xfer_len
; /*14h */
1007 u32 opcode
; /*18h */
1015 union megasas_sgl sgl
; /*28h */
1017 } __attribute__ ((packed
));
1019 struct megasas_abort_frame
{
1022 u8 reserved_0
; /*01h */
1023 u8 cmd_status
; /*02h */
1025 u8 reserved_1
; /*03h */
1026 u32 reserved_2
; /*04h */
1028 u32 context
; /*08h */
1032 u16 reserved_3
; /*12h */
1033 u32 reserved_4
; /*14h */
1035 u32 abort_context
; /*18h */
1038 u32 abort_mfi_phys_addr_lo
; /*20h */
1039 u32 abort_mfi_phys_addr_hi
; /*24h */
1041 u32 reserved_5
[6]; /*28h */
1043 } __attribute__ ((packed
));
1045 struct megasas_smp_frame
{
1048 u8 reserved_1
; /*01h */
1049 u8 cmd_status
; /*02h */
1050 u8 connection_status
; /*03h */
1052 u8 reserved_2
[3]; /*04h */
1053 u8 sge_count
; /*07h */
1055 u32 context
; /*08h */
1059 u16 timeout
; /*12h */
1061 u32 data_xfer_len
; /*14h */
1062 u64 sas_addr
; /*18h */
1065 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: req */
1066 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: req */
1069 } __attribute__ ((packed
));
1071 struct megasas_stp_frame
{
1074 u8 reserved_1
; /*01h */
1075 u8 cmd_status
; /*02h */
1076 u8 reserved_2
; /*03h */
1078 u8 target_id
; /*04h */
1079 u8 reserved_3
[2]; /*05h */
1080 u8 sge_count
; /*07h */
1082 u32 context
; /*08h */
1086 u16 timeout
; /*12h */
1088 u32 data_xfer_len
; /*14h */
1090 u16 fis
[10]; /*18h */
1094 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: data */
1095 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: data */
1098 } __attribute__ ((packed
));
1100 union megasas_frame
{
1102 struct megasas_header hdr
;
1103 struct megasas_init_frame init
;
1104 struct megasas_io_frame io
;
1105 struct megasas_pthru_frame pthru
;
1106 struct megasas_dcmd_frame dcmd
;
1107 struct megasas_abort_frame abort
;
1108 struct megasas_smp_frame smp
;
1109 struct megasas_stp_frame stp
;
1116 union megasas_evt_class_locale
{
1122 } __attribute__ ((packed
)) members
;
1126 } __attribute__ ((packed
));
1128 struct megasas_evt_log_info
{
1132 u32 shutdown_seq_num
;
1135 } __attribute__ ((packed
));
1137 struct megasas_progress
{
1140 u16 elapsed_seconds
;
1142 } __attribute__ ((packed
));
1144 struct megasas_evtarg_ld
{
1150 } __attribute__ ((packed
));
1152 struct megasas_evtarg_pd
{
1157 } __attribute__ ((packed
));
1159 struct megasas_evt_detail
{
1164 union megasas_evt_class_locale cl
;
1170 struct megasas_evtarg_pd pd
;
1176 } __attribute__ ((packed
)) cdbSense
;
1178 struct megasas_evtarg_ld ld
;
1181 struct megasas_evtarg_ld ld
;
1183 } __attribute__ ((packed
)) ld_count
;
1187 struct megasas_evtarg_ld ld
;
1188 } __attribute__ ((packed
)) ld_lba
;
1191 struct megasas_evtarg_ld ld
;
1194 } __attribute__ ((packed
)) ld_owner
;
1199 struct megasas_evtarg_ld ld
;
1200 struct megasas_evtarg_pd pd
;
1201 } __attribute__ ((packed
)) ld_lba_pd_lba
;
1204 struct megasas_evtarg_ld ld
;
1205 struct megasas_progress prog
;
1206 } __attribute__ ((packed
)) ld_prog
;
1209 struct megasas_evtarg_ld ld
;
1212 } __attribute__ ((packed
)) ld_state
;
1216 struct megasas_evtarg_ld ld
;
1217 } __attribute__ ((packed
)) ld_strip
;
1219 struct megasas_evtarg_pd pd
;
1222 struct megasas_evtarg_pd pd
;
1224 } __attribute__ ((packed
)) pd_err
;
1228 struct megasas_evtarg_pd pd
;
1229 } __attribute__ ((packed
)) pd_lba
;
1233 struct megasas_evtarg_pd pd
;
1234 struct megasas_evtarg_ld ld
;
1235 } __attribute__ ((packed
)) pd_lba_ld
;
1238 struct megasas_evtarg_pd pd
;
1239 struct megasas_progress prog
;
1240 } __attribute__ ((packed
)) pd_prog
;
1243 struct megasas_evtarg_pd pd
;
1246 } __attribute__ ((packed
)) pd_state
;
1253 } __attribute__ ((packed
)) pci
;
1261 } __attribute__ ((packed
)) time
;
1267 } __attribute__ ((packed
)) ecc
;
1275 char description
[128];
1277 } __attribute__ ((packed
));
1279 struct megasas_aen_event
{
1280 struct delayed_work hotplug_work
;
1281 struct megasas_instance
*instance
;
1284 struct megasas_irq_context
{
1285 struct megasas_instance
*instance
;
1289 struct megasas_instance
{
1292 dma_addr_t producer_h
;
1294 dma_addr_t consumer_h
;
1297 dma_addr_t reply_queue_h
;
1299 unsigned long base_addr
;
1300 struct megasas_register_set __iomem
*reg_set
;
1302 struct megasas_pd_list pd_list
[MEGASAS_MAX_PD
];
1303 u8 ld_ids
[MEGASAS_MAX_LD_IDS
];
1308 /* For Fusion its num IOCTL cmds, for others MFI based its
1311 u32 max_sectors_per_req
;
1312 struct megasas_aen_event
*ev
;
1314 struct megasas_cmd
**cmd_list
;
1315 struct list_head cmd_pool
;
1316 /* used to sync fire the cmd to fw */
1317 spinlock_t cmd_pool_lock
;
1318 /* used to sync fire the cmd to fw */
1319 spinlock_t hba_lock
;
1320 /* used to synch producer, consumer ptrs in dpc */
1321 spinlock_t completion_lock
;
1322 struct dma_pool
*frame_dma_pool
;
1323 struct dma_pool
*sense_dma_pool
;
1325 struct megasas_evt_detail
*evt_detail
;
1326 dma_addr_t evt_detail_h
;
1327 struct megasas_cmd
*aen_cmd
;
1328 struct mutex aen_mutex
;
1329 struct semaphore ioctl_sem
;
1331 struct Scsi_Host
*host
;
1333 wait_queue_head_t int_cmd_wait_q
;
1334 wait_queue_head_t abort_cmd_wait_q
;
1336 struct pci_dev
*pdev
;
1338 u32 fw_support_ieee
;
1340 atomic_t fw_outstanding
;
1341 atomic_t fw_reset_no_pci_access
;
1343 struct megasas_instance_template
*instancet
;
1344 struct tasklet_struct isr_tasklet
;
1345 struct work_struct work_init
;
1351 u8 disableOnlineCtrlReset
;
1353 unsigned long last_time
;
1357 struct list_head internal_reset_pending_q
;
1359 /* Ptr to hba specific information */
1361 unsigned int msix_vectors
;
1362 struct msix_entry msixentry
[MEGASAS_MAX_MSIX_QUEUES
];
1363 struct megasas_irq_context irq_context
[MEGASAS_MAX_MSIX_QUEUES
];
1365 struct megasas_cmd
*map_update_cmd
;
1368 struct mutex reset_mutex
;
1369 int throttlequeuedepth
;
1373 MEGASAS_HBA_OPERATIONAL
= 0,
1374 MEGASAS_ADPRESET_SM_INFAULT
= 1,
1375 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS
= 2,
1376 MEGASAS_ADPRESET_SM_OPERATIONAL
= 3,
1377 MEGASAS_HW_CRITICAL_ERROR
= 4,
1378 MEGASAS_ADPRESET_INPROG_SIGN
= 0xDEADDEAD,
1381 struct megasas_instance_template
{
1382 void (*fire_cmd
)(struct megasas_instance
*, dma_addr_t
, \
1383 u32
, struct megasas_register_set __iomem
*);
1385 void (*enable_intr
)(struct megasas_register_set __iomem
*) ;
1386 void (*disable_intr
)(struct megasas_register_set __iomem
*);
1388 int (*clear_intr
)(struct megasas_register_set __iomem
*);
1390 u32 (*read_fw_status_reg
)(struct megasas_register_set __iomem
*);
1391 int (*adp_reset
)(struct megasas_instance
*, \
1392 struct megasas_register_set __iomem
*);
1393 int (*check_reset
)(struct megasas_instance
*, \
1394 struct megasas_register_set __iomem
*);
1395 irqreturn_t (*service_isr
)(int irq
, void *devp
);
1396 void (*tasklet
)(unsigned long);
1397 u32 (*init_adapter
)(struct megasas_instance
*);
1398 u32 (*build_and_issue_cmd
) (struct megasas_instance
*,
1399 struct scsi_cmnd
*);
1400 void (*issue_dcmd
) (struct megasas_instance
*instance
,
1401 struct megasas_cmd
*cmd
);
1404 #define MEGASAS_IS_LOGICAL(scp) \
1405 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1407 #define MEGASAS_DEV_INDEX(inst, scp) \
1408 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1411 struct megasas_cmd
{
1413 union megasas_frame
*frame
;
1414 dma_addr_t frame_phys_addr
;
1416 dma_addr_t sense_phys_addr
;
1422 u8 retry_for_fw_reset
;
1425 struct list_head list
;
1426 struct scsi_cmnd
*scmd
;
1427 struct megasas_instance
*instance
;
1437 #define MAX_MGMT_ADAPTERS 1024
1438 #define MAX_IOCTL_SGE 16
1440 struct megasas_iocpacket
{
1450 struct megasas_header hdr
;
1453 struct iovec sgl
[MAX_IOCTL_SGE
];
1455 } __attribute__ ((packed
));
1457 struct megasas_aen
{
1461 u32 class_locale_word
;
1462 } __attribute__ ((packed
));
1464 #ifdef CONFIG_COMPAT
1465 struct compat_megasas_iocpacket
{
1474 struct megasas_header hdr
;
1476 struct compat_iovec sgl
[MAX_IOCTL_SGE
];
1477 } __attribute__ ((packed
));
1479 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1482 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1483 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1485 struct megasas_mgmt_info
{
1488 struct megasas_instance
*instance
[MAX_MGMT_ADAPTERS
];
1492 #endif /*LSI_MEGARAID_SAS_H */