2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2003-2012 LSI Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * FILE: megaraid_sas.h
22 * Authors: LSI Corporation
24 * Send feedback to: <megaraidlinux@lsi.com>
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
30 #ifndef LSI_MEGARAID_SAS_H
31 #define LSI_MEGARAID_SAS_H
34 * MegaRAID SAS Driver meta data
36 #define MEGASAS_VERSION "06.600.18.00-rc1"
37 #define MEGASAS_RELDATE "May. 15, 2013"
38 #define MEGASAS_EXT_VERSION "Wed. May. 15 17:00:00 PDT 2013"
43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
51 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
52 #define PCI_DEVICE_ID_LSI_FURY 0x005f
57 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
58 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
59 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
60 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
61 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
62 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
67 #define MEGARAID_INTEL_RS3DC080_BRANDING \
68 "Intel(R) RAID Controller RS3DC080"
69 #define MEGARAID_INTEL_RS3DC040_BRANDING \
70 "Intel(R) RAID Controller RS3DC040"
71 #define MEGARAID_INTEL_RS3SC008_BRANDING \
72 "Intel(R) RAID Controller RS3SC008"
73 #define MEGARAID_INTEL_RS3MC044_BRANDING \
74 "Intel(R) RAID Controller RS3MC044"
75 #define MEGARAID_INTEL_RS3WC080_BRANDING \
76 "Intel(R) RAID Controller RS3WC080"
77 #define MEGARAID_INTEL_RS3WC040_BRANDING \
78 "Intel(R) RAID Controller RS3WC040"
81 * =====================================
82 * MegaRAID SAS MFI firmware definitions
83 * =====================================
87 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
88 * protocol between the software and firmware. Commands are issued using
93 * FW posts its state in upper 4 bits of outbound_msg_0 register
95 #define MFI_STATE_MASK 0xF0000000
96 #define MFI_STATE_UNDEFINED 0x00000000
97 #define MFI_STATE_BB_INIT 0x10000000
98 #define MFI_STATE_FW_INIT 0x40000000
99 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
100 #define MFI_STATE_FW_INIT_2 0x70000000
101 #define MFI_STATE_DEVICE_SCAN 0x80000000
102 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
103 #define MFI_STATE_FLUSH_CACHE 0xA0000000
104 #define MFI_STATE_READY 0xB0000000
105 #define MFI_STATE_OPERATIONAL 0xC0000000
106 #define MFI_STATE_FAULT 0xF0000000
107 #define MFI_RESET_REQUIRED 0x00000001
108 #define MFI_RESET_ADAPTER 0x00000002
109 #define MEGAMFI_FRAME_SIZE 64
112 * During FW init, clear pending cmds & reset state using inbound_msg_0
114 * ABORT : Abort all pending cmds
115 * READY : Move from OPERATIONAL to READY state; discard queue info
116 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
117 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
118 * HOTPLUG : Resume from Hotplug
119 * MFI_STOP_ADP : Send signal to FW to stop processing
121 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
122 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
123 #define DIAG_WRITE_ENABLE (0x00000080)
124 #define DIAG_RESET_ADAPTER (0x00000004)
126 #define MFI_ADP_RESET 0x00000040
127 #define MFI_INIT_ABORT 0x00000001
128 #define MFI_INIT_READY 0x00000002
129 #define MFI_INIT_MFIMODE 0x00000004
130 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
131 #define MFI_INIT_HOTPLUG 0x00000010
132 #define MFI_STOP_ADP 0x00000020
133 #define MFI_RESET_FLAGS MFI_INIT_READY| \
140 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
141 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
142 #define MFI_FRAME_SGL32 0x0000
143 #define MFI_FRAME_SGL64 0x0002
144 #define MFI_FRAME_SENSE32 0x0000
145 #define MFI_FRAME_SENSE64 0x0004
146 #define MFI_FRAME_DIR_NONE 0x0000
147 #define MFI_FRAME_DIR_WRITE 0x0008
148 #define MFI_FRAME_DIR_READ 0x0010
149 #define MFI_FRAME_DIR_BOTH 0x0018
150 #define MFI_FRAME_IEEE 0x0020
153 * Definition for cmd_status
155 #define MFI_CMD_STATUS_POLL_MODE 0xFF
158 * MFI command opcodes
160 #define MFI_CMD_INIT 0x00
161 #define MFI_CMD_LD_READ 0x01
162 #define MFI_CMD_LD_WRITE 0x02
163 #define MFI_CMD_LD_SCSI_IO 0x03
164 #define MFI_CMD_PD_SCSI_IO 0x04
165 #define MFI_CMD_DCMD 0x05
166 #define MFI_CMD_ABORT 0x06
167 #define MFI_CMD_SMP 0x07
168 #define MFI_CMD_STP 0x08
169 #define MFI_CMD_INVALID 0xff
171 #define MR_DCMD_CTRL_GET_INFO 0x01010000
172 #define MR_DCMD_LD_GET_LIST 0x03010000
174 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
175 #define MR_FLUSH_CTRL_CACHE 0x01
176 #define MR_FLUSH_DISK_CACHE 0x02
178 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
179 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
180 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
182 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
183 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
184 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
185 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
187 #define MR_DCMD_CLUSTER 0x08000000
188 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
189 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
190 #define MR_DCMD_PD_LIST_QUERY 0x02010100
195 extern u8
MR_ValidateMapInfo(struct megasas_instance
*instance
);
199 * MFI command completion codes
203 MFI_STAT_INVALID_CMD
= 0x01,
204 MFI_STAT_INVALID_DCMD
= 0x02,
205 MFI_STAT_INVALID_PARAMETER
= 0x03,
206 MFI_STAT_INVALID_SEQUENCE_NUMBER
= 0x04,
207 MFI_STAT_ABORT_NOT_POSSIBLE
= 0x05,
208 MFI_STAT_APP_HOST_CODE_NOT_FOUND
= 0x06,
209 MFI_STAT_APP_IN_USE
= 0x07,
210 MFI_STAT_APP_NOT_INITIALIZED
= 0x08,
211 MFI_STAT_ARRAY_INDEX_INVALID
= 0x09,
212 MFI_STAT_ARRAY_ROW_NOT_EMPTY
= 0x0a,
213 MFI_STAT_CONFIG_RESOURCE_CONFLICT
= 0x0b,
214 MFI_STAT_DEVICE_NOT_FOUND
= 0x0c,
215 MFI_STAT_DRIVE_TOO_SMALL
= 0x0d,
216 MFI_STAT_FLASH_ALLOC_FAIL
= 0x0e,
217 MFI_STAT_FLASH_BUSY
= 0x0f,
218 MFI_STAT_FLASH_ERROR
= 0x10,
219 MFI_STAT_FLASH_IMAGE_BAD
= 0x11,
220 MFI_STAT_FLASH_IMAGE_INCOMPLETE
= 0x12,
221 MFI_STAT_FLASH_NOT_OPEN
= 0x13,
222 MFI_STAT_FLASH_NOT_STARTED
= 0x14,
223 MFI_STAT_FLUSH_FAILED
= 0x15,
224 MFI_STAT_HOST_CODE_NOT_FOUNT
= 0x16,
225 MFI_STAT_LD_CC_IN_PROGRESS
= 0x17,
226 MFI_STAT_LD_INIT_IN_PROGRESS
= 0x18,
227 MFI_STAT_LD_LBA_OUT_OF_RANGE
= 0x19,
228 MFI_STAT_LD_MAX_CONFIGURED
= 0x1a,
229 MFI_STAT_LD_NOT_OPTIMAL
= 0x1b,
230 MFI_STAT_LD_RBLD_IN_PROGRESS
= 0x1c,
231 MFI_STAT_LD_RECON_IN_PROGRESS
= 0x1d,
232 MFI_STAT_LD_WRONG_RAID_LEVEL
= 0x1e,
233 MFI_STAT_MAX_SPARES_EXCEEDED
= 0x1f,
234 MFI_STAT_MEMORY_NOT_AVAILABLE
= 0x20,
235 MFI_STAT_MFC_HW_ERROR
= 0x21,
236 MFI_STAT_NO_HW_PRESENT
= 0x22,
237 MFI_STAT_NOT_FOUND
= 0x23,
238 MFI_STAT_NOT_IN_ENCL
= 0x24,
239 MFI_STAT_PD_CLEAR_IN_PROGRESS
= 0x25,
240 MFI_STAT_PD_TYPE_WRONG
= 0x26,
241 MFI_STAT_PR_DISABLED
= 0x27,
242 MFI_STAT_ROW_INDEX_INVALID
= 0x28,
243 MFI_STAT_SAS_CONFIG_INVALID_ACTION
= 0x29,
244 MFI_STAT_SAS_CONFIG_INVALID_DATA
= 0x2a,
245 MFI_STAT_SAS_CONFIG_INVALID_PAGE
= 0x2b,
246 MFI_STAT_SAS_CONFIG_INVALID_TYPE
= 0x2c,
247 MFI_STAT_SCSI_DONE_WITH_ERROR
= 0x2d,
248 MFI_STAT_SCSI_IO_FAILED
= 0x2e,
249 MFI_STAT_SCSI_RESERVATION_CONFLICT
= 0x2f,
250 MFI_STAT_SHUTDOWN_FAILED
= 0x30,
251 MFI_STAT_TIME_NOT_SET
= 0x31,
252 MFI_STAT_WRONG_STATE
= 0x32,
253 MFI_STAT_LD_OFFLINE
= 0x33,
254 MFI_STAT_PEER_NOTIFICATION_REJECTED
= 0x34,
255 MFI_STAT_PEER_NOTIFICATION_FAILED
= 0x35,
256 MFI_STAT_RESERVATION_IN_PROGRESS
= 0x36,
257 MFI_STAT_I2C_ERRORS_DETECTED
= 0x37,
258 MFI_STAT_PCI_ERRORS_DETECTED
= 0x38,
259 MFI_STAT_CONFIG_SEQ_MISMATCH
= 0x67,
261 MFI_STAT_INVALID_STATUS
= 0xFF
265 * Number of mailbox bytes in DCMD message frame
267 #define MFI_MBOX_SIZE 12
271 MR_EVT_CLASS_DEBUG
= -2,
272 MR_EVT_CLASS_PROGRESS
= -1,
273 MR_EVT_CLASS_INFO
= 0,
274 MR_EVT_CLASS_WARNING
= 1,
275 MR_EVT_CLASS_CRITICAL
= 2,
276 MR_EVT_CLASS_FATAL
= 3,
277 MR_EVT_CLASS_DEAD
= 4,
283 MR_EVT_LOCALE_LD
= 0x0001,
284 MR_EVT_LOCALE_PD
= 0x0002,
285 MR_EVT_LOCALE_ENCL
= 0x0004,
286 MR_EVT_LOCALE_BBU
= 0x0008,
287 MR_EVT_LOCALE_SAS
= 0x0010,
288 MR_EVT_LOCALE_CTRL
= 0x0020,
289 MR_EVT_LOCALE_CONFIG
= 0x0040,
290 MR_EVT_LOCALE_CLUSTER
= 0x0080,
291 MR_EVT_LOCALE_ALL
= 0xffff,
298 MR_EVT_ARGS_CDB_SENSE
,
300 MR_EVT_ARGS_LD_COUNT
,
302 MR_EVT_ARGS_LD_OWNER
,
303 MR_EVT_ARGS_LD_LBA_PD_LBA
,
305 MR_EVT_ARGS_LD_STATE
,
306 MR_EVT_ARGS_LD_STRIP
,
310 MR_EVT_ARGS_PD_LBA_LD
,
312 MR_EVT_ARGS_PD_STATE
,
319 MR_EVT_ARGS_PD_SPARE
,
320 MR_EVT_ARGS_PD_INDEX
,
321 MR_EVT_ARGS_DIAG_PASS
,
322 MR_EVT_ARGS_DIAG_FAIL
,
323 MR_EVT_ARGS_PD_LBA_LBA
,
324 MR_EVT_ARGS_PORT_PHY
,
325 MR_EVT_ARGS_PD_MISSING
,
326 MR_EVT_ARGS_PD_ADDRESS
,
328 MR_EVT_ARGS_CONNECTOR
,
331 MR_EVT_ARGS_PD_PATHINFO
,
332 MR_EVT_ARGS_PD_POWER_STATE
,
337 * define constants for device list query options
339 enum MR_PD_QUERY_TYPE
{
340 MR_PD_QUERY_TYPE_ALL
= 0,
341 MR_PD_QUERY_TYPE_STATE
= 1,
342 MR_PD_QUERY_TYPE_POWER_STATE
= 2,
343 MR_PD_QUERY_TYPE_MEDIA_TYPE
= 3,
344 MR_PD_QUERY_TYPE_SPEED
= 4,
345 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST
= 5,
348 #define MR_EVT_CFG_CLEARED 0x0004
349 #define MR_EVT_LD_STATE_CHANGE 0x0051
350 #define MR_EVT_PD_INSERTED 0x005b
351 #define MR_EVT_PD_REMOVED 0x0070
352 #define MR_EVT_LD_CREATED 0x008a
353 #define MR_EVT_LD_DELETED 0x008b
354 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
355 #define MR_EVT_LD_OFFLINE 0x00fc
356 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
357 #define MAX_LOGICAL_DRIVES 64
360 MR_PD_STATE_UNCONFIGURED_GOOD
= 0x00,
361 MR_PD_STATE_UNCONFIGURED_BAD
= 0x01,
362 MR_PD_STATE_HOT_SPARE
= 0x02,
363 MR_PD_STATE_OFFLINE
= 0x10,
364 MR_PD_STATE_FAILED
= 0x11,
365 MR_PD_STATE_REBUILD
= 0x14,
366 MR_PD_STATE_ONLINE
= 0x18,
367 MR_PD_STATE_COPYBACK
= 0x20,
368 MR_PD_STATE_SYSTEM
= 0x40,
373 * defines the physical drive address structure
375 struct MR_PD_ADDRESS
{
386 u8 enclConnectorIndex
;
391 u8 connectedPortBitmap
;
392 u8 connectedPortNumbers
;
398 * defines the physical drive list structure
403 struct MR_PD_ADDRESS addr
[1];
406 struct megasas_pd_list
{
413 * defines the logical drive reference structure
425 * defines the logical drive list structure
435 } ldList
[MAX_LOGICAL_DRIVES
];
439 * SAS controller properties
441 struct megasas_ctrl_prop
{
444 u16 pred_fail_poll_interval
;
445 u16 intr_throttle_count
;
446 u16 intr_throttle_timeouts
;
452 u8 cache_flush_interval
;
458 u8 disable_auto_rebuild
;
459 u8 disable_battery_warn
;
461 u16 ecc_bucket_leak_rate
;
462 u8 restore_hotspare_on_insertion
;
463 u8 expose_encl_devices
;
464 u8 maintainPdFailHistory
;
465 u8 disallowHostRequestReordering
;
468 u8 disableAutoDetectBackplane
;
473 * Add properties that can be controlled by
474 * a bit in the following structure.
477 u32 copyBackDisabled
: 1;
478 u32 SMARTerEnabled
: 1;
479 u32 prCorrectUnconfiguredAreas
: 1;
482 u32 SSDSMARTerEnabled
: 1;
483 u32 SSDPatrolReadEnabled
: 1;
484 u32 enableSpinDownUnconfigured
: 1;
485 u32 autoEnhancedImport
: 1;
486 u32 enableSecretKeyControl
: 1;
487 u32 disableOnlineCtrlReset
: 1;
488 u32 allowBootWithPinnedCache
: 1;
489 u32 disableSpinDownHS
: 1;
500 * SAS controller information
502 struct megasas_ctrl_info
{
505 * PCI device information
515 } __attribute__ ((packed
)) pci
;
518 * Host interface information
531 } __attribute__ ((packed
)) host_interface
;
534 * Device (backend) interface information
547 } __attribute__ ((packed
)) device_interface
;
550 * List of components residing in flash. All str are null terminated
552 u32 image_check_word
;
553 u32 image_component_count
;
562 } __attribute__ ((packed
)) image_component
[8];
565 * List of flash components that have been flashed on the card, but
566 * are not in use, pending reset of the adapter. This list will be
567 * empty if a flash operation has not occurred. All stings are null
570 u32 pending_image_component_count
;
579 } __attribute__ ((packed
)) pending_image_component
[8];
586 char product_name
[80];
590 * Other physical/controller/operation information. Indicates the
591 * presence of the hardware
601 } __attribute__ ((packed
)) hw_present
;
606 * Maximum data transfer sizes
608 u16 max_concurrent_cmds
;
610 u32 max_request_size
;
613 * Logical and physical device counts
615 u16 ld_present_count
;
616 u16 ld_degraded_count
;
617 u16 ld_offline_count
;
619 u16 pd_present_count
;
620 u16 pd_disk_present_count
;
621 u16 pd_disk_pred_failure_count
;
622 u16 pd_disk_failed_count
;
625 * Memory size information
634 u16 mem_correctable_error_count
;
635 u16 mem_uncorrectable_error_count
;
638 * Cluster information
640 u8 cluster_permitted
;
644 * Additional max data transfer sizes
646 u16 max_strips_per_io
;
649 * Controller capabilities structures
660 } __attribute__ ((packed
)) raid_levels
;
670 u32 cluster_supported
:1;
672 u32 spanning_allowed
:1;
673 u32 dedicated_hotspares
:1;
674 u32 revertible_hotspares
:1;
675 u32 foreign_config_import
:1;
676 u32 self_diagnostic
:1;
677 u32 mixed_redundancy_arr
:1;
678 u32 global_hot_spares
:1;
681 } __attribute__ ((packed
)) adapter_operations
;
689 u32 disk_cache_policy
:1;
692 } __attribute__ ((packed
)) ld_operations
;
700 } __attribute__ ((packed
)) stripe_sz_ops
;
709 } __attribute__ ((packed
)) pd_operations
;
713 u32 ctrl_supports_sas
:1;
714 u32 ctrl_supports_sata
:1;
715 u32 allow_mix_in_encl
:1;
716 u32 allow_mix_in_ld
:1;
717 u32 allow_sata_in_cluster
:1;
720 } __attribute__ ((packed
)) pd_mix_support
;
723 * Define ECC single-bit-error bucket information
729 * Include the controller properties (changeable items)
731 struct megasas_ctrl_prop properties
;
734 * Define FW pkg version (set in envt v'bles on OEM basis)
736 char package_version
[0x60];
740 * If adapterOperations.supportMoreThan8Phys is set,
741 * and deviceInterface.portCount is greater than 8,
742 * SAS Addrs for first 8 ports shall be populated in
743 * deviceInterface.portAddr, and the rest shall be
744 * populated in deviceInterfacePortAddr2.
746 u64 deviceInterfacePortAddr2
[8]; /*6a0h */
747 u8 reserved3
[128]; /*6e0h */
750 u16 minPdRaidLevel_0
:4;
751 u16 maxPdRaidLevel_0
:12;
753 u16 minPdRaidLevel_1
:4;
754 u16 maxPdRaidLevel_1
:12;
756 u16 minPdRaidLevel_5
:4;
757 u16 maxPdRaidLevel_5
:12;
759 u16 minPdRaidLevel_1E
:4;
760 u16 maxPdRaidLevel_1E
:12;
762 u16 minPdRaidLevel_6
:4;
763 u16 maxPdRaidLevel_6
:12;
765 u16 minPdRaidLevel_10
:4;
766 u16 maxPdRaidLevel_10
:12;
768 u16 minPdRaidLevel_50
:4;
769 u16 maxPdRaidLevel_50
:12;
771 u16 minPdRaidLevel_60
:4;
772 u16 maxPdRaidLevel_60
:12;
774 u16 minPdRaidLevel_1E_RLQ0
:4;
775 u16 maxPdRaidLevel_1E_RLQ0
:12;
777 u16 minPdRaidLevel_1E0_RLQ0
:4;
778 u16 maxPdRaidLevel_1E0_RLQ0
:12;
783 u16 maxPds
; /*780h */
784 u16 maxDedHSPs
; /*782h */
785 u16 maxGlobalHSPs
; /*784h */
786 u16 ddfSize
; /*786h */
787 u8 maxLdsPerArray
; /*788h */
788 u8 partitionsInDDF
; /*789h */
789 u8 lockKeyBinding
; /*78ah */
790 u8 maxPITsPerLd
; /*78bh */
791 u8 maxViewsPerLd
; /*78ch */
792 u8 maxTargetId
; /*78dh */
793 u16 maxBvlVdSize
; /*78eh */
795 u16 maxConfigurableSSCSize
; /*790h */
796 u16 currentSSCsize
; /*792h */
798 char expanderFwVersion
[12]; /*794h */
800 u16 PFKTrialTimeRemaining
; /*7A0h */
802 u16 cacheMemorySize
; /*7A2h */
805 u32 supportPIcontroller
:1;
806 u32 supportLdPIType1
:1;
807 u32 supportLdPIType2
:1;
808 u32 supportLdPIType3
:1;
809 u32 supportLdBBMInfo
:1;
810 u32 supportShieldState
:1;
811 u32 blockSSDWriteCacheChange
:1;
812 u32 supportSuspendResumeBGops
:1;
813 u32 supportEmergencySpares
:1;
814 u32 supportSetLinkSpeed
:1;
815 u32 supportBootTimePFKChange
:1;
817 u32 disableOnlinePFKChange
:1;
818 u32 supportPerfTuning
:1;
819 u32 supportSSDPatrolRead
:1;
820 u32 realTimeScheduler
:1;
822 u32 supportResetNow
:1;
823 u32 supportEmulatedDrives
:1;
825 u32 dedicatedHotSparesLimited
:1;
828 u32 supportUnevenSpans
:1;
830 } adapterOperations2
;
832 u8 driverVersion
[32]; /*7A8h */
833 u8 maxDAPdCountSpinup60
; /*7C8h */
834 u8 temperatureROC
; /*7C9h */
835 u8 temperatureCtrl
; /*7CAh */
836 u8 reserved4
; /*7CBh */
837 u16 maxConfigurablePds
; /*7CCh */
840 u8 reserved5
[2]; /*0x7CDh */
843 * HA cluster information
847 u32 peerIsIncompatible
:1;
848 u32 hwIncompatible
:1;
849 u32 fwVersionMismatch
:1;
850 u32 ctrlPropIncompatible
:1;
851 u32 premiumFeatureMismatch
:1;
855 char clusterId
[16]; /*7D4h */
857 u8 pad
[0x800-0x7E4]; /*7E4 */
861 * ===============================
862 * MegaRAID SAS driver definitions
863 * ===============================
865 #define MEGASAS_MAX_PD_CHANNELS 2
866 #define MEGASAS_MAX_LD_CHANNELS 2
867 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
868 MEGASAS_MAX_LD_CHANNELS)
869 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
870 #define MEGASAS_DEFAULT_INIT_ID -1
871 #define MEGASAS_MAX_LUN 8
872 #define MEGASAS_MAX_LD 64
873 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
874 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
875 MEGASAS_MAX_DEV_PER_CHANNEL)
876 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
877 MEGASAS_MAX_DEV_PER_CHANNEL)
879 #define MEGASAS_MAX_SECTORS (2*1024)
880 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
881 #define MEGASAS_DBG_LVL 1
883 #define MEGASAS_FW_BUSY 1
887 #define PTHRU_FRAME 1
890 * When SCSI mid-layer calls driver's reset routine, driver waits for
891 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
892 * that the driver cannot _actually_ abort or reset pending commands. While
893 * it is waiting for the commands to complete, it prints a diagnostic message
894 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
896 #define MEGASAS_RESET_WAIT_TIME 180
897 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
898 #define MEGASAS_RESET_NOTICE_INTERVAL 5
899 #define MEGASAS_IOCTL_CMD 0
900 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
901 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
904 * FW reports the maximum of number of commands that it can accept (maximum
905 * commands that can be outstanding) at any time. The driver must report a
906 * lower number to the mid layer because it can issue a few internal commands
907 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
910 #define MEGASAS_INT_CMDS 32
911 #define MEGASAS_SKINNY_INT_CMDS 5
913 #define MEGASAS_MAX_MSIX_QUEUES 128
915 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
916 * SGLs based on the size of dma_addr_t
918 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
920 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
922 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
923 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
924 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
926 #define MFI_OB_INTR_STATUS_MASK 0x00000002
927 #define MFI_POLL_TIMEOUT_SECS 60
929 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
930 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
931 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
932 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
933 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
935 #define MFI_1068_PCSR_OFFSET 0x84
936 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
937 #define MFI_1068_FW_READY 0xDDDD0000
939 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
940 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
941 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
942 #define MR_MAX_MSIX_REG_ARRAY 16
944 * register set for both 1068 and 1078 controllers
945 * structure extended for 1078 registers
948 struct megasas_register_set
{
949 u32 doorbell
; /*0000h*/
950 u32 fusion_seq_offset
; /*0004h*/
951 u32 fusion_host_diag
; /*0008h*/
952 u32 reserved_01
; /*000Ch*/
954 u32 inbound_msg_0
; /*0010h*/
955 u32 inbound_msg_1
; /*0014h*/
956 u32 outbound_msg_0
; /*0018h*/
957 u32 outbound_msg_1
; /*001Ch*/
959 u32 inbound_doorbell
; /*0020h*/
960 u32 inbound_intr_status
; /*0024h*/
961 u32 inbound_intr_mask
; /*0028h*/
963 u32 outbound_doorbell
; /*002Ch*/
964 u32 outbound_intr_status
; /*0030h*/
965 u32 outbound_intr_mask
; /*0034h*/
967 u32 reserved_1
[2]; /*0038h*/
969 u32 inbound_queue_port
; /*0040h*/
970 u32 outbound_queue_port
; /*0044h*/
972 u32 reserved_2
[9]; /*0048h*/
973 u32 reply_post_host_index
; /*006Ch*/
974 u32 reserved_2_2
[12]; /*0070h*/
976 u32 outbound_doorbell_clear
; /*00A0h*/
978 u32 reserved_3
[3]; /*00A4h*/
980 u32 outbound_scratch_pad
; /*00B0h*/
981 u32 outbound_scratch_pad_2
; /*00B4h*/
983 u32 reserved_4
[2]; /*00B8h*/
985 u32 inbound_low_queue_port
; /*00C0h*/
987 u32 inbound_high_queue_port
; /*00C4h*/
989 u32 reserved_5
; /*00C8h*/
990 u32 res_6
[11]; /*CCh*/
993 u32 index_registers
[807]; /*00CCh*/
994 } __attribute__ ((packed
));
996 struct megasas_sge32
{
1001 } __attribute__ ((packed
));
1003 struct megasas_sge64
{
1008 } __attribute__ ((packed
));
1010 struct megasas_sge_skinny
{
1018 struct megasas_sge32 sge32
[1];
1019 struct megasas_sge64 sge64
[1];
1020 struct megasas_sge_skinny sge_skinny
[1];
1022 } __attribute__ ((packed
));
1024 struct megasas_header
{
1027 u8 sense_len
; /*01h */
1028 u8 cmd_status
; /*02h */
1029 u8 scsi_status
; /*03h */
1031 u8 target_id
; /*04h */
1033 u8 cdb_len
; /*06h */
1034 u8 sge_count
; /*07h */
1036 u32 context
; /*08h */
1040 u16 timeout
; /*12h */
1041 u32 data_xferlen
; /*14h */
1043 } __attribute__ ((packed
));
1045 union megasas_sgl_frame
{
1047 struct megasas_sge32 sge32
[8];
1048 struct megasas_sge64 sge64
[5];
1050 } __attribute__ ((packed
));
1052 typedef union _MFI_CAPABILITIES
{
1054 u32 support_fp_remote_lun
:1;
1055 u32 support_additional_msix
:1;
1061 struct megasas_init_frame
{
1064 u8 reserved_0
; /*01h */
1065 u8 cmd_status
; /*02h */
1067 u8 reserved_1
; /*03h */
1068 MFI_CAPABILITIES driver_operations
; /*04h*/
1070 u32 context
; /*08h */
1074 u16 reserved_3
; /*12h */
1075 u32 data_xfer_len
; /*14h */
1077 u32 queue_info_new_phys_addr_lo
; /*18h */
1078 u32 queue_info_new_phys_addr_hi
; /*1Ch */
1079 u32 queue_info_old_phys_addr_lo
; /*20h */
1080 u32 queue_info_old_phys_addr_hi
; /*24h */
1082 u32 reserved_4
[6]; /*28h */
1084 } __attribute__ ((packed
));
1086 struct megasas_init_queue_info
{
1088 u32 init_flags
; /*00h */
1089 u32 reply_queue_entries
; /*04h */
1091 u32 reply_queue_start_phys_addr_lo
; /*08h */
1092 u32 reply_queue_start_phys_addr_hi
; /*0Ch */
1093 u32 producer_index_phys_addr_lo
; /*10h */
1094 u32 producer_index_phys_addr_hi
; /*14h */
1095 u32 consumer_index_phys_addr_lo
; /*18h */
1096 u32 consumer_index_phys_addr_hi
; /*1Ch */
1098 } __attribute__ ((packed
));
1100 struct megasas_io_frame
{
1103 u8 sense_len
; /*01h */
1104 u8 cmd_status
; /*02h */
1105 u8 scsi_status
; /*03h */
1107 u8 target_id
; /*04h */
1108 u8 access_byte
; /*05h */
1109 u8 reserved_0
; /*06h */
1110 u8 sge_count
; /*07h */
1112 u32 context
; /*08h */
1116 u16 timeout
; /*12h */
1117 u32 lba_count
; /*14h */
1119 u32 sense_buf_phys_addr_lo
; /*18h */
1120 u32 sense_buf_phys_addr_hi
; /*1Ch */
1122 u32 start_lba_lo
; /*20h */
1123 u32 start_lba_hi
; /*24h */
1125 union megasas_sgl sgl
; /*28h */
1127 } __attribute__ ((packed
));
1129 struct megasas_pthru_frame
{
1132 u8 sense_len
; /*01h */
1133 u8 cmd_status
; /*02h */
1134 u8 scsi_status
; /*03h */
1136 u8 target_id
; /*04h */
1138 u8 cdb_len
; /*06h */
1139 u8 sge_count
; /*07h */
1141 u32 context
; /*08h */
1145 u16 timeout
; /*12h */
1146 u32 data_xfer_len
; /*14h */
1148 u32 sense_buf_phys_addr_lo
; /*18h */
1149 u32 sense_buf_phys_addr_hi
; /*1Ch */
1151 u8 cdb
[16]; /*20h */
1152 union megasas_sgl sgl
; /*30h */
1154 } __attribute__ ((packed
));
1156 struct megasas_dcmd_frame
{
1159 u8 reserved_0
; /*01h */
1160 u8 cmd_status
; /*02h */
1161 u8 reserved_1
[4]; /*03h */
1162 u8 sge_count
; /*07h */
1164 u32 context
; /*08h */
1168 u16 timeout
; /*12h */
1170 u32 data_xfer_len
; /*14h */
1171 u32 opcode
; /*18h */
1179 union megasas_sgl sgl
; /*28h */
1181 } __attribute__ ((packed
));
1183 struct megasas_abort_frame
{
1186 u8 reserved_0
; /*01h */
1187 u8 cmd_status
; /*02h */
1189 u8 reserved_1
; /*03h */
1190 u32 reserved_2
; /*04h */
1192 u32 context
; /*08h */
1196 u16 reserved_3
; /*12h */
1197 u32 reserved_4
; /*14h */
1199 u32 abort_context
; /*18h */
1202 u32 abort_mfi_phys_addr_lo
; /*20h */
1203 u32 abort_mfi_phys_addr_hi
; /*24h */
1205 u32 reserved_5
[6]; /*28h */
1207 } __attribute__ ((packed
));
1209 struct megasas_smp_frame
{
1212 u8 reserved_1
; /*01h */
1213 u8 cmd_status
; /*02h */
1214 u8 connection_status
; /*03h */
1216 u8 reserved_2
[3]; /*04h */
1217 u8 sge_count
; /*07h */
1219 u32 context
; /*08h */
1223 u16 timeout
; /*12h */
1225 u32 data_xfer_len
; /*14h */
1226 u64 sas_addr
; /*18h */
1229 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: req */
1230 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: req */
1233 } __attribute__ ((packed
));
1235 struct megasas_stp_frame
{
1238 u8 reserved_1
; /*01h */
1239 u8 cmd_status
; /*02h */
1240 u8 reserved_2
; /*03h */
1242 u8 target_id
; /*04h */
1243 u8 reserved_3
[2]; /*05h */
1244 u8 sge_count
; /*07h */
1246 u32 context
; /*08h */
1250 u16 timeout
; /*12h */
1252 u32 data_xfer_len
; /*14h */
1254 u16 fis
[10]; /*18h */
1258 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: data */
1259 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: data */
1262 } __attribute__ ((packed
));
1264 union megasas_frame
{
1266 struct megasas_header hdr
;
1267 struct megasas_init_frame init
;
1268 struct megasas_io_frame io
;
1269 struct megasas_pthru_frame pthru
;
1270 struct megasas_dcmd_frame dcmd
;
1271 struct megasas_abort_frame abort
;
1272 struct megasas_smp_frame smp
;
1273 struct megasas_stp_frame stp
;
1280 union megasas_evt_class_locale
{
1286 } __attribute__ ((packed
)) members
;
1290 } __attribute__ ((packed
));
1292 struct megasas_evt_log_info
{
1296 u32 shutdown_seq_num
;
1299 } __attribute__ ((packed
));
1301 struct megasas_progress
{
1304 u16 elapsed_seconds
;
1306 } __attribute__ ((packed
));
1308 struct megasas_evtarg_ld
{
1314 } __attribute__ ((packed
));
1316 struct megasas_evtarg_pd
{
1321 } __attribute__ ((packed
));
1323 struct megasas_evt_detail
{
1328 union megasas_evt_class_locale cl
;
1334 struct megasas_evtarg_pd pd
;
1340 } __attribute__ ((packed
)) cdbSense
;
1342 struct megasas_evtarg_ld ld
;
1345 struct megasas_evtarg_ld ld
;
1347 } __attribute__ ((packed
)) ld_count
;
1351 struct megasas_evtarg_ld ld
;
1352 } __attribute__ ((packed
)) ld_lba
;
1355 struct megasas_evtarg_ld ld
;
1358 } __attribute__ ((packed
)) ld_owner
;
1363 struct megasas_evtarg_ld ld
;
1364 struct megasas_evtarg_pd pd
;
1365 } __attribute__ ((packed
)) ld_lba_pd_lba
;
1368 struct megasas_evtarg_ld ld
;
1369 struct megasas_progress prog
;
1370 } __attribute__ ((packed
)) ld_prog
;
1373 struct megasas_evtarg_ld ld
;
1376 } __attribute__ ((packed
)) ld_state
;
1380 struct megasas_evtarg_ld ld
;
1381 } __attribute__ ((packed
)) ld_strip
;
1383 struct megasas_evtarg_pd pd
;
1386 struct megasas_evtarg_pd pd
;
1388 } __attribute__ ((packed
)) pd_err
;
1392 struct megasas_evtarg_pd pd
;
1393 } __attribute__ ((packed
)) pd_lba
;
1397 struct megasas_evtarg_pd pd
;
1398 struct megasas_evtarg_ld ld
;
1399 } __attribute__ ((packed
)) pd_lba_ld
;
1402 struct megasas_evtarg_pd pd
;
1403 struct megasas_progress prog
;
1404 } __attribute__ ((packed
)) pd_prog
;
1407 struct megasas_evtarg_pd pd
;
1410 } __attribute__ ((packed
)) pd_state
;
1417 } __attribute__ ((packed
)) pci
;
1425 } __attribute__ ((packed
)) time
;
1431 } __attribute__ ((packed
)) ecc
;
1439 char description
[128];
1441 } __attribute__ ((packed
));
1443 struct megasas_aen_event
{
1444 struct delayed_work hotplug_work
;
1445 struct megasas_instance
*instance
;
1448 struct megasas_irq_context
{
1449 struct megasas_instance
*instance
;
1453 struct megasas_instance
{
1456 dma_addr_t producer_h
;
1458 dma_addr_t consumer_h
;
1461 dma_addr_t reply_queue_h
;
1463 unsigned long base_addr
;
1464 struct megasas_register_set __iomem
*reg_set
;
1465 u32
*reply_post_host_index_addr
[MR_MAX_MSIX_REG_ARRAY
];
1466 struct megasas_pd_list pd_list
[MEGASAS_MAX_PD
];
1467 u8 ld_ids
[MEGASAS_MAX_LD_IDS
];
1472 /* For Fusion its num IOCTL cmds, for others MFI based its
1475 u32 max_sectors_per_req
;
1476 struct megasas_aen_event
*ev
;
1478 struct megasas_cmd
**cmd_list
;
1479 struct list_head cmd_pool
;
1480 /* used to sync fire the cmd to fw */
1481 spinlock_t cmd_pool_lock
;
1482 /* used to sync fire the cmd to fw */
1483 spinlock_t hba_lock
;
1484 /* used to synch producer, consumer ptrs in dpc */
1485 spinlock_t completion_lock
;
1486 struct dma_pool
*frame_dma_pool
;
1487 struct dma_pool
*sense_dma_pool
;
1489 struct megasas_evt_detail
*evt_detail
;
1490 dma_addr_t evt_detail_h
;
1491 struct megasas_cmd
*aen_cmd
;
1492 struct mutex aen_mutex
;
1493 struct semaphore ioctl_sem
;
1495 struct Scsi_Host
*host
;
1497 wait_queue_head_t int_cmd_wait_q
;
1498 wait_queue_head_t abort_cmd_wait_q
;
1500 struct pci_dev
*pdev
;
1502 u32 fw_support_ieee
;
1504 atomic_t fw_outstanding
;
1505 atomic_t fw_reset_no_pci_access
;
1507 struct megasas_instance_template
*instancet
;
1508 struct tasklet_struct isr_tasklet
;
1509 struct work_struct work_init
;
1515 u8 disableOnlineCtrlReset
;
1516 u8 UnevenSpanSupport
;
1518 unsigned long last_time
;
1522 struct list_head internal_reset_pending_q
;
1524 /* Ptr to hba specific information */
1526 unsigned int msix_vectors
;
1527 struct msix_entry msixentry
[MEGASAS_MAX_MSIX_QUEUES
];
1528 struct megasas_irq_context irq_context
[MEGASAS_MAX_MSIX_QUEUES
];
1530 struct megasas_cmd
*map_update_cmd
;
1533 struct mutex reset_mutex
;
1534 int throttlequeuedepth
;
1540 MEGASAS_HBA_OPERATIONAL
= 0,
1541 MEGASAS_ADPRESET_SM_INFAULT
= 1,
1542 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS
= 2,
1543 MEGASAS_ADPRESET_SM_OPERATIONAL
= 3,
1544 MEGASAS_HW_CRITICAL_ERROR
= 4,
1545 MEGASAS_ADPRESET_INPROG_SIGN
= 0xDEADDEAD,
1548 struct megasas_instance_template
{
1549 void (*fire_cmd
)(struct megasas_instance
*, dma_addr_t
, \
1550 u32
, struct megasas_register_set __iomem
*);
1552 void (*enable_intr
)(struct megasas_instance
*);
1553 void (*disable_intr
)(struct megasas_instance
*);
1555 int (*clear_intr
)(struct megasas_register_set __iomem
*);
1557 u32 (*read_fw_status_reg
)(struct megasas_register_set __iomem
*);
1558 int (*adp_reset
)(struct megasas_instance
*, \
1559 struct megasas_register_set __iomem
*);
1560 int (*check_reset
)(struct megasas_instance
*, \
1561 struct megasas_register_set __iomem
*);
1562 irqreturn_t (*service_isr
)(int irq
, void *devp
);
1563 void (*tasklet
)(unsigned long);
1564 u32 (*init_adapter
)(struct megasas_instance
*);
1565 u32 (*build_and_issue_cmd
) (struct megasas_instance
*,
1566 struct scsi_cmnd
*);
1567 void (*issue_dcmd
) (struct megasas_instance
*instance
,
1568 struct megasas_cmd
*cmd
);
1571 #define MEGASAS_IS_LOGICAL(scp) \
1572 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1574 #define MEGASAS_DEV_INDEX(inst, scp) \
1575 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1578 struct megasas_cmd
{
1580 union megasas_frame
*frame
;
1581 dma_addr_t frame_phys_addr
;
1583 dma_addr_t sense_phys_addr
;
1589 u8 retry_for_fw_reset
;
1592 struct list_head list
;
1593 struct scsi_cmnd
*scmd
;
1594 struct megasas_instance
*instance
;
1604 #define MAX_MGMT_ADAPTERS 1024
1605 #define MAX_IOCTL_SGE 16
1607 struct megasas_iocpacket
{
1617 struct megasas_header hdr
;
1620 struct iovec sgl
[MAX_IOCTL_SGE
];
1622 } __attribute__ ((packed
));
1624 struct megasas_aen
{
1628 u32 class_locale_word
;
1629 } __attribute__ ((packed
));
1631 #ifdef CONFIG_COMPAT
1632 struct compat_megasas_iocpacket
{
1641 struct megasas_header hdr
;
1643 struct compat_iovec sgl
[MAX_IOCTL_SGE
];
1644 } __attribute__ ((packed
));
1646 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1649 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1650 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1652 struct megasas_mgmt_info
{
1655 struct megasas_instance
*instance
[MAX_MGMT_ADAPTERS
];
1659 #endif /*LSI_MEGARAID_SAS_H */