2 * This driver adapted from Drew Eckhardt's Trantor T128 driver
4 * Copyright 1993, Drew Eckhardt
6 * (Unix and Linux consulting and custom programming)
10 * ( Based on T128 - DISTRIBUTION RELEASE 3. )
12 * Modified to work with the Pro Audio Spectrum/Studio 16
16 * For more information, please consult
25 * SCSI Protocol Controller
28 * NCR Microelectronics
29 * 1635 Aeroplaza Drive
30 * Colorado Springs, CO 80916
39 #define PAS16_PUBLIC_RELEASE 3
41 #define PDEBUG_INIT 0x1
42 #define PDEBUG_TRANSFER 0x2
44 #define PAS16_DEFAULT_BASE_1 0x388
45 #define PAS16_DEFAULT_BASE_2 0x384
46 #define PAS16_DEFAULT_BASE_3 0x38c
47 #define PAS16_DEFAULT_BASE_4 0x288
49 #define PAS16_DEFAULT_BOARD_1_IRQ 10
50 #define PAS16_DEFAULT_BOARD_2_IRQ 12
51 #define PAS16_DEFAULT_BOARD_3_IRQ 14
52 #define PAS16_DEFAULT_BOARD_4_IRQ 15
56 * The Pro Audio Spectrum boards are I/O mapped. They use a Zilog 5380
57 * SCSI controller, which is the equivalent of NCR's 5380. "Pseudo-DMA"
58 * architecture is used, where a PAL drives the DMA signals on the 5380
59 * allowing fast, blind transfers with proper handshaking.
63 /* The Time-out Counter register is used to safe-guard against a stuck
64 * bus (in the case of RDY driven handshake) or a stuck byte (if 16-Bit
65 * DMA conversion is used). The counter uses a 28.224MHz clock
66 * divided by 14 as its clock source. In the case of a stuck byte in
67 * the holding register, an interrupt is generated (and mixed with the
68 * one with the drive) using the CD-ROM interrupt pointer.
71 #define P_TIMEOUT_COUNTER_REG 0x4000
72 #define P_TC_DISABLE 0x80 /* Set to 0 to enable timeout int. */
73 /* Bits D6-D0 contain timeout count */
76 #define P_TIMEOUT_STATUS_REG_OFFSET 0x4001
77 #define P_TS_TIM 0x80 /* check timeout status */
79 #define P_TS_ARM_DRQ_INT 0x08 /* Arm DRQ Int. When set high,
80 * the next rising edge will
81 * cause a CD-ROM interrupt.
82 * When set low, the interrupt
83 * will be cleared. There is
84 * no status available for
87 #define P_TS_ENABLE_TO_ERR_INTERRUPT /* Enable timeout error int. */
88 #define P_TS_ENABLE_WAIT /* Enable Wait */
90 #define P_TS_CT 0x01 /* clear timeout. Note: writing
91 * to this register clears the
92 * timeout error int. or status
97 * The data register reads/writes to/from the 5380 in pseudo-DMA mode
100 #define P_DATA_REG_OFFSET 0x5c00 /* rw */
102 #define P_STATUS_REG_OFFSET 0x5c01 /* ro */
103 #define P_ST_RDY 0x80 /* 5380 DDRQ Status */
105 #define P_IRQ_STATUS 0x5c03
106 #define P_IS_IRQ 0x80 /* DIRQ status */
108 #define PCB_CONFIG 0x803
109 #define MASTER_ADDRESS_PTR 0x9a01 /* Fixed position - no relo */
110 #define SYS_CONFIG_4 0x8003
111 #define WAIT_STATE 0xbc00
112 #define OPERATION_MODE_1 0xec03
113 #define IO_CONFIG_3 0xf002
117 static int pas16_abort(Scsi_Cmnd
*);
118 static int pas16_biosparam(struct scsi_device
*, struct block_device
*,
120 static int pas16_detect(struct scsi_host_template
*);
121 static int pas16_queue_command(struct Scsi_Host
*, struct scsi_cmnd
*);
122 static int pas16_bus_reset(Scsi_Cmnd
*);
125 #define CMD_PER_LUN 2
132 #define NCR5380_implementation_fields \
133 volatile unsigned short io_port
135 #define NCR5380_local_declare() \
136 volatile unsigned short io_port
138 #define NCR5380_setup(instance) \
139 io_port = (instance)->io_port
141 #define PAS16_io_port(reg) ( io_port + pas16_offset[(reg)] )
143 #if !(PDEBUG & PDEBUG_TRANSFER)
144 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
145 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
147 #define NCR5380_read(reg) \
148 (((unsigned char) printk("scsi%d : read register %d at io_port %04x\n"\
149 , instance->hostno, (reg), PAS16_io_port(reg))), inb( PAS16_io_port(reg)) )
151 #define NCR5380_write(reg, value) \
152 (printk("scsi%d : write %02x to register %d at io_port %04x\n", \
153 instance->hostno, (value), (reg), PAS16_io_port(reg)), \
154 outb( (value),PAS16_io_port(reg) ) )
159 #define NCR5380_intr pas16_intr
160 #define do_NCR5380_intr do_pas16_intr
161 #define NCR5380_queue_command pas16_queue_command
162 #define NCR5380_abort pas16_abort
163 #define NCR5380_bus_reset pas16_bus_reset
164 #define NCR5380_show_info pas16_show_info
165 #define NCR5380_write_info pas16_write_info
168 1101 0100 1010 1000 */
170 #define PAS16_IRQS 0xd4a8
172 #endif /* ndef ASM */
This page took 0.033139 seconds and 5 git commands to generate.