drivers/scsi/pm8001/pm80xx_hwi.h

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions, and the following disclaimer,
  12  *      without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *      substantially similar to the "NO WARRANTY" disclaimer below
  15  *      ("Disclaimer") and any redistribution must be conditioned upon
  16  *      including a substantially similar Disclaimer requirement for further
  17  *      binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *      of any contributors may be used to endorse or promote products derived
  20  *      from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #ifndef _PMC8001_REG_H_
  42 #define _PMC8001_REG_H_
  43
  44 #include <linux/types.h>
  45 #include <scsi/libsas.h>
  46
  47 /* for Request Opcode of IOMB */
  48 #define OPC_INB_ECHO                            1       /* 0x000 */
  49 #define OPC_INB_PHYSTART                        4       /* 0x004 */
  50 #define OPC_INB_PHYSTOP                         5       /* 0x005 */
  51 #define OPC_INB_SSPINIIOSTART                   6       /* 0x006 */
  52 #define OPC_INB_SSPINITMSTART                   7       /* 0x007 */
  53 /* 0x8 RESV IN SPCv */
  54 #define OPC_INB_RSVD                            8       /* 0x008 */
  55 #define OPC_INB_DEV_HANDLE_ACCEPT               9       /* 0x009 */
  56 #define OPC_INB_SSPTGTIOSTART                   10      /* 0x00A */
  57 #define OPC_INB_SSPTGTRSPSTART                  11      /* 0x00B */
  58 /* 0xC, 0xD, 0xE removed in SPCv */
  59 #define OPC_INB_SSP_ABORT                       15      /* 0x00F */
  60 #define OPC_INB_DEREG_DEV_HANDLE                16      /* 0x010 */
  61 #define OPC_INB_GET_DEV_HANDLE                  17      /* 0x011 */
  62 #define OPC_INB_SMP_REQUEST                     18      /* 0x012 */
  63 /* 0x13 SMP_RESPONSE is removed in SPCv */
  64 #define OPC_INB_SMP_ABORT                       20      /* 0x014 */
  65 /* 0x16 RESV IN SPCv */
  66 #define OPC_INB_RSVD1                           22      /* 0x016 */
  67 #define OPC_INB_SATA_HOST_OPSTART               23      /* 0x017 */
  68 #define OPC_INB_SATA_ABORT                      24      /* 0x018 */
  69 #define OPC_INB_LOCAL_PHY_CONTROL               25      /* 0x019 */
  70 /* 0x1A RESV IN SPCv */
  71 #define OPC_INB_RSVD2                           26      /* 0x01A */
  72 #define OPC_INB_FW_FLASH_UPDATE                 32      /* 0x020 */
  73 #define OPC_INB_GPIO                            34      /* 0x022 */
  74 #define OPC_INB_SAS_DIAG_MODE_START_END         35      /* 0x023 */
  75 #define OPC_INB_SAS_DIAG_EXECUTE                36      /* 0x024 */
  76 /* 0x25 RESV IN SPCv */
  77 #define OPC_INB_RSVD3                           37      /* 0x025 */
  78 #define OPC_INB_GET_TIME_STAMP                  38      /* 0x026 */
  79 #define OPC_INB_PORT_CONTROL                    39      /* 0x027 */
  80 #define OPC_INB_GET_NVMD_DATA                   40      /* 0x028 */
  81 #define OPC_INB_SET_NVMD_DATA                   41      /* 0x029 */
  82 #define OPC_INB_SET_DEVICE_STATE                42      /* 0x02A */
  83 #define OPC_INB_GET_DEVICE_STATE                43      /* 0x02B */
  84 #define OPC_INB_SET_DEV_INFO                    44      /* 0x02C */
  85 /* 0x2D RESV IN SPCv */
  86 #define OPC_INB_RSVD4                           45      /* 0x02D */
  87 #define OPC_INB_SGPIO_REGISTER                  46      /* 0x02E */
  88 #define OPC_INB_PCIE_DIAG_EXEC                  47      /* 0x02F */
  89 #define OPC_INB_SET_CONTROLLER_CONFIG           48      /* 0x030 */
  90 #define OPC_INB_GET_CONTROLLER_CONFIG           49      /* 0x031 */
  91 #define OPC_INB_REG_DEV                         50      /* 0x032 */
  92 #define OPC_INB_SAS_HW_EVENT_ACK                51      /* 0x033 */
  93 #define OPC_INB_GET_DEVICE_INFO                 52      /* 0x034 */
  94 #define OPC_INB_GET_PHY_PROFILE                 53      /* 0x035 */
  95 #define OPC_INB_FLASH_OP_EXT                    54      /* 0x036 */
  96 #define OPC_INB_SET_PHY_PROFILE                 55      /* 0x037 */
  97 #define OPC_INB_KEK_MANAGEMENT                  256     /* 0x100 */
  98 #define OPC_INB_DEK_MANAGEMENT                  257     /* 0x101 */
  99 #define OPC_INB_SSP_INI_DIF_ENC_IO              258     /* 0x102 */
 100 #define OPC_INB_SATA_DIF_ENC_IO                 259     /* 0x103 */
 101
 102 /* for Response Opcode of IOMB */
 103 #define OPC_OUB_ECHO                                    1       /* 0x001 */
 104 #define OPC_OUB_RSVD                                    4       /* 0x004 */
 105 #define OPC_OUB_SSP_COMP                                5       /* 0x005 */
 106 #define OPC_OUB_SMP_COMP                                6       /* 0x006 */
 107 #define OPC_OUB_LOCAL_PHY_CNTRL                         7       /* 0x007 */
 108 #define OPC_OUB_RSVD1                                   10      /* 0x00A */
 109 #define OPC_OUB_DEREG_DEV                               11      /* 0x00B */
 110 #define OPC_OUB_GET_DEV_HANDLE                          12      /* 0x00C */
 111 #define OPC_OUB_SATA_COMP                               13      /* 0x00D */
 112 #define OPC_OUB_SATA_EVENT                              14      /* 0x00E */
 113 #define OPC_OUB_SSP_EVENT                               15      /* 0x00F */
 114 #define OPC_OUB_RSVD2                                   16      /* 0x010 */
 115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
 116 #define OPC_OUB_SSP_RECV_EVENT                          18      /* 0x012 */
 117 #define OPC_OUB_RSVD3                                   19      /* 0x013 */
 118 #define OPC_OUB_FW_FLASH_UPDATE                         20      /* 0x014 */
 119 #define OPC_OUB_GPIO_RESPONSE                           22      /* 0x016 */
 120 #define OPC_OUB_GPIO_EVENT                              23      /* 0x017 */
 121 #define OPC_OUB_GENERAL_EVENT                           24      /* 0x018 */
 122 #define OPC_OUB_SSP_ABORT_RSP                           26      /* 0x01A */
 123 #define OPC_OUB_SATA_ABORT_RSP                          27      /* 0x01B */
 124 #define OPC_OUB_SAS_DIAG_MODE_START_END                 28      /* 0x01C */
 125 #define OPC_OUB_SAS_DIAG_EXECUTE                        29      /* 0x01D */
 126 #define OPC_OUB_GET_TIME_STAMP                          30      /* 0x01E */
 127 #define OPC_OUB_RSVD4                                   31      /* 0x01F */
 128 #define OPC_OUB_PORT_CONTROL                            32      /* 0x020 */
 129 #define OPC_OUB_SKIP_ENTRY                              33      /* 0x021 */
 130 #define OPC_OUB_SMP_ABORT_RSP                           34      /* 0x022 */
 131 #define OPC_OUB_GET_NVMD_DATA                           35      /* 0x023 */
 132 #define OPC_OUB_SET_NVMD_DATA                           36      /* 0x024 */
 133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL                   37      /* 0x025 */
 134 #define OPC_OUB_SET_DEVICE_STATE                        38      /* 0x026 */
 135 #define OPC_OUB_GET_DEVICE_STATE                        39      /* 0x027 */
 136 #define OPC_OUB_SET_DEV_INFO                            40      /* 0x028 */
 137 #define OPC_OUB_RSVD5                                   41      /* 0x029 */
 138 #define OPC_OUB_HW_EVENT                                1792    /* 0x700 */
 139 #define OPC_OUB_DEV_HANDLE_ARRIV                        1824    /* 0x720 */
 140 #define OPC_OUB_THERM_HW_EVENT                          1840    /* 0x730 */
 141 #define OPC_OUB_SGPIO_RESP                              2094    /* 0x82E */
 142 #define OPC_OUB_PCIE_DIAG_EXECUTE                       2095    /* 0x82F */
 143 #define OPC_OUB_DEV_REGIST                              2098    /* 0x832 */
 144 #define OPC_OUB_SAS_HW_EVENT_ACK                        2099    /* 0x833 */
 145 #define OPC_OUB_GET_DEVICE_INFO                         2100    /* 0x834 */
 146 /* spcv specific commands */
 147 #define OPC_OUB_PHY_START_RESP                          2052    /* 0x804 */
 148 #define OPC_OUB_PHY_STOP_RESP                           2053    /* 0x805 */
 149 #define OPC_OUB_SET_CONTROLLER_CONFIG                   2096    /* 0x830 */
 150 #define OPC_OUB_GET_CONTROLLER_CONFIG                   2097    /* 0x831 */
 151 #define OPC_OUB_GET_PHY_PROFILE                         2101    /* 0x835 */
 152 #define OPC_OUB_FLASH_OP_EXT                            2102    /* 0x836 */
 153 #define OPC_OUB_SET_PHY_PROFILE                         2103    /* 0x837 */
 154 #define OPC_OUB_KEK_MANAGEMENT_RESP                     2304    /* 0x900 */
 155 #define OPC_OUB_DEK_MANAGEMENT_RESP                     2305    /* 0x901 */
 156 #define OPC_OUB_SSP_COALESCED_COMP_RESP                 2306    /* 0x902 */
 157
 158 /* for phy start*/
 159 #define SSC_DISABLE_15                  (0x01 << 16)
 160 #define SSC_DISABLE_30                  (0x02 << 16)
 161 #define SSC_DISABLE_60                  (0x04 << 16)
 162 #define SAS_ASE                         (0x01 << 15)
 163 #define SPINHOLD_DISABLE                (0x00 << 14)
 164 #define SPINHOLD_ENABLE                 (0x01 << 14)
 165 #define LINKMODE_SAS                    (0x01 << 12)
 166 #define LINKMODE_DSATA                  (0x02 << 12)
 167 #define LINKMODE_AUTO                   (0x03 << 12)
 168 #define LINKRATE_15                     (0x01 << 8)
 169 #define LINKRATE_30                     (0x02 << 8)
 170 #define LINKRATE_60                     (0x06 << 8)
 171 #define LINKRATE_120                    (0x08 << 8)
 172
 173 /* phy_profile */
 174 #define SAS_PHY_ANALOG_SETTINGS_PAGE    0x04
 175 #define PHY_DWORD_LENGTH                0xC
 176
 177 /* Thermal related */
 178 #define THERMAL_ENABLE                  0x1
 179 #define THERMAL_LOG_ENABLE              0x1
 180 #define THERMAL_OP_CODE                 0x6
 181 #define LTEMPHIL                         70
 182 #define RTEMPHIL                        100
 183
 184 /* Encryption info */
 185 #define SCRATCH_PAD3_ENC_DISABLED       0x00000000
 186 #define SCRATCH_PAD3_ENC_DIS_ERR        0x00000001
 187 #define SCRATCH_PAD3_ENC_ENA_ERR        0x00000002
 188 #define SCRATCH_PAD3_ENC_READY          0x00000003
 189 #define SCRATCH_PAD3_ENC_MASK           SCRATCH_PAD3_ENC_READY
 190
 191 #define SCRATCH_PAD3_XTS_ENABLED                (1 << 14)
 192 #define SCRATCH_PAD3_SMA_ENABLED                (1 << 4)
 193 #define SCRATCH_PAD3_SMB_ENABLED                (1 << 5)
 194 #define SCRATCH_PAD3_SMF_ENABLED                0
 195 #define SCRATCH_PAD3_SM_MASK                    0x000000F0
 196 #define SCRATCH_PAD3_ERR_CODE                   0x00FF0000
 197
 198 #define SEC_MODE_SMF                            0x0
 199 #define SEC_MODE_SMA                            0x100
 200 #define SEC_MODE_SMB                            0x200
 201 #define CIPHER_MODE_ECB                         0x00000001
 202 #define CIPHER_MODE_XTS                         0x00000002
 203 #define KEK_MGMT_SUBOP_KEYCARDUPDATE            0x4
 204
 205 /* SAS protocol timer configuration page */
 206 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE  0x04
 207 #define STP_MCT_TMO                     32
 208 #define SSP_MCT_TMO                     32
 209 #define SAS_MAX_OPEN_TIME                               5
 210 #define SMP_MAX_CONN_TIMER              0xFF
 211 #define STP_FRM_TIMER                   0
 212 #define STP_IDLE_TIME                   5 /* 5 us; controller default */
 213 #define SAS_MFD                         0
 214 #define SAS_OPNRJT_RTRY_INTVL           2
 215 #define SAS_DOPNRJT_RTRY_TMO            128
 216 #define SAS_COPNRJT_RTRY_TMO            128
 217
 218 /* for phy state */
 219 #define PHY_STATE_LINK_UP_SPCV          0x2
 220 /*
 221   Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
 222   Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
 223   is DOPNRJT_RTRY_TMO
 224 */
 225 #define SAS_DOPNRJT_RTRY_THR            23438
 226 #define SAS_COPNRJT_RTRY_THR            23438
 227 #define SAS_MAX_AIP                     0x200000
 228 #define IT_NEXUS_TIMEOUT       0x7D0
 229 #define PORT_RECOVERY_TIMEOUT  ((IT_NEXUS_TIMEOUT/100) + 30)
 230
 231 struct mpi_msg_hdr {
 232         __le32  header; /* Bits [11:0] - Message operation code */
 233         /* Bits [15:12] - Message Category */
 234         /* Bits [21:16] - Outboundqueue ID for the
 235         operation completion message */
 236         /* Bits [23:22] - Reserved */
 237         /* Bits [28:24] - Buffer Count, indicates how
 238         many buffer are allocated for the massage */
 239         /* Bits [30:29] - Reserved */
 240         /* Bits [31] - Message Valid bit */
 241 } __attribute__((packed, aligned(4)));
 242
 243 /*
 244  * brief the data structure of PHY Start Command
 245  * use to describe enable the phy (128 bytes)
 246  */
 247 struct phy_start_req {
 248         __le32  tag;
 249         __le32  ase_sh_lm_slr_phyid;
 250         struct sas_identify_frame sas_identify; /* 28 Bytes */
 251         __le32 spasti;
 252         u32     reserved[21];
 253 } __attribute__((packed, aligned(4)));
 254
 255 /*
 256  * brief the data structure of PHY Start Command
 257  * use to disable the phy (128 bytes)
 258  */
 259 struct phy_stop_req {
 260         __le32  tag;
 261         __le32  phy_id;
 262         u32     reserved[29];
 263 } __attribute__((packed, aligned(4)));
 264
 265 /* set device bits fis - device to host */
 266 struct set_dev_bits_fis {
 267         u8      fis_type;       /* 0xA1*/
 268         u8      n_i_pmport;
 269         /* b7 : n Bit. Notification bit. If set device needs attention. */
 270         /* b6 : i Bit. Interrupt Bit */
 271         /* b5-b4: reserved2 */
 272         /* b3-b0: PM Port */
 273         u8      status;
 274         u8      error;
 275         u32     _r_a;
 276 } __attribute__ ((packed));
 277 /* PIO setup FIS - device to host */
 278 struct pio_setup_fis {
 279         u8      fis_type;       /* 0x5f */
 280         u8      i_d_pmPort;
 281         /* b7 : reserved */
 282         /* b6 : i bit. Interrupt bit */
 283         /* b5 : d bit. data transfer direction. set to 1 for device to host
 284         xfer */
 285         /* b4 : reserved */
 286         /* b3-b0: PM Port */
 287         u8      status;
 288         u8      error;
 289         u8      lbal;
 290         u8      lbam;
 291         u8      lbah;
 292         u8      device;
 293         u8      lbal_exp;
 294         u8      lbam_exp;
 295         u8      lbah_exp;
 296         u8      _r_a;
 297         u8      sector_count;
 298         u8      sector_count_exp;
 299         u8      _r_b;
 300         u8      e_status;
 301         u8      _r_c[2];
 302         u8      transfer_count;
 303 } __attribute__ ((packed));
 304
 305 /*
 306  * brief the data structure of SATA Completion Response
 307  * use to describe the sata task response (64 bytes)
 308  */
 309 struct sata_completion_resp {
 310         __le32  tag;
 311         __le32  status;
 312         __le32  param;
 313         u32     sata_resp[12];
 314 } __attribute__((packed, aligned(4)));
 315
 316 /*
 317  * brief the data structure of SAS HW Event Notification
 318  * use to alert the host about the hardware event(64 bytes)
 319  */
 320 /* updated outbound struct for spcv */
 321
 322 struct hw_event_resp {
 323         __le32  lr_status_evt_portid;
 324         __le32  evt_param;
 325         __le32  phyid_npip_portstate;
 326         struct sas_identify_frame       sas_identify;
 327         struct dev_to_host_fis  sata_fis;
 328 } __attribute__((packed, aligned(4)));
 329
 330 /*
 331  * brief the data structure for thermal event notification
 332  */
 333
 334 struct thermal_hw_event {
 335         __le32  thermal_event;
 336         __le32  rht_lht;
 337 } __attribute__((packed, aligned(4)));
 338
 339 /*
 340  * brief the data structure of REGISTER DEVICE Command
 341  * use to describe MPI REGISTER DEVICE Command (64 bytes)
 342  */
 343
 344 struct reg_dev_req {
 345         __le32  tag;
 346         __le32  phyid_portid;
 347         __le32  dtype_dlr_mcn_ir_retry;
 348         __le32  firstburstsize_ITNexustimeout;
 349         u8      sas_addr[SAS_ADDR_SIZE];
 350         __le32  upper_device_id;
 351         u32     reserved[24];
 352 } __attribute__((packed, aligned(4)));
 353
 354 /*
 355  * brief the data structure of DEREGISTER DEVICE Command
 356  * use to request spc to remove all internal resources associated
 357  * with the device id (64 bytes)
 358  */
 359
 360 struct dereg_dev_req {
 361         __le32  tag;
 362         __le32  device_id;
 363         u32     reserved[29];
 364 } __attribute__((packed, aligned(4)));
 365
 366 /*
 367  * brief the data structure of DEVICE_REGISTRATION Response
 368  * use to notify the completion of the device registration (64 bytes)
 369  */
 370 struct dev_reg_resp {
 371         __le32  tag;
 372         __le32  status;
 373         __le32  device_id;
 374         u32     reserved[12];
 375 } __attribute__((packed, aligned(4)));
 376
 377 /*
 378  * brief the data structure of Local PHY Control Command
 379  * use to issue PHY CONTROL to local phy (64 bytes)
 380  */
 381 struct local_phy_ctl_req {
 382         __le32  tag;
 383         __le32  phyop_phyid;
 384         u32     reserved1[29];
 385 } __attribute__((packed, aligned(4)));
 386
 387 /**
 388  * brief the data structure of Local Phy Control Response
 389  * use to describe MPI Local Phy Control Response (64 bytes)
 390  */
 391  struct local_phy_ctl_resp {
 392         __le32  tag;
 393         __le32  phyop_phyid;
 394         __le32  status;
 395         u32     reserved[12];
 396 } __attribute__((packed, aligned(4)));
 397
 398 #define OP_BITS 0x0000FF00
 399 #define ID_BITS 0x000000FF
 400
 401 /*
 402  * brief the data structure of PORT Control Command
 403  * use to control port properties (64 bytes)
 404  */
 405
 406 struct port_ctl_req {
 407         __le32  tag;
 408         __le32  portop_portid;
 409         __le32  param0;
 410         __le32  param1;
 411         u32     reserved1[27];
 412 } __attribute__((packed, aligned(4)));
 413
 414 /*
 415  * brief the data structure of HW Event Ack Command
 416  * use to acknowledge receive HW event (64 bytes)
 417  */
 418 struct hw_event_ack_req {
 419         __le32  tag;
 420         __le32  phyid_sea_portid;
 421         __le32  param0;
 422         __le32  param1;
 423         u32     reserved1[27];
 424 } __attribute__((packed, aligned(4)));
 425
 426 /*
 427  * brief the data structure of PHY_START Response Command
 428  * indicates the completion of PHY_START command (64 bytes)
 429  */
 430 struct phy_start_resp {
 431         __le32  tag;
 432         __le32  status;
 433         __le32  phyid;
 434         u32     reserved[12];
 435 } __attribute__((packed, aligned(4)));
 436
 437 /*
 438  * brief the data structure of PHY_STOP Response Command
 439  * indicates the completion of PHY_STOP command (64 bytes)
 440  */
 441 struct phy_stop_resp {
 442         __le32  tag;
 443         __le32  status;
 444         __le32  phyid;
 445         u32     reserved[12];
 446 } __attribute__((packed, aligned(4)));
 447
 448 /*
 449  * brief the data structure of SSP Completion Response
 450  * use to indicate a SSP Completion (n bytes)
 451  */
 452 struct ssp_completion_resp {
 453         __le32  tag;
 454         __le32  status;
 455         __le32  param;
 456         __le32  ssptag_rescv_rescpad;
 457         struct ssp_response_iu ssp_resp_iu;
 458         __le32  residual_count;
 459 } __attribute__((packed, aligned(4)));
 460
 461 #define SSP_RESCV_BIT   0x00010000
 462
 463 /*
 464  * brief the data structure of SATA EVNET response
 465  * use to indicate a SATA Completion (64 bytes)
 466  */
 467 struct sata_event_resp {
 468         __le32 tag;
 469         __le32 event;
 470         __le32 port_id;
 471         __le32 device_id;
 472         u32 reserved;
 473         __le32 event_param0;
 474         __le32 event_param1;
 475         __le32 sata_addr_h32;
 476         __le32 sata_addr_l32;
 477         __le32 e_udt1_udt0_crc;
 478         __le32 e_udt5_udt4_udt3_udt2;
 479         __le32 a_udt1_udt0_crc;
 480         __le32 a_udt5_udt4_udt3_udt2;
 481         __le32 hwdevid_diferr;
 482         __le32 err_framelen_byteoffset;
 483         __le32 err_dataframe;
 484 } __attribute__((packed, aligned(4)));
 485
 486 /*
 487  * brief the data structure of SSP EVNET esponse
 488  * use to indicate a SSP Completion (64 bytes)
 489  */
 490 struct ssp_event_resp {
 491         __le32 tag;
 492         __le32 event;
 493         __le32 port_id;
 494         __le32 device_id;
 495         __le32 ssp_tag;
 496         __le32 event_param0;
 497         __le32 event_param1;
 498         __le32 sas_addr_h32;
 499         __le32 sas_addr_l32;
 500         __le32 e_udt1_udt0_crc;
 501         __le32 e_udt5_udt4_udt3_udt2;
 502         __le32 a_udt1_udt0_crc;
 503         __le32 a_udt5_udt4_udt3_udt2;
 504         __le32 hwdevid_diferr;
 505         __le32 err_framelen_byteoffset;
 506         __le32 err_dataframe;
 507 } __attribute__((packed, aligned(4)));
 508
 509 /**
 510  * brief the data structure of General Event Notification Response
 511  * use to describe MPI General Event Notification Response (64 bytes)
 512  */
 513 struct general_event_resp {
 514         __le32  status;
 515         __le32  inb_IOMB_payload[14];
 516 } __attribute__((packed, aligned(4)));
 517
 518 #define GENERAL_EVENT_PAYLOAD   14
 519 #define OPCODE_BITS     0x00000fff
 520
 521 /*
 522  * brief the data structure of SMP Request Command
 523  * use to describe MPI SMP REQUEST Command (64 bytes)
 524  */
 525 struct smp_req {
 526         __le32  tag;
 527         __le32  device_id;
 528         __le32  len_ip_ir;
 529         /* Bits [0] - Indirect response */
 530         /* Bits [1] - Indirect Payload */
 531         /* Bits [15:2] - Reserved */
 532         /* Bits [23:16] - direct payload Len */
 533         /* Bits [31:24] - Reserved */
 534         u8      smp_req16[16];
 535         union {
 536                 u8      smp_req[32];
 537                 struct {
 538                         __le64 long_req_addr;/* sg dma address, LE */
 539                         __le32 long_req_size;/* LE */
 540                         u32     _r_a;
 541                         __le64 long_resp_addr;/* sg dma address, LE */
 542                         __le32 long_resp_size;/* LE */
 543                         u32     _r_b;
 544                         } long_smp_req;/* sequencer extension */
 545         };
 546         __le32  rsvd[16];
 547 } __attribute__((packed, aligned(4)));
 548 /*
 549  * brief the data structure of SMP Completion Response
 550  * use to describe MPI SMP Completion Response (64 bytes)
 551  */
 552 struct smp_completion_resp {
 553         __le32  tag;
 554         __le32  status;
 555         __le32  param;
 556         u8      _r_a[252];
 557 } __attribute__((packed, aligned(4)));
 558
 559 /*
 560  *brief the data structure of SSP SMP SATA Abort Command
 561  * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
 562  */
 563 struct task_abort_req {
 564         __le32  tag;
 565         __le32  device_id;
 566         __le32  tag_to_abort;
 567         __le32  abort_all;
 568         u32     reserved[27];
 569 } __attribute__((packed, aligned(4)));
 570
 571 /* These flags used for SSP SMP & SATA Abort */
 572 #define ABORT_MASK              0x3
 573 #define ABORT_SINGLE            0x0
 574 #define ABORT_ALL               0x1
 575
 576 /**
 577  * brief the data structure of SSP SATA SMP Abort Response
 578  * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
 579  */
 580 struct task_abort_resp {
 581         __le32  tag;
 582         __le32  status;
 583         __le32  scp;
 584         u32     reserved[12];
 585 } __attribute__((packed, aligned(4)));
 586
 587 /**
 588  * brief the data structure of SAS Diagnostic Start/End Command
 589  * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
 590  */
 591 struct sas_diag_start_end_req {
 592         __le32  tag;
 593         __le32  operation_phyid;
 594         u32     reserved[29];
 595 } __attribute__((packed, aligned(4)));
 596
 597 /**
 598  * brief the data structure of SAS Diagnostic Execute Command
 599  * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
 600  */
 601 struct sas_diag_execute_req {
 602         __le32  tag;
 603         __le32  cmdtype_cmddesc_phyid;
 604         __le32  pat1_pat2;
 605         __le32  threshold;
 606         __le32  codepat_errmsk;
 607         __le32  pmon;
 608         __le32  pERF1CTL;
 609         u32     reserved[24];
 610 } __attribute__((packed, aligned(4)));
 611
 612 #define SAS_DIAG_PARAM_BYTES 24
 613
 614 /*
 615  * brief the data structure of Set Device State Command
 616  * use to describe MPI Set Device State Command (64 bytes)
 617  */
 618 struct set_dev_state_req {
 619         __le32  tag;
 620         __le32  device_id;
 621         __le32  nds;
 622         u32     reserved[28];
 623 } __attribute__((packed, aligned(4)));
 624
 625 /*
 626  * brief the data structure of SATA Start Command
 627  * use to describe MPI SATA IO Start Command (64 bytes)
 628  * Note: This structure is common for normal / encryption I/O
 629  */
 630
 631 struct sata_start_req {
 632         __le32  tag;
 633         __le32  device_id;
 634         __le32  data_len;
 635         __le32  ncqtag_atap_dir_m_dad;
 636         struct host_to_dev_fis  sata_fis;
 637         u32     reserved1;
 638         u32     reserved2;      /* dword 11. rsvd for normal I/O. */
 639                                 /* EPLE Descl for enc I/O */
 640         u32     addr_low;       /* dword 12. rsvd for enc I/O */
 641         u32     addr_high;      /* dword 13. reserved for enc I/O */
 642         __le32  len;            /* dword 14: length for normal I/O. */
 643                                 /* EPLE Desch for enc I/O */
 644         __le32  esgl;           /* dword 15. rsvd for enc I/O */
 645         __le32  atapi_scsi_cdb[4];      /* dword 16-19. rsvd for enc I/O */
 646         /* The below fields are reserved for normal I/O */
 647         __le32  key_index_mode; /* dword 20 */
 648         __le32  sector_cnt_enss;/* dword 21 */
 649         __le32  keytagl;        /* dword 22 */
 650         __le32  keytagh;        /* dword 23 */
 651         __le32  twk_val0;       /* dword 24 */
 652         __le32  twk_val1;       /* dword 25 */
 653         __le32  twk_val2;       /* dword 26 */
 654         __le32  twk_val3;       /* dword 27 */
 655         __le32  enc_addr_low;   /* dword 28. Encryption SGL address high */
 656         __le32  enc_addr_high;  /* dword 29. Encryption SGL address low */
 657         __le32  enc_len;        /* dword 30. Encryption length */
 658         __le32  enc_esgl;       /* dword 31. Encryption esgl bit */
 659 } __attribute__((packed, aligned(4)));
 660
 661 /**
 662  * brief the data structure of SSP INI TM Start Command
 663  * use to describe MPI SSP INI TM Start Command (64 bytes)
 664  */
 665 struct ssp_ini_tm_start_req {
 666         __le32  tag;
 667         __le32  device_id;
 668         __le32  relate_tag;
 669         __le32  tmf;
 670         u8      lun[8];
 671         __le32  ds_ads_m;
 672         u32     reserved[24];
 673 } __attribute__((packed, aligned(4)));
 674
 675 struct ssp_info_unit {
 676         u8      lun[8];/* SCSI Logical Unit Number */
 677         u8      reserved1;/* reserved */
 678         u8      efb_prio_attr;
 679         /* B7 : enabledFirstBurst */
 680         /* B6-3 : taskPriority */
 681         /* B2-0 : taskAttribute */
 682         u8      reserved2;      /* reserved */
 683         u8      additional_cdb_len;
 684         /* B7-2 : additional_cdb_len */
 685         /* B1-0 : reserved */
 686         u8      cdb[16];/* The SCSI CDB up to 16 bytes length */
 687 } __attribute__((packed, aligned(4)));
 688
 689 /**
 690  * brief the data structure of SSP INI IO Start Command
 691  * use to describe MPI SSP INI IO Start Command (64 bytes)
 692  * Note: This structure is common for normal / encryption I/O
 693  */
 694 struct ssp_ini_io_start_req {
 695         __le32  tag;
 696         __le32  device_id;
 697         __le32  data_len;
 698         __le32  dad_dir_m_tlr;
 699         struct ssp_info_unit    ssp_iu;
 700         __le32  addr_low;       /* dword 12: sgl low for normal I/O. */
 701                                 /* epl_descl for encryption I/O */
 702         __le32  addr_high;      /* dword 13: sgl hi for normal I/O */
 703                                 /* dpl_descl for encryption I/O */
 704         __le32  len;            /* dword 14: len for normal I/O. */
 705                                 /* edpl_desch for encryption I/O */
 706         __le32  esgl;           /* dword 15: ESGL bit for normal I/O. */
 707                                 /* user defined tag mask for enc I/O */
 708         /* The below fields are reserved for normal I/O */
 709         u8      udt[12];        /* dword 16-18 */
 710         __le32  sectcnt_ios;    /* dword 19 */
 711         __le32  key_cmode;      /* dword 20 */
 712         __le32  ks_enss;        /* dword 21 */
 713         __le32  keytagl;        /* dword 22 */
 714         __le32  keytagh;        /* dword 23 */
 715         __le32  twk_val0;       /* dword 24 */
 716         __le32  twk_val1;       /* dword 25 */
 717         __le32  twk_val2;       /* dword 26 */
 718         __le32  twk_val3;       /* dword 27 */
 719         __le32  enc_addr_low;   /* dword 28: Encryption sgl addr low */
 720         __le32  enc_addr_high;  /* dword 29: Encryption sgl addr hi */
 721         __le32  enc_len;        /* dword 30: Encryption length */
 722         __le32  enc_esgl;       /* dword 31: ESGL bit for encryption */
 723 } __attribute__((packed, aligned(4)));
 724
 725 /**
 726  * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
 727  * use to initiate SSP I/O operation with optional DIF/ENC
 728  */
 729 struct ssp_dif_enc_io_req {
 730         __le32  tag;
 731         __le32  device_id;
 732         __le32  data_len;
 733         __le32  dirMTlr;
 734         __le32  sspiu0;
 735         __le32  sspiu1;
 736         __le32  sspiu2;
 737         __le32  sspiu3;
 738         __le32  sspiu4;
 739         __le32  sspiu5;
 740         __le32  sspiu6;
 741         __le32  epl_des;
 742         __le32  dpl_desl_ndplr;
 743         __le32  dpl_desh;
 744         __le32  uum_uuv_bss_difbits;
 745         u8      udt[12];
 746         __le32  sectcnt_ios;
 747         __le32  key_cmode;
 748         __le32  ks_enss;
 749         __le32  keytagl;
 750         __le32  keytagh;
 751         __le32  twk_val0;
 752         __le32  twk_val1;
 753         __le32  twk_val2;
 754         __le32  twk_val3;
 755         __le32  addr_low;
 756         __le32  addr_high;
 757         __le32  len;
 758         __le32  esgl;
 759 } __attribute__((packed, aligned(4)));
 760
 761 /**
 762  * brief the data structure of Firmware download
 763  * use to describe MPI FW DOWNLOAD Command (64 bytes)
 764  */
 765 struct fw_flash_Update_req {
 766         __le32  tag;
 767         __le32  cur_image_offset;
 768         __le32  cur_image_len;
 769         __le32  total_image_len;
 770         u32     reserved0[7];
 771         __le32  sgl_addr_lo;
 772         __le32  sgl_addr_hi;
 773         __le32  len;
 774         __le32  ext_reserved;
 775         u32     reserved1[16];
 776 } __attribute__((packed, aligned(4)));
 777
 778 #define FWFLASH_IOMB_RESERVED_LEN 0x07
 779 /**
 780  * brief the data structure of FW_FLASH_UPDATE Response
 781  * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
 782  *
 783  */
 784  struct fw_flash_Update_resp {
 785         __le32  tag;
 786         __le32  status;
 787         u32     reserved[13];
 788 } __attribute__((packed, aligned(4)));
 789
 790 /**
 791  * brief the data structure of Get NVM Data Command
 792  * use to get data from NVM in HBA(64 bytes)
 793  */
 794 struct get_nvm_data_req {
 795         __le32  tag;
 796         __le32  len_ir_vpdd;
 797         __le32  vpd_offset;
 798         u32     reserved[8];
 799         __le32  resp_addr_lo;
 800         __le32  resp_addr_hi;
 801         __le32  resp_len;
 802         u32     reserved1[17];
 803 } __attribute__((packed, aligned(4)));
 804
 805 struct set_nvm_data_req {
 806         __le32  tag;
 807         __le32  len_ir_vpdd;
 808         __le32  vpd_offset;
 809         u32     reserved[8];
 810         __le32  resp_addr_lo;
 811         __le32  resp_addr_hi;
 812         __le32  resp_len;
 813         u32     reserved1[17];
 814 } __attribute__((packed, aligned(4)));
 815
 816 /**
 817  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 818  * use to modify controller configuration
 819  */
 820 struct set_ctrl_cfg_req {
 821         __le32  tag;
 822         __le32  cfg_pg[14];
 823         u32     reserved[16];
 824 } __attribute__((packed, aligned(4)));
 825
 826 /**
 827  * brief the data structure for GET CONTROLLER CONFIG COMMAND
 828  * use to get controller configuration page
 829  */
 830 struct get_ctrl_cfg_req {
 831         __le32  tag;
 832         __le32  pgcd;
 833         __le32  int_vec;
 834         u32     reserved[28];
 835 } __attribute__((packed, aligned(4)));
 836
 837 /**
 838  * brief the data structure for KEK_MANAGEMENT COMMAND
 839  * use for KEK management
 840  */
 841 struct kek_mgmt_req {
 842         __le32  tag;
 843         __le32  new_curidx_ksop;
 844         u32     reserved;
 845         __le32  kblob[12];
 846         u32     reserved1[16];
 847 } __attribute__((packed, aligned(4)));
 848
 849 /**
 850  * brief the data structure for DEK_MANAGEMENT COMMAND
 851  * use for DEK management
 852  */
 853 struct dek_mgmt_req {
 854         __le32  tag;
 855         __le32  kidx_dsop;
 856         __le32  dekidx;
 857         __le32  addr_l;
 858         __le32  addr_h;
 859         __le32  nent;
 860         __le32  dbf_tblsize;
 861         u32     reserved[24];
 862 } __attribute__((packed, aligned(4)));
 863
 864 /**
 865  * brief the data structure for SET PHY PROFILE COMMAND
 866  * use to retrive phy specific information
 867  */
 868 struct set_phy_profile_req {
 869         __le32  tag;
 870         __le32  ppc_phyid;
 871         u32     reserved[29];
 872 } __attribute__((packed, aligned(4)));
 873
 874 /**
 875  * brief the data structure for GET PHY PROFILE COMMAND
 876  * use to retrive phy specific information
 877  */
 878 struct get_phy_profile_req {
 879         __le32  tag;
 880         __le32  ppc_phyid;
 881         __le32  profile[29];
 882 } __attribute__((packed, aligned(4)));
 883
 884 /**
 885  * brief the data structure for EXT FLASH PARTITION
 886  * use to manage ext flash partition
 887  */
 888 struct ext_flash_partition_req {
 889         __le32  tag;
 890         __le32  cmd;
 891         __le32  offset;
 892         __le32  len;
 893         u32     reserved[7];
 894         __le32  addr_low;
 895         __le32  addr_high;
 896         __le32  len1;
 897         __le32  ext;
 898         u32     reserved1[16];
 899 } __attribute__((packed, aligned(4)));
 900
 901 #define TWI_DEVICE      0x0
 902 #define C_SEEPROM       0x1
 903 #define VPD_FLASH       0x4
 904 #define AAP1_RDUMP      0x5
 905 #define IOP_RDUMP       0x6
 906 #define EXPAN_ROM       0x7
 907
 908 #define IPMode          0x80000000
 909 #define NVMD_TYPE       0x0000000F
 910 #define NVMD_STAT       0x0000FFFF
 911 #define NVMD_LEN        0xFF000000
 912 /**
 913  * brief the data structure of Get NVMD Data Response
 914  * use to describe MPI Get NVMD Data Response (64 bytes)
 915  */
 916 struct get_nvm_data_resp {
 917         __le32          tag;
 918         __le32          ir_tda_bn_dps_das_nvm;
 919         __le32          dlen_status;
 920         __le32          nvm_data[12];
 921 } __attribute__((packed, aligned(4)));
 922
 923 /**
 924  * brief the data structure of SAS Diagnostic Start/End Response
 925  * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
 926  *
 927  */
 928 struct sas_diag_start_end_resp {
 929         __le32          tag;
 930         __le32          status;
 931         u32             reserved[13];
 932 } __attribute__((packed, aligned(4)));
 933
 934 /**
 935  * brief the data structure of SAS Diagnostic Execute Response
 936  * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
 937  *
 938  */
 939 struct sas_diag_execute_resp {
 940         __le32          tag;
 941         __le32          cmdtype_cmddesc_phyid;
 942         __le32          Status;
 943         __le32          ReportData;
 944         u32             reserved[11];
 945 } __attribute__((packed, aligned(4)));
 946
 947 /**
 948  * brief the data structure of Set Device State Response
 949  * use to describe MPI Set Device State Response (64 bytes)
 950  *
 951  */
 952 struct set_dev_state_resp {
 953         __le32          tag;
 954         __le32          status;
 955         __le32          device_id;
 956         __le32          pds_nds;
 957         u32             reserved[11];
 958 } __attribute__((packed, aligned(4)));
 959
 960 /* new outbound structure for spcv - begins */
 961 /**
 962  * brief the data structure for SET CONTROLLER CONFIG COMMAND
 963  * use to modify controller configuration
 964  */
 965 struct set_ctrl_cfg_resp {
 966         __le32 tag;
 967         __le32 status;
 968         __le32 err_qlfr_pgcd;
 969         u32 reserved[12];
 970 } __attribute__((packed, aligned(4)));
 971
 972 struct get_ctrl_cfg_resp {
 973         __le32 tag;
 974         __le32 status;
 975         __le32 err_qlfr;
 976         __le32 confg_page[12];
 977 } __attribute__((packed, aligned(4)));
 978
 979 struct kek_mgmt_resp {
 980         __le32 tag;
 981         __le32 status;
 982         __le32 kidx_new_curr_ksop;
 983         __le32 err_qlfr;
 984         u32 reserved[11];
 985 } __attribute__((packed, aligned(4)));
 986
 987 struct dek_mgmt_resp {
 988         __le32 tag;
 989         __le32 status;
 990         __le32 kekidx_tbls_dsop;
 991         __le32 dekidx;
 992         __le32 err_qlfr;
 993         u32 reserved[10];
 994 } __attribute__((packed, aligned(4)));
 995
 996 struct get_phy_profile_resp {
 997         __le32 tag;
 998         __le32 status;
 999         __le32 ppc_phyid;
1000         __le32 ppc_specific_rsp[12];
1001 } __attribute__((packed, aligned(4)));
1002
1003 struct flash_op_ext_resp {
1004         __le32 tag;
1005         __le32 cmd;
1006         __le32 status;
1007         __le32 epart_size;
1008         __le32 epart_sect_size;
1009         u32 reserved[10];
1010 } __attribute__((packed, aligned(4)));
1011
1012 struct set_phy_profile_resp {
1013         __le32 tag;
1014         __le32 status;
1015         __le32 ppc_phyid;
1016         __le32 ppc_specific_rsp[12];
1017 } __attribute__((packed, aligned(4)));
1018
1019 struct ssp_coalesced_comp_resp {
1020         __le32 coal_cnt;
1021         __le32 tag0;
1022         __le32 ssp_tag0;
1023         __le32 tag1;
1024         __le32 ssp_tag1;
1025         __le32 add_tag_ssp_tag[10];
1026 } __attribute__((packed, aligned(4)));
1027
1028 /* new outbound structure for spcv - ends */
1029
1030 /* brief data structure for SAS protocol timer configuration page.
1031  *
1032  */
1033 struct SASProtocolTimerConfig {
1034         __le32 pageCode;                        /* 0 */
1035         __le32 MST_MSI;                         /* 1 */
1036         __le32 STP_SSP_MCT_TMO;                 /* 2 */
1037         __le32 STP_FRM_TMO;                     /* 3 */
1038         __le32 STP_IDLE_TMO;                    /* 4 */
1039         __le32 OPNRJT_RTRY_INTVL;               /* 5 */
1040         __le32 Data_Cmd_OPNRJT_RTRY_TMO;        /* 6 */
1041         __le32 Data_Cmd_OPNRJT_RTRY_THR;        /* 7 */
1042         __le32 MAX_AIP;                         /* 8 */
1043 } __attribute__((packed, aligned(4)));
1044
1045 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1046
1047 #define NDS_BITS 0x0F
1048 #define PDS_BITS 0xF0
1049
1050 /*
1051  * HW Events type
1052  */
1053
1054 #define HW_EVENT_RESET_START                    0x01
1055 #define HW_EVENT_CHIP_RESET_COMPLETE            0x02
1056 #define HW_EVENT_PHY_STOP_STATUS                0x03
1057 #define HW_EVENT_SAS_PHY_UP                     0x04
1058 #define HW_EVENT_SATA_PHY_UP                    0x05
1059 #define HW_EVENT_SATA_SPINUP_HOLD               0x06
1060 #define HW_EVENT_PHY_DOWN                       0x07
1061 #define HW_EVENT_PORT_INVALID                   0x08
1062 #define HW_EVENT_BROADCAST_CHANGE               0x09
1063 #define HW_EVENT_PHY_ERROR                      0x0A
1064 #define HW_EVENT_BROADCAST_SES                  0x0B
1065 #define HW_EVENT_INBOUND_CRC_ERROR              0x0C
1066 #define HW_EVENT_HARD_RESET_RECEIVED            0x0D
1067 #define HW_EVENT_MALFUNCTION                    0x0E
1068 #define HW_EVENT_ID_FRAME_TIMEOUT               0x0F
1069 #define HW_EVENT_BROADCAST_EXP                  0x10
1070 #define HW_EVENT_PHY_START_STATUS               0x11
1071 #define HW_EVENT_LINK_ERR_INVALID_DWORD         0x12
1072 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR       0x13
1073 #define HW_EVENT_LINK_ERR_CODE_VIOLATION        0x14
1074 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH   0x15
1075 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED      0x16
1076 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO        0x17
1077 #define HW_EVENT_PORT_RECOVER                   0x18
1078 #define HW_EVENT_PORT_RESET_TIMER_TMO           0x19
1079 #define HW_EVENT_PORT_RESET_COMPLETE            0x20
1080 #define EVENT_BROADCAST_ASYNCH_EVENT            0x21
1081
1082 /* port state */
1083 #define PORT_NOT_ESTABLISHED                    0x00
1084 #define PORT_VALID                              0x01
1085 #define PORT_LOSTCOMM                           0x02
1086 #define PORT_IN_RESET                           0x04
1087 #define PORT_3RD_PARTY_RESET                    0x07
1088 #define PORT_INVALID                            0x08
1089
1090 /*
1091  * SSP/SMP/SATA IO Completion Status values
1092  */
1093
1094 #define IO_SUCCESS                              0x00
1095 #define IO_ABORTED                              0x01
1096 #define IO_OVERFLOW                             0x02
1097 #define IO_UNDERFLOW                            0x03
1098 #define IO_FAILED                               0x04
1099 #define IO_ABORT_RESET                          0x05
1100 #define IO_NOT_VALID                            0x06
1101 #define IO_NO_DEVICE                            0x07
1102 #define IO_ILLEGAL_PARAMETER                    0x08
1103 #define IO_LINK_FAILURE                         0x09
1104 #define IO_PROG_ERROR                           0x0A
1105
1106 #define IO_EDC_IN_ERROR                         0x0B
1107 #define IO_EDC_OUT_ERROR                        0x0C
1108 #define IO_ERROR_HW_TIMEOUT                     0x0D
1109 #define IO_XFER_ERROR_BREAK                     0x0E
1110 #define IO_XFER_ERROR_PHY_NOT_READY             0x0F
1111 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED        0x10
1112 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION                0x11
1113 #define IO_OPEN_CNX_ERROR_BREAK                         0x12
1114 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS                 0x13
1115 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION               0x14
1116 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1117 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY            0x16
1118 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION             0x17
1119 /* This error code 0x18 is not used on SPCv */
1120 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR                 0x18
1121 #define IO_XFER_ERROR_NAK_RECEIVED                      0x19
1122 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT                   0x1A
1123 #define IO_XFER_ERROR_PEER_ABORTED                      0x1B
1124 #define IO_XFER_ERROR_RX_FRAME                          0x1C
1125 #define IO_XFER_ERROR_DMA                               0x1D
1126 #define IO_XFER_ERROR_CREDIT_TIMEOUT                    0x1E
1127 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT                 0x1F
1128 #define IO_XFER_ERROR_SATA                              0x20
1129
1130 /* This error code 0x22 is not used on SPCv */
1131 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST               0x22
1132 #define IO_XFER_ERROR_REJECTED_NCQ_MODE                 0x21
1133 #define IO_XFER_ERROR_ABORTED_NCQ_MODE                  0x23
1134 #define IO_XFER_OPEN_RETRY_TIMEOUT                      0x24
1135 /* This error code 0x25 is not used on SPCv */
1136 #define IO_XFER_SMP_RESP_CONNECTION_ERROR               0x25
1137 #define IO_XFER_ERROR_UNEXPECTED_PHASE                  0x26
1138 #define IO_XFER_ERROR_XFER_RDY_OVERRUN                  0x27
1139 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED             0x28
1140 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT         0x30
1141
1142 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1143 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK    0x31
1144 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1145
1146 #define IO_XFER_ERROR_OFFSET_MISMATCH                   0x34
1147 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN                0x35
1148 #define IO_XFER_CMD_FRAME_ISSUED                        0x36
1149 #define IO_ERROR_INTERNAL_SMP_RESOURCE                  0x37
1150 #define IO_PORT_IN_RESET                                0x38
1151 #define IO_DS_NON_OPERATIONAL                           0x39
1152 #define IO_DS_IN_RECOVERY                               0x3A
1153 #define IO_TM_TAG_NOT_FOUND                             0x3B
1154 #define IO_XFER_PIO_SETUP_ERROR                         0x3C
1155 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR                    0x3D
1156 #define IO_DS_IN_ERROR                                  0x3E
1157 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY              0x3F
1158 #define IO_ABORT_IN_PROGRESS                            0x40
1159 #define IO_ABORT_DELAYED                                0x41
1160 #define IO_INVALID_LENGTH                               0x42
1161
1162 /********** additional response event values *****************/
1163
1164 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT          0x43
1165 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED    0x44
1166 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO        0x45
1167 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST         0x46
1168 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE    0x47
1169 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1170 #define IO_DS_INVALID                                   0x49
1171 /* WARNING: the value is not contiguous from here */
1172 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR     0x52
1173 #define IO_XFER_DMA_ACTIVATE_TIMEOUT            0x53
1174 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR        0x54
1175 #define MPI_IO_RQE_BUSY_FULL                    0x55
1176 #define IO_XFER_ERR_EOB_DATA_OVERRUN            0x56
1177 #define IO_XFR_ERROR_INVALID_SSP_RSP_FRAME      0x57
1178 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED        0x58
1179
1180 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE         0x1004
1181 #define MPI_ERR_ATAPI_DEVICE_BUSY               0x1024
1182
1183 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS         0x2040
1184 /*
1185  * An encryption IO request failed due to DEK Key Tag mismatch.
1186  * The key tag supplied in the encryption IOMB does not match with
1187  * the Key Tag in the referenced DEK Entry.
1188  */
1189 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH       0x2041
1190 #define IO_XFR_ERROR_CIPHER_MODE_INVALID        0x2042
1191 /*
1192  * An encryption I/O request failed because the initial value (IV)
1193  * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1194  */
1195 #define IO_XFR_ERROR_DEK_IV_MISMATCH            0x2043
1196 /* An encryption I/O request failed due to an internal RAM ECC or
1197  * interface error while unwrapping the DEK. */
1198 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR    0x2044
1199 /* An encryption I/O request failed due to an internal RAM ECC or
1200  * interface error while unwrapping the DEK. */
1201 #define IO_XFR_ERROR_INTERNAL_RAM               0x2045
1202 /*
1203  * An encryption I/O request failed
1204  * because the DEK index specified in the I/O was outside the bounds of
1205  * the total number of entries in the host DEK table.
1206  */
1207 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1208
1209 /* define DIF IO response error status code */
1210 #define IO_XFR_ERROR_DIF_MISMATCH                       0x3000
1211 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH       0x3001
1212 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH         0x3002
1213 #define IO_XFR_ERROR_DIF_CRC_MISMATCH                   0x3003
1214
1215 /* define operator management response status and error qualifier code */
1216 #define OPR_MGMT_OP_NOT_SUPPORTED                       0x2060
1217 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL          0x2061
1218 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND           0x2062
1219 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH         0x2063
1220 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED       0x2064
1221 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL            0x2022
1222 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE    0x2023
1223 /***************** additional response event values ***************/
1224
1225 /* WARNING: This error code must always be the last number.
1226  * If you add error code, modify this code also
1227  * It is used as an index
1228  */
1229 #define IO_ERROR_UNKNOWN_GENERIC                        0x2023
1230
1231 /* MSGU CONFIGURATION TABLE*/
1232
1233 #define SPCv_MSGU_CFG_TABLE_UPDATE              0x001
1234 #define SPCv_MSGU_CFG_TABLE_RESET               0x002
1235 #define SPCv_MSGU_CFG_TABLE_FREEZE              0x004
1236 #define SPCv_MSGU_CFG_TABLE_UNFREEZE            0x008
1237 #define MSGU_IBDB_SET                           0x00
1238 #define MSGU_HOST_INT_STATUS                    0x08
1239 #define MSGU_HOST_INT_MASK                      0x0C
1240 #define MSGU_IOPIB_INT_STATUS                   0x18
1241 #define MSGU_IOPIB_INT_MASK                     0x1C
1242 #define MSGU_IBDB_CLEAR                         0x20
1243
1244 #define MSGU_MSGU_CONTROL                       0x24
1245 #define MSGU_ODR                                0x20
1246 #define MSGU_ODCR                               0x28
1247
1248 #define MSGU_ODMR                               0x30
1249 #define MSGU_ODMR_U                             0x34
1250 #define MSGU_ODMR_CLR                           0x38
1251 #define MSGU_ODMR_CLR_U                         0x3C
1252 #define MSGU_OD_RSVD                            0x40
1253
1254 #define MSGU_SCRATCH_PAD_0                      0x44
1255 #define MSGU_SCRATCH_PAD_1                      0x48
1256 #define MSGU_SCRATCH_PAD_2                      0x4C
1257 #define MSGU_SCRATCH_PAD_3                      0x50
1258 #define MSGU_HOST_SCRATCH_PAD_0                 0x54
1259 #define MSGU_HOST_SCRATCH_PAD_1                 0x58
1260 #define MSGU_HOST_SCRATCH_PAD_2                 0x5C
1261 #define MSGU_HOST_SCRATCH_PAD_3                 0x60
1262 #define MSGU_HOST_SCRATCH_PAD_4                 0x64
1263 #define MSGU_HOST_SCRATCH_PAD_5                 0x68
1264 #define MSGU_HOST_SCRATCH_PAD_6                 0x6C
1265 #define MSGU_HOST_SCRATCH_PAD_7                 0x70
1266
1267 /* bit definition for ODMR register */
1268 #define ODMR_MASK_ALL                   0xFFFFFFFF/* mask all
1269                                         interrupt vector */
1270 #define ODMR_CLEAR_ALL                  0       /* clear all
1271                                         interrupt vector */
1272 /* bit definition for ODCR register */
1273 #define ODCR_CLEAR_ALL                  0xFFFFFFFF /* mask all
1274                                         interrupt vector*/
1275 /* MSIX Interupts */
1276 #define MSIX_TABLE_OFFSET               0x2000
1277 #define MSIX_TABLE_ELEMENT_SIZE         0x10
1278 #define MSIX_INTERRUPT_CONTROL_OFFSET   0xC
1279 #define MSIX_TABLE_BASE                 (MSIX_TABLE_OFFSET + \
1280                                         MSIX_INTERRUPT_CONTROL_OFFSET)
1281 #define MSIX_INTERRUPT_DISABLE          0x1
1282 #define MSIX_INTERRUPT_ENABLE           0x0
1283
1284 /* state definition for Scratch Pad1 register */
1285 #define SCRATCH_PAD_RAAE_READY          0x3
1286 #define SCRATCH_PAD_ILA_READY           0xC
1287 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS   0x0
1288 #define SCRATCH_PAD_IOP0_READY          0xC00
1289 #define SCRATCH_PAD_IOP1_READY          0x3000
1290
1291 /* boot loader state */
1292 #define SCRATCH_PAD1_BOOTSTATE_MASK             0x70    /* Bit 4-6 */
1293 #define SCRATCH_PAD1_BOOTSTATE_SUCESS           0x0     /* Load successful */
1294 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM      0x10    /* HDA SEEPROM */
1295 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP    0x20    /* HDA BootStrap Pins */
1296 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET    0x30    /* HDA Soft Reset */
1297 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR       0x40    /* HDA critical error */
1298 #define SCRATCH_PAD1_BOOTSTATE_R1               0x50    /* Reserved */
1299 #define SCRATCH_PAD1_BOOTSTATE_R2               0x60    /* Reserved */
1300 #define SCRATCH_PAD1_BOOTSTATE_FATAL            0x70    /* Fatal Error */
1301
1302  /* state definition for Scratch Pad2 register */
1303 #define SCRATCH_PAD2_POR                0x00    /* power on state */
1304 #define SCRATCH_PAD2_SFR                0x01    /* soft reset state */
1305 #define SCRATCH_PAD2_ERR                0x02    /* error state */
1306 #define SCRATCH_PAD2_RDY                0x03    /* ready state */
1307 #define SCRATCH_PAD2_FWRDY_RST          0x04    /* FW rdy for soft reset flag */
1308 #define SCRATCH_PAD2_IOPRDY_RST         0x08    /* IOP ready for soft reset */
1309 #define SCRATCH_PAD2_STATE_MASK         0xFFFFFFF4 /* ScratchPad 2
1310  Mask, bit1-0 State */
1311 #define SCRATCH_PAD2_RESERVED           0x000003FC/* Scratch Pad1
1312  Reserved bit 2 to 9 */
1313
1314 #define SCRATCH_PAD_ERROR_MASK          0xFFFFFC00 /* Error mask bits */
1315 #define SCRATCH_PAD_STATE_MASK          0x00000003 /* State Mask bits */
1316
1317 /* main configuration offset - byte offset */
1318 #define MAIN_SIGNATURE_OFFSET           0x00 /* DWORD 0x00 */
1319 #define MAIN_INTERFACE_REVISION         0x04 /* DWORD 0x01 */
1320 #define MAIN_FW_REVISION                0x08 /* DWORD 0x02 */
1321 #define MAIN_MAX_OUTSTANDING_IO_OFFSET  0x0C /* DWORD 0x03 */
1322 #define MAIN_MAX_SGL_OFFSET             0x10 /* DWORD 0x04 */
1323 #define MAIN_CNTRL_CAP_OFFSET           0x14 /* DWORD 0x05 */
1324 #define MAIN_GST_OFFSET                 0x18 /* DWORD 0x06 */
1325 #define MAIN_IBQ_OFFSET                 0x1C /* DWORD 0x07 */
1326 #define MAIN_OBQ_OFFSET                 0x20 /* DWORD 0x08 */
1327 #define MAIN_IQNPPD_HPPD_OFFSET         0x24 /* DWORD 0x09 */
1328
1329 /* 0x28 - 0x4C - RSVD */
1330 #define MAIN_EVENT_CRC_CHECK            0x48 /* DWORD 0x12 */
1331 #define MAIN_EVENT_LOG_ADDR_HI          0x50 /* DWORD 0x14 */
1332 #define MAIN_EVENT_LOG_ADDR_LO          0x54 /* DWORD 0x15 */
1333 #define MAIN_EVENT_LOG_BUFF_SIZE        0x58 /* DWORD 0x16 */
1334 #define MAIN_EVENT_LOG_OPTION           0x5C /* DWORD 0x17 */
1335 #define MAIN_PCS_EVENT_LOG_ADDR_HI      0x60 /* DWORD 0x18 */
1336 #define MAIN_PCS_EVENT_LOG_ADDR_LO      0x64 /* DWORD 0x19 */
1337 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE    0x68 /* DWORD 0x1A */
1338 #define MAIN_PCS_EVENT_LOG_OPTION       0x6C /* DWORD 0x1B */
1339 #define MAIN_FATAL_ERROR_INTERRUPT      0x70 /* DWORD 0x1C */
1340 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET  0x74 /* DWORD 0x1D */
1341 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH  0x78 /* DWORD 0x1E */
1342 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET  0x7C /* DWORD 0x1F */
1343 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH  0x80 /* DWORD 0x20 */
1344 #define MAIN_GPIO_LED_FLAGS_OFFSET      0x84 /* DWORD 0x21 */
1345 #define MAIN_ANALOG_SETUP_OFFSET        0x88 /* DWORD 0x22 */
1346
1347 #define MAIN_INT_VECTOR_TABLE_OFFSET    0x8C /* DWORD 0x23 */
1348 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET  0x90 /* DWORD 0x24 */
1349 #define MAIN_PORT_RECOVERY_TIMER        0x94 /* DWORD 0x25 */
1350 #define MAIN_INT_REASSERTION_DELAY      0x98 /* DWORD 0x26 */
1351
1352 /* Gereral Status Table offset - byte offset */
1353 #define GST_GSTLEN_MPIS_OFFSET          0x00
1354 #define GST_IQ_FREEZE_STATE0_OFFSET     0x04
1355 #define GST_IQ_FREEZE_STATE1_OFFSET     0x08
1356 #define GST_MSGUTCNT_OFFSET             0x0C
1357 #define GST_IOPTCNT_OFFSET              0x10
1358 /* 0x14 - 0x34 - RSVD */
1359 #define GST_GPIO_INPUT_VAL              0x38
1360 /* 0x3c - 0x40 - RSVD */
1361 #define GST_RERRINFO_OFFSET0            0x44
1362 #define GST_RERRINFO_OFFSET1            0x48
1363 #define GST_RERRINFO_OFFSET2            0x4c
1364 #define GST_RERRINFO_OFFSET3            0x50
1365 #define GST_RERRINFO_OFFSET4            0x54
1366 #define GST_RERRINFO_OFFSET5            0x58
1367 #define GST_RERRINFO_OFFSET6            0x5c
1368 #define GST_RERRINFO_OFFSET7            0x60
1369
1370 /* General Status Table - MPI state */
1371 #define GST_MPI_STATE_UNINIT            0x00
1372 #define GST_MPI_STATE_INIT              0x01
1373 #define GST_MPI_STATE_TERMINATION       0x02
1374 #define GST_MPI_STATE_ERROR             0x03
1375 #define GST_MPI_STATE_MASK              0x07
1376
1377 /* Per SAS PHY Attributes */
1378
1379 #define PSPA_PHYSTATE0_OFFSET           0x00 /* Dword V */
1380 #define PSPA_OB_HW_EVENT_PID0_OFFSET    0x04 /* DWORD V+1 */
1381 #define PSPA_PHYSTATE1_OFFSET           0x08 /* Dword V+2 */
1382 #define PSPA_OB_HW_EVENT_PID1_OFFSET    0x0C /* DWORD V+3 */
1383 #define PSPA_PHYSTATE2_OFFSET           0x10 /* Dword V+4 */
1384 #define PSPA_OB_HW_EVENT_PID2_OFFSET    0x14 /* DWORD V+5 */
1385 #define PSPA_PHYSTATE3_OFFSET           0x18 /* Dword V+6 */
1386 #define PSPA_OB_HW_EVENT_PID3_OFFSET    0x1C /* DWORD V+7 */
1387 #define PSPA_PHYSTATE4_OFFSET           0x20 /* Dword V+8 */
1388 #define PSPA_OB_HW_EVENT_PID4_OFFSET    0x24 /* DWORD V+9 */
1389 #define PSPA_PHYSTATE5_OFFSET           0x28 /* Dword V+10 */
1390 #define PSPA_OB_HW_EVENT_PID5_OFFSET    0x2C /* DWORD V+11 */
1391 #define PSPA_PHYSTATE6_OFFSET           0x30 /* Dword V+12 */
1392 #define PSPA_OB_HW_EVENT_PID6_OFFSET    0x34 /* DWORD V+13 */
1393 #define PSPA_PHYSTATE7_OFFSET           0x38 /* Dword V+14 */
1394 #define PSPA_OB_HW_EVENT_PID7_OFFSET    0x3C /* DWORD V+15 */
1395 #define PSPA_PHYSTATE8_OFFSET           0x40 /* DWORD V+16 */
1396 #define PSPA_OB_HW_EVENT_PID8_OFFSET    0x44 /* DWORD V+17 */
1397 #define PSPA_PHYSTATE9_OFFSET           0x48 /* DWORD V+18 */
1398 #define PSPA_OB_HW_EVENT_PID9_OFFSET    0x4C /* DWORD V+19 */
1399 #define PSPA_PHYSTATE10_OFFSET          0x50 /* DWORD V+20 */
1400 #define PSPA_OB_HW_EVENT_PID10_OFFSET   0x54 /* DWORD V+21 */
1401 #define PSPA_PHYSTATE11_OFFSET          0x58 /* DWORD V+22 */
1402 #define PSPA_OB_HW_EVENT_PID11_OFFSET   0x5C /* DWORD V+23 */
1403 #define PSPA_PHYSTATE12_OFFSET          0x60 /* DWORD V+24 */
1404 #define PSPA_OB_HW_EVENT_PID12_OFFSET   0x64 /* DWORD V+25 */
1405 #define PSPA_PHYSTATE13_OFFSET          0x68 /* DWORD V+26 */
1406 #define PSPA_OB_HW_EVENT_PID13_OFFSET   0x6c /* DWORD V+27 */
1407 #define PSPA_PHYSTATE14_OFFSET          0x70 /* DWORD V+28 */
1408 #define PSPA_OB_HW_EVENT_PID14_OFFSET   0x74 /* DWORD V+29 */
1409 #define PSPA_PHYSTATE15_OFFSET          0x78 /* DWORD V+30 */
1410 #define PSPA_OB_HW_EVENT_PID15_OFFSET   0x7c /* DWORD V+31 */
1411 /* end PSPA */
1412
1413 /* inbound queue configuration offset - byte offset */
1414 #define IB_PROPERITY_OFFSET             0x00
1415 #define IB_BASE_ADDR_HI_OFFSET          0x04
1416 #define IB_BASE_ADDR_LO_OFFSET          0x08
1417 #define IB_CI_BASE_ADDR_HI_OFFSET       0x0C
1418 #define IB_CI_BASE_ADDR_LO_OFFSET       0x10
1419 #define IB_PIPCI_BAR                    0x14
1420 #define IB_PIPCI_BAR_OFFSET             0x18
1421 #define IB_RESERVED_OFFSET              0x1C
1422
1423 /* outbound queue configuration offset - byte offset */
1424 #define OB_PROPERITY_OFFSET             0x00
1425 #define OB_BASE_ADDR_HI_OFFSET          0x04
1426 #define OB_BASE_ADDR_LO_OFFSET          0x08
1427 #define OB_PI_BASE_ADDR_HI_OFFSET       0x0C
1428 #define OB_PI_BASE_ADDR_LO_OFFSET       0x10
1429 #define OB_CIPCI_BAR                    0x14
1430 #define OB_CIPCI_BAR_OFFSET             0x18
1431 #define OB_INTERRUPT_COALES_OFFSET      0x1C
1432 #define OB_DYNAMIC_COALES_OFFSET        0x20
1433 #define OB_PROPERTY_INT_ENABLE          0x40000000
1434
1435 #define MBIC_NMI_ENABLE_VPE0_IOP        0x000418
1436 #define MBIC_NMI_ENABLE_VPE0_AAP1       0x000418
1437 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1438 #define PCIE_EVENT_INTERRUPT_ENABLE     0x003040
1439 #define PCIE_EVENT_INTERRUPT            0x003044
1440 #define PCIE_ERROR_INTERRUPT_ENABLE     0x003048
1441 #define PCIE_ERROR_INTERRUPT            0x00304C
1442
1443 /* SPCV soft reset */
1444 #define SPC_REG_SOFT_RESET 0x00001000
1445 #define SPCv_NORMAL_RESET_VALUE         0x1
1446
1447 #define SPCv_SOFT_RESET_READ_MASK               0xC0
1448 #define SPCv_SOFT_RESET_NO_RESET                0x0
1449 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED    0x40
1450 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED        0x80
1451 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED      0xC0
1452
1453 /* signature definition for host scratch pad0 register */
1454 #define SPC_SOFT_RESET_SIGNATURE        0x252acbcd
1455 /* Signature for Soft Reset */
1456
1457 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1458 #define SPC_REG_RESET                   0x000000/* reset register */
1459
1460 /* bit definition for SPC_RESET register */
1461 #define SPC_REG_RESET_OSSP              0x00000001
1462 #define SPC_REG_RESET_RAAE              0x00000002
1463 #define SPC_REG_RESET_PCS_SPBC          0x00000004
1464 #define SPC_REG_RESET_PCS_IOP_SS        0x00000008
1465 #define SPC_REG_RESET_PCS_AAP1_SS       0x00000010
1466 #define SPC_REG_RESET_PCS_AAP2_SS       0x00000020
1467 #define SPC_REG_RESET_PCS_LM            0x00000040
1468 #define SPC_REG_RESET_PCS               0x00000080
1469 #define SPC_REG_RESET_GSM               0x00000100
1470 #define SPC_REG_RESET_DDR2              0x00010000
1471 #define SPC_REG_RESET_BDMA_CORE         0x00020000
1472 #define SPC_REG_RESET_BDMA_SXCBI        0x00040000
1473 #define SPC_REG_RESET_PCIE_AL_SXCBI     0x00080000
1474 #define SPC_REG_RESET_PCIE_PWR          0x00100000
1475 #define SPC_REG_RESET_PCIE_SFT          0x00200000
1476 #define SPC_REG_RESET_PCS_SXCBI         0x00400000
1477 #define SPC_REG_RESET_LMS_SXCBI         0x00800000
1478 #define SPC_REG_RESET_PMIC_SXCBI        0x01000000
1479 #define SPC_REG_RESET_PMIC_CORE         0x02000000
1480 #define SPC_REG_RESET_PCIE_PC_SXCBI     0x04000000
1481 #define SPC_REG_RESET_DEVICE            0x80000000
1482
1483 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1484 #define SPCV_IBW_AXI_TRANSLATION_LOW    0x001010
1485
1486 #define MBIC_AAP1_ADDR_BASE             0x060000
1487 #define MBIC_IOP_ADDR_BASE              0x070000
1488 #define GSM_ADDR_BASE                   0x0700000
1489 /* Dynamic map through Bar4 - 0x00700000 */
1490 #define GSM_CONFIG_RESET                0x00000000
1491 #define RAM_ECC_DB_ERR                  0x00000018
1492 #define GSM_READ_ADDR_PARITY_INDIC      0x00000058
1493 #define GSM_WRITE_ADDR_PARITY_INDIC     0x00000060
1494 #define GSM_WRITE_DATA_PARITY_INDIC     0x00000068
1495 #define GSM_READ_ADDR_PARITY_CHECK      0x00000038
1496 #define GSM_WRITE_ADDR_PARITY_CHECK     0x00000040
1497 #define GSM_WRITE_DATA_PARITY_CHECK     0x00000048
1498
1499 #define RB6_ACCESS_REG                  0x6A0000
1500 #define HDAC_EXEC_CMD                   0x0002
1501 #define HDA_C_PA                        0xcb
1502 #define HDA_SEQ_ID_BITS                 0x00ff0000
1503 #define HDA_GSM_OFFSET_BITS             0x00FFFFFF
1504 #define HDA_GSM_CMD_OFFSET_BITS         0x42C0
1505 #define HDA_GSM_RSP_OFFSET_BITS         0x42E0
1506
1507 #define MBIC_AAP1_ADDR_BASE             0x060000
1508 #define MBIC_IOP_ADDR_BASE              0x070000
1509 #define GSM_ADDR_BASE                   0x0700000
1510 #define SPC_TOP_LEVEL_ADDR_BASE         0x000000
1511 #define GSM_CONFIG_RESET_VALUE          0x00003b00
1512 #define GPIO_ADDR_BASE                  0x00090000
1513 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET   0x0000010c
1514
1515 /* RB6 offset */
1516 #define SPC_RB6_OFFSET                  0x80C0
1517 /* Magic number of soft reset for RB6 */
1518 #define RB6_MAGIC_NUMBER_RST            0x1234
1519
1520 /* Device Register status */
1521 #define DEVREG_SUCCESS                                  0x00
1522 #define DEVREG_FAILURE_OUT_OF_RESOURCE                  0x01
1523 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED        0x02
1524 #define DEVREG_FAILURE_INVALID_PHY_ID                   0x03
1525 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED        0x04
1526 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE             0x05
1527 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE             0x06
1528 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID            0x07
1529
1530
1531 #define MEMBASE_II_SHIFT_REGISTER       0x1010
1532 #endif