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scsi: remove ordered_tags scsi_device field
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 #define MAX_Q_DEPTH 32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
119
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
128
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
133 " Default is 2.\n"
134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
137
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
150
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
157
158 int ql2xfwloadbin;
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
167 int ql2xetsenable;
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
173 int ql2xdbwr = 1;
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
179
180 int ql2xtargetreset = 1;
181 module_param(ql2xtargetreset, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
186 int ql2xgffidenable;
187 module_param(ql2xgffidenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
191
192 int ql2xasynctmfenable;
193 module_param(ql2xasynctmfenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
197
198 int ql2xdontresethba;
199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdontresethba,
201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
204
205 uint64_t ql2xmaxlun = MAX_LUNS;
206 module_param(ql2xmaxlun, ullong, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
211 int ql2xmdcapmask = 0x1F;
212 module_param(ql2xmdcapmask, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
216
217 int ql2xmdenable = 1;
218 module_param(ql2xmdenable, int, S_IRUGO);
219 MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
223
224 /*
225 * SCSI host template entry points
226 */
227 static int qla2xxx_slave_configure(struct scsi_device * device);
228 static int qla2xxx_slave_alloc(struct scsi_device *);
229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230 static void qla2xxx_scan_start(struct Scsi_Host *);
231 static void qla2xxx_slave_destroy(struct scsi_device *);
232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
238
239 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
240 static void qla2x00_clear_drv_active(struct qla_hw_data *);
241 static void qla2x00_free_device(scsi_qla_host_t *);
242 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
243
244 struct scsi_host_template qla2xxx_driver_template = {
245 .module = THIS_MODULE,
246 .name = QLA2XXX_DRIVER_NAME,
247 .queuecommand = qla2xxx_queuecommand,
248
249 .eh_abort_handler = qla2xxx_eh_abort,
250 .eh_device_reset_handler = qla2xxx_eh_device_reset,
251 .eh_target_reset_handler = qla2xxx_eh_target_reset,
252 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
253 .eh_host_reset_handler = qla2xxx_eh_host_reset,
254
255 .slave_configure = qla2xxx_slave_configure,
256
257 .slave_alloc = qla2xxx_slave_alloc,
258 .slave_destroy = qla2xxx_slave_destroy,
259 .scan_finished = qla2xxx_scan_finished,
260 .scan_start = qla2xxx_scan_start,
261 .change_queue_depth = qla2x00_change_queue_depth,
262 .change_queue_type = scsi_change_queue_type,
263 .this_id = -1,
264 .cmd_per_lun = 3,
265 .use_clustering = ENABLE_CLUSTERING,
266 .sg_tablesize = SG_ALL,
267
268 .max_sectors = 0xFFFF,
269 .shost_attrs = qla2x00_host_attrs,
270
271 .supported_mode = MODE_INITIATOR,
272 };
273
274 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
275 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
276
277 /* TODO Convert to inlines
278 *
279 * Timer routines
280 */
281
282 __inline__ void
283 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
284 {
285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
291 }
292
293 static inline void
294 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
295 {
296 /* Currently used for 82XX only. */
297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
300 return;
301 }
302
303 mod_timer(&vha->timer, jiffies + interval * HZ);
304 }
305
306 static __inline__ void
307 qla2x00_stop_timer(scsi_qla_host_t *vha)
308 {
309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
311 }
312
313 static int qla2x00_do_dpc(void *data);
314
315 static void qla2x00_rst_aen(scsi_qla_host_t *);
316
317 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
319 static void qla2x00_free_fw_dump(struct qla_hw_data *);
320 static void qla2x00_mem_free(struct qla_hw_data *);
321
322 /* -------------------------------------------------------------------------- */
323 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
325 {
326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
328 GFP_KERNEL);
329 if (!ha->req_q_map) {
330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
332 goto fail_req_map;
333 }
334
335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
340 goto fail_rsp_map;
341 }
342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352 fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355 fail_req_map:
356 return -ENOMEM;
357 }
358
359 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
360 {
361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
371 if (req)
372 kfree(req->outstanding_cmds);
373
374 kfree(req);
375 req = NULL;
376 }
377
378 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379 {
380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
389 }
390 kfree(rsp);
391 rsp = NULL;
392 }
393
394 static void qla2x00_free_queues(struct qla_hw_data *ha)
395 {
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
401 req = ha->req_q_map[cnt];
402 qla2x00_free_req_que(ha, req);
403 }
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
413 }
414
415 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416 {
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
421 if (!(ha->fw_attributes & BIT_6)) {
422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
424 goto fail;
425 }
426 if (ql2xmultique_tag) {
427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
434 goto fail;
435 }
436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
444 goto fail2;
445 }
446 }
447 ha->flags.cpu_affinity_enabled = 1;
448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
453 "CPU affinity mode enalbed, "
454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
456 }
457 return 0;
458 fail2:
459 qla25xx_delete_queues(vha);
460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
462 vha->req = ha->req_q_map[0];
463 fail:
464 ha->mqenable = 0;
465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
468 return 1;
469 }
470
471 static char *
472 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
473 {
474 struct qla_hw_data *ha = vha->hw;
475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493 }
494
495 static char *
496 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
497 {
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
499 struct qla_hw_data *ha = vha->hw;
500 uint32_t pci_bus;
501
502 if (pci_is_pcie(ha->pdev)) {
503 char lwstr[6];
504 uint32_t lstat, lspeed, lwidth;
505
506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
509
510 strcpy(str, "PCIe (");
511 switch (lspeed) {
512 case 1:
513 strcat(str, "2.5GT/s ");
514 break;
515 case 2:
516 strcat(str, "5.0GT/s ");
517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
522 strcat(str, "<unknown> ");
523 break;
524 }
525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548 }
549
550 static char *
551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
552 {
553 char un_str[10];
554 struct qla_hw_data *ha = vha->hw;
555
556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version);
558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586 }
587
588 static char *
589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
590 {
591 struct qla_hw_data *ha = vha->hw;
592
593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
595 return str;
596 }
597
598 void
599 qla2x00_sp_free_dma(void *vha, void *ptr)
600 {
601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
605
606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
609 }
610
611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
619 qla2x00_clean_dsd_pool(ha, sp, NULL);
620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
631
632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
642 qla2x00_rel_sp(sp->fcport->vha, sp);
643 }
644
645 static void
646 qla2x00_sp_compl(void *data, void *ptr, int res)
647 {
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
667 }
668
669 /* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
672 static int
673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
674 {
675 scsi_qla_host_t *vha = shost_priv(host);
676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
680 srb_t *sp;
681 int rval;
682
683 if (ha->flags.eeh_busy) {
684 if (ha->flags.pci_channel_io_perm_failure) {
685 ql_dbg(ql_dbg_aer, vha, 0x9010,
686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
688 cmd->result = DID_NO_CONNECT << 16;
689 } else {
690 ql_dbg(ql_dbg_aer, vha, 0x9011,
691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
692 cmd->result = DID_REQUEUE << 16;
693 }
694 goto qc24_fail_command;
695 }
696
697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
703 goto qc24_fail_command;
704 }
705
706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
730 goto qc24_target_busy;
731 }
732
733 /*
734 * Return target busy if we've received a non-zero retry_delay_timer
735 * in a FCP_RSP.
736 */
737 if (time_after(jiffies, fcport->retry_delay_timestamp))
738 fcport->retry_delay_timestamp = 0;
739 else
740 goto qc24_target_busy;
741
742 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
743 if (!sp)
744 goto qc24_host_busy;
745
746 sp->u.scmd.cmd = cmd;
747 sp->type = SRB_SCSI_CMD;
748 atomic_set(&sp->ref_count, 1);
749 CMD_SP(cmd) = (void *)sp;
750 sp->free = qla2x00_sp_free_dma;
751 sp->done = qla2x00_sp_compl;
752
753 rval = ha->isp_ops->start_scsi(sp);
754 if (rval != QLA_SUCCESS) {
755 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
756 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
757 goto qc24_host_busy_free_sp;
758 }
759
760 return 0;
761
762 qc24_host_busy_free_sp:
763 qla2x00_sp_free_dma(ha, sp);
764
765 qc24_host_busy:
766 return SCSI_MLQUEUE_HOST_BUSY;
767
768 qc24_target_busy:
769 return SCSI_MLQUEUE_TARGET_BUSY;
770
771 qc24_fail_command:
772 cmd->scsi_done(cmd);
773
774 return 0;
775 }
776
777 /*
778 * qla2x00_eh_wait_on_command
779 * Waits for the command to be returned by the Firmware for some
780 * max time.
781 *
782 * Input:
783 * cmd = Scsi Command to wait on.
784 *
785 * Return:
786 * Not Found : 0
787 * Found : 1
788 */
789 static int
790 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
791 {
792 #define ABORT_POLLING_PERIOD 1000
793 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
794 unsigned long wait_iter = ABORT_WAIT_ITER;
795 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
796 struct qla_hw_data *ha = vha->hw;
797 int ret = QLA_SUCCESS;
798
799 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
800 ql_dbg(ql_dbg_taskm, vha, 0x8005,
801 "Return:eh_wait.\n");
802 return ret;
803 }
804
805 while (CMD_SP(cmd) && wait_iter--) {
806 msleep(ABORT_POLLING_PERIOD);
807 }
808 if (CMD_SP(cmd))
809 ret = QLA_FUNCTION_FAILED;
810
811 return ret;
812 }
813
814 /*
815 * qla2x00_wait_for_hba_online
816 * Wait till the HBA is online after going through
817 * <= MAX_RETRIES_OF_ISP_ABORT or
818 * finally HBA is disabled ie marked offline
819 *
820 * Input:
821 * ha - pointer to host adapter structure
822 *
823 * Note:
824 * Does context switching-Release SPIN_LOCK
825 * (if any) before calling this routine.
826 *
827 * Return:
828 * Success (Adapter is online) : 0
829 * Failed (Adapter is offline/disabled) : 1
830 */
831 int
832 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
833 {
834 int return_status;
835 unsigned long wait_online;
836 struct qla_hw_data *ha = vha->hw;
837 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
838
839 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
840 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
841 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
842 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
843 ha->dpc_active) && time_before(jiffies, wait_online)) {
844
845 msleep(1000);
846 }
847 if (base_vha->flags.online)
848 return_status = QLA_SUCCESS;
849 else
850 return_status = QLA_FUNCTION_FAILED;
851
852 return (return_status);
853 }
854
855 /*
856 * qla2x00_wait_for_hba_ready
857 * Wait till the HBA is ready before doing driver unload
858 *
859 * Input:
860 * ha - pointer to host adapter structure
861 *
862 * Note:
863 * Does context switching-Release SPIN_LOCK
864 * (if any) before calling this routine.
865 *
866 */
867 static void
868 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
869 {
870 struct qla_hw_data *ha = vha->hw;
871
872 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
873 ha->flags.mbox_busy) ||
874 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
875 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
876 msleep(1000);
877 }
878
879 int
880 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
881 {
882 int return_status;
883 unsigned long wait_reset;
884 struct qla_hw_data *ha = vha->hw;
885 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
886
887 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
888 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
889 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
890 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
891 ha->dpc_active) && time_before(jiffies, wait_reset)) {
892
893 msleep(1000);
894
895 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
896 ha->flags.chip_reset_done)
897 break;
898 }
899 if (ha->flags.chip_reset_done)
900 return_status = QLA_SUCCESS;
901 else
902 return_status = QLA_FUNCTION_FAILED;
903
904 return return_status;
905 }
906
907 static void
908 sp_get(struct srb *sp)
909 {
910 atomic_inc(&sp->ref_count);
911 }
912
913 /**************************************************************************
914 * qla2xxx_eh_abort
915 *
916 * Description:
917 * The abort function will abort the specified command.
918 *
919 * Input:
920 * cmd = Linux SCSI command packet to be aborted.
921 *
922 * Returns:
923 * Either SUCCESS or FAILED.
924 *
925 * Note:
926 * Only return FAILED if command not returned by firmware.
927 **************************************************************************/
928 static int
929 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
930 {
931 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
932 srb_t *sp;
933 int ret;
934 unsigned int id;
935 uint64_t lun;
936 unsigned long flags;
937 int rval, wait = 0;
938 struct qla_hw_data *ha = vha->hw;
939
940 if (!CMD_SP(cmd))
941 return SUCCESS;
942
943 ret = fc_block_scsi_eh(cmd);
944 if (ret != 0)
945 return ret;
946 ret = SUCCESS;
947
948 id = cmd->device->id;
949 lun = cmd->device->lun;
950
951 spin_lock_irqsave(&ha->hardware_lock, flags);
952 sp = (srb_t *) CMD_SP(cmd);
953 if (!sp) {
954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
955 return SUCCESS;
956 }
957
958 ql_dbg(ql_dbg_taskm, vha, 0x8002,
959 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
960 vha->host_no, id, lun, sp, cmd);
961
962 /* Get a reference to the sp and drop the lock.*/
963 sp_get(sp);
964
965 spin_unlock_irqrestore(&ha->hardware_lock, flags);
966 rval = ha->isp_ops->abort_command(sp);
967 if (rval) {
968 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
969 /*
970 * Decrement the ref_count since we can't find the
971 * command
972 */
973 atomic_dec(&sp->ref_count);
974 ret = SUCCESS;
975 } else
976 ret = FAILED;
977
978 ql_dbg(ql_dbg_taskm, vha, 0x8003,
979 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
980 } else {
981 ql_dbg(ql_dbg_taskm, vha, 0x8004,
982 "Abort command mbx success cmd=%p.\n", cmd);
983 wait = 1;
984 }
985
986 spin_lock_irqsave(&ha->hardware_lock, flags);
987 /*
988 * Clear the slot in the oustanding_cmds array if we can't find the
989 * command to reclaim the resources.
990 */
991 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
992 vha->req->outstanding_cmds[sp->handle] = NULL;
993 sp->done(ha, sp, 0);
994 spin_unlock_irqrestore(&ha->hardware_lock, flags);
995
996 /* Did the command return during mailbox execution? */
997 if (ret == FAILED && !CMD_SP(cmd))
998 ret = SUCCESS;
999
1000 /* Wait for the command to be returned. */
1001 if (wait) {
1002 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1003 ql_log(ql_log_warn, vha, 0x8006,
1004 "Abort handler timed out cmd=%p.\n", cmd);
1005 ret = FAILED;
1006 }
1007 }
1008
1009 ql_log(ql_log_info, vha, 0x801c,
1010 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1011 vha->host_no, id, lun, wait, ret);
1012
1013 return ret;
1014 }
1015
1016 int
1017 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1018 uint64_t l, enum nexus_wait_type type)
1019 {
1020 int cnt, match, status;
1021 unsigned long flags;
1022 struct qla_hw_data *ha = vha->hw;
1023 struct req_que *req;
1024 srb_t *sp;
1025 struct scsi_cmnd *cmd;
1026
1027 status = QLA_SUCCESS;
1028
1029 spin_lock_irqsave(&ha->hardware_lock, flags);
1030 req = vha->req;
1031 for (cnt = 1; status == QLA_SUCCESS &&
1032 cnt < req->num_outstanding_cmds; cnt++) {
1033 sp = req->outstanding_cmds[cnt];
1034 if (!sp)
1035 continue;
1036 if (sp->type != SRB_SCSI_CMD)
1037 continue;
1038 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1039 continue;
1040 match = 0;
1041 cmd = GET_CMD_SP(sp);
1042 switch (type) {
1043 case WAIT_HOST:
1044 match = 1;
1045 break;
1046 case WAIT_TARGET:
1047 match = cmd->device->id == t;
1048 break;
1049 case WAIT_LUN:
1050 match = (cmd->device->id == t &&
1051 cmd->device->lun == l);
1052 break;
1053 }
1054 if (!match)
1055 continue;
1056
1057 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1058 status = qla2x00_eh_wait_on_command(cmd);
1059 spin_lock_irqsave(&ha->hardware_lock, flags);
1060 }
1061 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1062
1063 return status;
1064 }
1065
1066 static char *reset_errors[] = {
1067 "HBA not online",
1068 "HBA not ready",
1069 "Task management failed",
1070 "Waiting for command completions",
1071 };
1072
1073 static int
1074 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1075 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1076 {
1077 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1078 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1079 int err;
1080
1081 if (!fcport) {
1082 return FAILED;
1083 }
1084
1085 err = fc_block_scsi_eh(cmd);
1086 if (err != 0)
1087 return err;
1088
1089 ql_log(ql_log_info, vha, 0x8009,
1090 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1091 cmd->device->id, cmd->device->lun, cmd);
1092
1093 err = 0;
1094 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x800a,
1096 "Wait for hba online failed for cmd=%p.\n", cmd);
1097 goto eh_reset_failed;
1098 }
1099 err = 2;
1100 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1101 != QLA_SUCCESS) {
1102 ql_log(ql_log_warn, vha, 0x800c,
1103 "do_reset failed for cmd=%p.\n", cmd);
1104 goto eh_reset_failed;
1105 }
1106 err = 3;
1107 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1108 cmd->device->lun, type) != QLA_SUCCESS) {
1109 ql_log(ql_log_warn, vha, 0x800d,
1110 "wait for pending cmds failed for cmd=%p.\n", cmd);
1111 goto eh_reset_failed;
1112 }
1113
1114 ql_log(ql_log_info, vha, 0x800e,
1115 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1116 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1117
1118 return SUCCESS;
1119
1120 eh_reset_failed:
1121 ql_log(ql_log_info, vha, 0x800f,
1122 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1123 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1124 cmd);
1125 return FAILED;
1126 }
1127
1128 static int
1129 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1130 {
1131 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1132 struct qla_hw_data *ha = vha->hw;
1133
1134 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1135 ha->isp_ops->lun_reset);
1136 }
1137
1138 static int
1139 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1140 {
1141 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1142 struct qla_hw_data *ha = vha->hw;
1143
1144 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1145 ha->isp_ops->target_reset);
1146 }
1147
1148 /**************************************************************************
1149 * qla2xxx_eh_bus_reset
1150 *
1151 * Description:
1152 * The bus reset function will reset the bus and abort any executing
1153 * commands.
1154 *
1155 * Input:
1156 * cmd = Linux SCSI command packet of the command that cause the
1157 * bus reset.
1158 *
1159 * Returns:
1160 * SUCCESS/FAILURE (defined as macro in scsi.h).
1161 *
1162 **************************************************************************/
1163 static int
1164 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1165 {
1166 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1167 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1168 int ret = FAILED;
1169 unsigned int id;
1170 uint64_t lun;
1171
1172 id = cmd->device->id;
1173 lun = cmd->device->lun;
1174
1175 if (!fcport) {
1176 return ret;
1177 }
1178
1179 ret = fc_block_scsi_eh(cmd);
1180 if (ret != 0)
1181 return ret;
1182 ret = FAILED;
1183
1184 ql_log(ql_log_info, vha, 0x8012,
1185 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1186
1187 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1188 ql_log(ql_log_fatal, vha, 0x8013,
1189 "Wait for hba online failed board disabled.\n");
1190 goto eh_bus_reset_done;
1191 }
1192
1193 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1194 ret = SUCCESS;
1195
1196 if (ret == FAILED)
1197 goto eh_bus_reset_done;
1198
1199 /* Flush outstanding commands. */
1200 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1201 QLA_SUCCESS) {
1202 ql_log(ql_log_warn, vha, 0x8014,
1203 "Wait for pending commands failed.\n");
1204 ret = FAILED;
1205 }
1206
1207 eh_bus_reset_done:
1208 ql_log(ql_log_warn, vha, 0x802b,
1209 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1210 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1211
1212 return ret;
1213 }
1214
1215 /**************************************************************************
1216 * qla2xxx_eh_host_reset
1217 *
1218 * Description:
1219 * The reset function will reset the Adapter.
1220 *
1221 * Input:
1222 * cmd = Linux SCSI command packet of the command that cause the
1223 * adapter reset.
1224 *
1225 * Returns:
1226 * Either SUCCESS or FAILED.
1227 *
1228 * Note:
1229 **************************************************************************/
1230 static int
1231 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1232 {
1233 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1234 struct qla_hw_data *ha = vha->hw;
1235 int ret = FAILED;
1236 unsigned int id;
1237 uint64_t lun;
1238 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1239
1240 id = cmd->device->id;
1241 lun = cmd->device->lun;
1242
1243 ql_log(ql_log_info, vha, 0x8018,
1244 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1245
1246 /*
1247 * No point in issuing another reset if one is active. Also do not
1248 * attempt a reset if we are updating flash.
1249 */
1250 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1251 goto eh_host_reset_lock;
1252
1253 if (vha != base_vha) {
1254 if (qla2x00_vp_abort_isp(vha))
1255 goto eh_host_reset_lock;
1256 } else {
1257 if (IS_P3P_TYPE(vha->hw)) {
1258 if (!qla82xx_fcoe_ctx_reset(vha)) {
1259 /* Ctx reset success */
1260 ret = SUCCESS;
1261 goto eh_host_reset_lock;
1262 }
1263 /* fall thru if ctx reset failed */
1264 }
1265 if (ha->wq)
1266 flush_workqueue(ha->wq);
1267
1268 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1269 if (ha->isp_ops->abort_isp(base_vha)) {
1270 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1271 /* failed. schedule dpc to try */
1272 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1273
1274 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1275 ql_log(ql_log_warn, vha, 0x802a,
1276 "wait for hba online failed.\n");
1277 goto eh_host_reset_lock;
1278 }
1279 }
1280 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1281 }
1282
1283 /* Waiting for command to be returned to OS.*/
1284 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1285 QLA_SUCCESS)
1286 ret = SUCCESS;
1287
1288 eh_host_reset_lock:
1289 ql_log(ql_log_info, vha, 0x8017,
1290 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1291 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1292
1293 return ret;
1294 }
1295
1296 /*
1297 * qla2x00_loop_reset
1298 * Issue loop reset.
1299 *
1300 * Input:
1301 * ha = adapter block pointer.
1302 *
1303 * Returns:
1304 * 0 = success
1305 */
1306 int
1307 qla2x00_loop_reset(scsi_qla_host_t *vha)
1308 {
1309 int ret;
1310 struct fc_port *fcport;
1311 struct qla_hw_data *ha = vha->hw;
1312
1313 if (IS_QLAFX00(ha)) {
1314 return qlafx00_loop_reset(vha);
1315 }
1316
1317 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1318 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1319 if (fcport->port_type != FCT_TARGET)
1320 continue;
1321
1322 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1323 if (ret != QLA_SUCCESS) {
1324 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1325 "Bus Reset failed: Reset=%d "
1326 "d_id=%x.\n", ret, fcport->d_id.b24);
1327 }
1328 }
1329 }
1330
1331
1332 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1333 atomic_set(&vha->loop_state, LOOP_DOWN);
1334 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1335 qla2x00_mark_all_devices_lost(vha, 0);
1336 ret = qla2x00_full_login_lip(vha);
1337 if (ret != QLA_SUCCESS) {
1338 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1339 "full_login_lip=%d.\n", ret);
1340 }
1341 }
1342
1343 if (ha->flags.enable_lip_reset) {
1344 ret = qla2x00_lip_reset(vha);
1345 if (ret != QLA_SUCCESS)
1346 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1347 "lip_reset failed (%d).\n", ret);
1348 }
1349
1350 /* Issue marker command only when we are going to start the I/O */
1351 vha->marker_needed = 1;
1352
1353 return QLA_SUCCESS;
1354 }
1355
1356 void
1357 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1358 {
1359 int que, cnt;
1360 unsigned long flags;
1361 srb_t *sp;
1362 struct qla_hw_data *ha = vha->hw;
1363 struct req_que *req;
1364
1365 qlt_host_reset_handler(ha);
1366
1367 spin_lock_irqsave(&ha->hardware_lock, flags);
1368 for (que = 0; que < ha->max_req_queues; que++) {
1369 req = ha->req_q_map[que];
1370 if (!req)
1371 continue;
1372 if (!req->outstanding_cmds)
1373 continue;
1374 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1375 sp = req->outstanding_cmds[cnt];
1376 if (sp) {
1377 req->outstanding_cmds[cnt] = NULL;
1378 sp->done(vha, sp, res);
1379 }
1380 }
1381 }
1382 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1383 }
1384
1385 static int
1386 qla2xxx_slave_alloc(struct scsi_device *sdev)
1387 {
1388 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1389
1390 if (!rport || fc_remote_port_chkready(rport))
1391 return -ENXIO;
1392
1393 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1394
1395 return 0;
1396 }
1397
1398 static int
1399 qla2xxx_slave_configure(struct scsi_device *sdev)
1400 {
1401 scsi_qla_host_t *vha = shost_priv(sdev->host);
1402 struct req_que *req = vha->req;
1403
1404 if (IS_T10_PI_CAPABLE(vha->hw))
1405 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1406
1407 if (sdev->tagged_supported)
1408 scsi_activate_tcq(sdev, req->max_q_depth);
1409 else
1410 scsi_deactivate_tcq(sdev, req->max_q_depth);
1411 return 0;
1412 }
1413
1414 static void
1415 qla2xxx_slave_destroy(struct scsi_device *sdev)
1416 {
1417 sdev->hostdata = NULL;
1418 }
1419
1420 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1421 {
1422 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1423
1424 if (!scsi_track_queue_full(sdev, qdepth))
1425 return;
1426
1427 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1428 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
1429 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1430 }
1431
1432 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1433 {
1434 fc_port_t *fcport = sdev->hostdata;
1435 struct scsi_qla_host *vha = fcport->vha;
1436 struct req_que *req = NULL;
1437
1438 req = vha->req;
1439 if (!req)
1440 return;
1441
1442 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1443 return;
1444
1445 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1446
1447 ql_dbg(ql_dbg_io, vha, 0x302a,
1448 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
1449 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1450 }
1451
1452 static int
1453 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1454 {
1455 switch (reason) {
1456 case SCSI_QDEPTH_DEFAULT:
1457 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1458 break;
1459 case SCSI_QDEPTH_QFULL:
1460 qla2x00_handle_queue_full(sdev, qdepth);
1461 break;
1462 case SCSI_QDEPTH_RAMP_UP:
1463 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1464 break;
1465 default:
1466 return -EOPNOTSUPP;
1467 }
1468
1469 return sdev->queue_depth;
1470 }
1471
1472 /**
1473 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1474 * @ha: HA context
1475 *
1476 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1477 * supported addressing method.
1478 */
1479 static void
1480 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1481 {
1482 /* Assume a 32bit DMA mask. */
1483 ha->flags.enable_64bit_addressing = 0;
1484
1485 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1486 /* Any upper-dword bits set? */
1487 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1488 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1489 /* Ok, a 64bit DMA mask is applicable. */
1490 ha->flags.enable_64bit_addressing = 1;
1491 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1492 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1493 return;
1494 }
1495 }
1496
1497 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1498 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1499 }
1500
1501 static void
1502 qla2x00_enable_intrs(struct qla_hw_data *ha)
1503 {
1504 unsigned long flags = 0;
1505 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1506
1507 spin_lock_irqsave(&ha->hardware_lock, flags);
1508 ha->interrupts_on = 1;
1509 /* enable risc and host interrupts */
1510 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1511 RD_REG_WORD(&reg->ictrl);
1512 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1513
1514 }
1515
1516 static void
1517 qla2x00_disable_intrs(struct qla_hw_data *ha)
1518 {
1519 unsigned long flags = 0;
1520 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1521
1522 spin_lock_irqsave(&ha->hardware_lock, flags);
1523 ha->interrupts_on = 0;
1524 /* disable risc and host interrupts */
1525 WRT_REG_WORD(&reg->ictrl, 0);
1526 RD_REG_WORD(&reg->ictrl);
1527 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1528 }
1529
1530 static void
1531 qla24xx_enable_intrs(struct qla_hw_data *ha)
1532 {
1533 unsigned long flags = 0;
1534 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1535
1536 spin_lock_irqsave(&ha->hardware_lock, flags);
1537 ha->interrupts_on = 1;
1538 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1539 RD_REG_DWORD(&reg->ictrl);
1540 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1541 }
1542
1543 static void
1544 qla24xx_disable_intrs(struct qla_hw_data *ha)
1545 {
1546 unsigned long flags = 0;
1547 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1548
1549 if (IS_NOPOLLING_TYPE(ha))
1550 return;
1551 spin_lock_irqsave(&ha->hardware_lock, flags);
1552 ha->interrupts_on = 0;
1553 WRT_REG_DWORD(&reg->ictrl, 0);
1554 RD_REG_DWORD(&reg->ictrl);
1555 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1556 }
1557
1558 static int
1559 qla2x00_iospace_config(struct qla_hw_data *ha)
1560 {
1561 resource_size_t pio;
1562 uint16_t msix;
1563 int cpus;
1564
1565 if (pci_request_selected_regions(ha->pdev, ha->bars,
1566 QLA2XXX_DRIVER_NAME)) {
1567 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1568 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1569 pci_name(ha->pdev));
1570 goto iospace_error_exit;
1571 }
1572 if (!(ha->bars & 1))
1573 goto skip_pio;
1574
1575 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1576 pio = pci_resource_start(ha->pdev, 0);
1577 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1578 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1579 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1580 "Invalid pci I/O region size (%s).\n",
1581 pci_name(ha->pdev));
1582 pio = 0;
1583 }
1584 } else {
1585 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1586 "Region #0 no a PIO resource (%s).\n",
1587 pci_name(ha->pdev));
1588 pio = 0;
1589 }
1590 ha->pio_address = pio;
1591 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1592 "PIO address=%llu.\n",
1593 (unsigned long long)ha->pio_address);
1594
1595 skip_pio:
1596 /* Use MMIO operations for all accesses. */
1597 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1598 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1599 "Region #1 not an MMIO resource (%s), aborting.\n",
1600 pci_name(ha->pdev));
1601 goto iospace_error_exit;
1602 }
1603 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1604 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1605 "Invalid PCI mem region size (%s), aborting.\n",
1606 pci_name(ha->pdev));
1607 goto iospace_error_exit;
1608 }
1609
1610 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1611 if (!ha->iobase) {
1612 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1613 "Cannot remap MMIO (%s), aborting.\n",
1614 pci_name(ha->pdev));
1615 goto iospace_error_exit;
1616 }
1617
1618 /* Determine queue resources */
1619 ha->max_req_queues = ha->max_rsp_queues = 1;
1620 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1621 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1622 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1623 goto mqiobase_exit;
1624
1625 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1626 pci_resource_len(ha->pdev, 3));
1627 if (ha->mqiobase) {
1628 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1629 "MQIO Base=%p.\n", ha->mqiobase);
1630 /* Read MSIX vector size of the board */
1631 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1632 ha->msix_count = msix;
1633 /* Max queues are bounded by available msix vectors */
1634 /* queue 0 uses two msix vectors */
1635 if (ql2xmultique_tag) {
1636 cpus = num_online_cpus();
1637 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1638 (cpus + 1) : (ha->msix_count - 1);
1639 ha->max_req_queues = 2;
1640 } else if (ql2xmaxqueues > 1) {
1641 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1642 QLA_MQ_SIZE : ql2xmaxqueues;
1643 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1644 "QoS mode set, max no of request queues:%d.\n",
1645 ha->max_req_queues);
1646 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1647 "QoS mode set, max no of request queues:%d.\n",
1648 ha->max_req_queues);
1649 }
1650 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1651 "MSI-X vector count: %d.\n", msix);
1652 } else
1653 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1654 "BAR 3 not enabled.\n");
1655
1656 mqiobase_exit:
1657 ha->msix_count = ha->max_rsp_queues + 1;
1658 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1659 "MSIX Count:%d.\n", ha->msix_count);
1660 return (0);
1661
1662 iospace_error_exit:
1663 return (-ENOMEM);
1664 }
1665
1666
1667 static int
1668 qla83xx_iospace_config(struct qla_hw_data *ha)
1669 {
1670 uint16_t msix;
1671 int cpus;
1672
1673 if (pci_request_selected_regions(ha->pdev, ha->bars,
1674 QLA2XXX_DRIVER_NAME)) {
1675 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1676 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1677 pci_name(ha->pdev));
1678
1679 goto iospace_error_exit;
1680 }
1681
1682 /* Use MMIO operations for all accesses. */
1683 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1684 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1685 "Invalid pci I/O region size (%s).\n",
1686 pci_name(ha->pdev));
1687 goto iospace_error_exit;
1688 }
1689 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1690 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1691 "Invalid PCI mem region size (%s), aborting\n",
1692 pci_name(ha->pdev));
1693 goto iospace_error_exit;
1694 }
1695
1696 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1697 if (!ha->iobase) {
1698 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1699 "Cannot remap MMIO (%s), aborting.\n",
1700 pci_name(ha->pdev));
1701 goto iospace_error_exit;
1702 }
1703
1704 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1705 /* 83XX 26XX always use MQ type access for queues
1706 * - mbar 2, a.k.a region 4 */
1707 ha->max_req_queues = ha->max_rsp_queues = 1;
1708 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1709 pci_resource_len(ha->pdev, 4));
1710
1711 if (!ha->mqiobase) {
1712 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1713 "BAR2/region4 not enabled\n");
1714 goto mqiobase_exit;
1715 }
1716
1717 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1718 pci_resource_len(ha->pdev, 2));
1719 if (ha->msixbase) {
1720 /* Read MSIX vector size of the board */
1721 pci_read_config_word(ha->pdev,
1722 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1723 ha->msix_count = msix;
1724 /* Max queues are bounded by available msix vectors */
1725 /* queue 0 uses two msix vectors */
1726 if (ql2xmultique_tag) {
1727 cpus = num_online_cpus();
1728 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1729 (cpus + 1) : (ha->msix_count - 1);
1730 ha->max_req_queues = 2;
1731 } else if (ql2xmaxqueues > 1) {
1732 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1733 QLA_MQ_SIZE : ql2xmaxqueues;
1734 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1735 "QoS mode set, max no of request queues:%d.\n",
1736 ha->max_req_queues);
1737 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1738 "QoS mode set, max no of request queues:%d.\n",
1739 ha->max_req_queues);
1740 }
1741 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1742 "MSI-X vector count: %d.\n", msix);
1743 } else
1744 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1745 "BAR 1 not enabled.\n");
1746
1747 mqiobase_exit:
1748 ha->msix_count = ha->max_rsp_queues + 1;
1749
1750 qlt_83xx_iospace_config(ha);
1751
1752 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1753 "MSIX Count:%d.\n", ha->msix_count);
1754 return 0;
1755
1756 iospace_error_exit:
1757 return -ENOMEM;
1758 }
1759
1760 static struct isp_operations qla2100_isp_ops = {
1761 .pci_config = qla2100_pci_config,
1762 .reset_chip = qla2x00_reset_chip,
1763 .chip_diag = qla2x00_chip_diag,
1764 .config_rings = qla2x00_config_rings,
1765 .reset_adapter = qla2x00_reset_adapter,
1766 .nvram_config = qla2x00_nvram_config,
1767 .update_fw_options = qla2x00_update_fw_options,
1768 .load_risc = qla2x00_load_risc,
1769 .pci_info_str = qla2x00_pci_info_str,
1770 .fw_version_str = qla2x00_fw_version_str,
1771 .intr_handler = qla2100_intr_handler,
1772 .enable_intrs = qla2x00_enable_intrs,
1773 .disable_intrs = qla2x00_disable_intrs,
1774 .abort_command = qla2x00_abort_command,
1775 .target_reset = qla2x00_abort_target,
1776 .lun_reset = qla2x00_lun_reset,
1777 .fabric_login = qla2x00_login_fabric,
1778 .fabric_logout = qla2x00_fabric_logout,
1779 .calc_req_entries = qla2x00_calc_iocbs_32,
1780 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1781 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1782 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1783 .read_nvram = qla2x00_read_nvram_data,
1784 .write_nvram = qla2x00_write_nvram_data,
1785 .fw_dump = qla2100_fw_dump,
1786 .beacon_on = NULL,
1787 .beacon_off = NULL,
1788 .beacon_blink = NULL,
1789 .read_optrom = qla2x00_read_optrom_data,
1790 .write_optrom = qla2x00_write_optrom_data,
1791 .get_flash_version = qla2x00_get_flash_version,
1792 .start_scsi = qla2x00_start_scsi,
1793 .abort_isp = qla2x00_abort_isp,
1794 .iospace_config = qla2x00_iospace_config,
1795 .initialize_adapter = qla2x00_initialize_adapter,
1796 };
1797
1798 static struct isp_operations qla2300_isp_ops = {
1799 .pci_config = qla2300_pci_config,
1800 .reset_chip = qla2x00_reset_chip,
1801 .chip_diag = qla2x00_chip_diag,
1802 .config_rings = qla2x00_config_rings,
1803 .reset_adapter = qla2x00_reset_adapter,
1804 .nvram_config = qla2x00_nvram_config,
1805 .update_fw_options = qla2x00_update_fw_options,
1806 .load_risc = qla2x00_load_risc,
1807 .pci_info_str = qla2x00_pci_info_str,
1808 .fw_version_str = qla2x00_fw_version_str,
1809 .intr_handler = qla2300_intr_handler,
1810 .enable_intrs = qla2x00_enable_intrs,
1811 .disable_intrs = qla2x00_disable_intrs,
1812 .abort_command = qla2x00_abort_command,
1813 .target_reset = qla2x00_abort_target,
1814 .lun_reset = qla2x00_lun_reset,
1815 .fabric_login = qla2x00_login_fabric,
1816 .fabric_logout = qla2x00_fabric_logout,
1817 .calc_req_entries = qla2x00_calc_iocbs_32,
1818 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1819 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1820 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1821 .read_nvram = qla2x00_read_nvram_data,
1822 .write_nvram = qla2x00_write_nvram_data,
1823 .fw_dump = qla2300_fw_dump,
1824 .beacon_on = qla2x00_beacon_on,
1825 .beacon_off = qla2x00_beacon_off,
1826 .beacon_blink = qla2x00_beacon_blink,
1827 .read_optrom = qla2x00_read_optrom_data,
1828 .write_optrom = qla2x00_write_optrom_data,
1829 .get_flash_version = qla2x00_get_flash_version,
1830 .start_scsi = qla2x00_start_scsi,
1831 .abort_isp = qla2x00_abort_isp,
1832 .iospace_config = qla2x00_iospace_config,
1833 .initialize_adapter = qla2x00_initialize_adapter,
1834 };
1835
1836 static struct isp_operations qla24xx_isp_ops = {
1837 .pci_config = qla24xx_pci_config,
1838 .reset_chip = qla24xx_reset_chip,
1839 .chip_diag = qla24xx_chip_diag,
1840 .config_rings = qla24xx_config_rings,
1841 .reset_adapter = qla24xx_reset_adapter,
1842 .nvram_config = qla24xx_nvram_config,
1843 .update_fw_options = qla24xx_update_fw_options,
1844 .load_risc = qla24xx_load_risc,
1845 .pci_info_str = qla24xx_pci_info_str,
1846 .fw_version_str = qla24xx_fw_version_str,
1847 .intr_handler = qla24xx_intr_handler,
1848 .enable_intrs = qla24xx_enable_intrs,
1849 .disable_intrs = qla24xx_disable_intrs,
1850 .abort_command = qla24xx_abort_command,
1851 .target_reset = qla24xx_abort_target,
1852 .lun_reset = qla24xx_lun_reset,
1853 .fabric_login = qla24xx_login_fabric,
1854 .fabric_logout = qla24xx_fabric_logout,
1855 .calc_req_entries = NULL,
1856 .build_iocbs = NULL,
1857 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1858 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1859 .read_nvram = qla24xx_read_nvram_data,
1860 .write_nvram = qla24xx_write_nvram_data,
1861 .fw_dump = qla24xx_fw_dump,
1862 .beacon_on = qla24xx_beacon_on,
1863 .beacon_off = qla24xx_beacon_off,
1864 .beacon_blink = qla24xx_beacon_blink,
1865 .read_optrom = qla24xx_read_optrom_data,
1866 .write_optrom = qla24xx_write_optrom_data,
1867 .get_flash_version = qla24xx_get_flash_version,
1868 .start_scsi = qla24xx_start_scsi,
1869 .abort_isp = qla2x00_abort_isp,
1870 .iospace_config = qla2x00_iospace_config,
1871 .initialize_adapter = qla2x00_initialize_adapter,
1872 };
1873
1874 static struct isp_operations qla25xx_isp_ops = {
1875 .pci_config = qla25xx_pci_config,
1876 .reset_chip = qla24xx_reset_chip,
1877 .chip_diag = qla24xx_chip_diag,
1878 .config_rings = qla24xx_config_rings,
1879 .reset_adapter = qla24xx_reset_adapter,
1880 .nvram_config = qla24xx_nvram_config,
1881 .update_fw_options = qla24xx_update_fw_options,
1882 .load_risc = qla24xx_load_risc,
1883 .pci_info_str = qla24xx_pci_info_str,
1884 .fw_version_str = qla24xx_fw_version_str,
1885 .intr_handler = qla24xx_intr_handler,
1886 .enable_intrs = qla24xx_enable_intrs,
1887 .disable_intrs = qla24xx_disable_intrs,
1888 .abort_command = qla24xx_abort_command,
1889 .target_reset = qla24xx_abort_target,
1890 .lun_reset = qla24xx_lun_reset,
1891 .fabric_login = qla24xx_login_fabric,
1892 .fabric_logout = qla24xx_fabric_logout,
1893 .calc_req_entries = NULL,
1894 .build_iocbs = NULL,
1895 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1896 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1897 .read_nvram = qla25xx_read_nvram_data,
1898 .write_nvram = qla25xx_write_nvram_data,
1899 .fw_dump = qla25xx_fw_dump,
1900 .beacon_on = qla24xx_beacon_on,
1901 .beacon_off = qla24xx_beacon_off,
1902 .beacon_blink = qla24xx_beacon_blink,
1903 .read_optrom = qla25xx_read_optrom_data,
1904 .write_optrom = qla24xx_write_optrom_data,
1905 .get_flash_version = qla24xx_get_flash_version,
1906 .start_scsi = qla24xx_dif_start_scsi,
1907 .abort_isp = qla2x00_abort_isp,
1908 .iospace_config = qla2x00_iospace_config,
1909 .initialize_adapter = qla2x00_initialize_adapter,
1910 };
1911
1912 static struct isp_operations qla81xx_isp_ops = {
1913 .pci_config = qla25xx_pci_config,
1914 .reset_chip = qla24xx_reset_chip,
1915 .chip_diag = qla24xx_chip_diag,
1916 .config_rings = qla24xx_config_rings,
1917 .reset_adapter = qla24xx_reset_adapter,
1918 .nvram_config = qla81xx_nvram_config,
1919 .update_fw_options = qla81xx_update_fw_options,
1920 .load_risc = qla81xx_load_risc,
1921 .pci_info_str = qla24xx_pci_info_str,
1922 .fw_version_str = qla24xx_fw_version_str,
1923 .intr_handler = qla24xx_intr_handler,
1924 .enable_intrs = qla24xx_enable_intrs,
1925 .disable_intrs = qla24xx_disable_intrs,
1926 .abort_command = qla24xx_abort_command,
1927 .target_reset = qla24xx_abort_target,
1928 .lun_reset = qla24xx_lun_reset,
1929 .fabric_login = qla24xx_login_fabric,
1930 .fabric_logout = qla24xx_fabric_logout,
1931 .calc_req_entries = NULL,
1932 .build_iocbs = NULL,
1933 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1934 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1935 .read_nvram = NULL,
1936 .write_nvram = NULL,
1937 .fw_dump = qla81xx_fw_dump,
1938 .beacon_on = qla24xx_beacon_on,
1939 .beacon_off = qla24xx_beacon_off,
1940 .beacon_blink = qla83xx_beacon_blink,
1941 .read_optrom = qla25xx_read_optrom_data,
1942 .write_optrom = qla24xx_write_optrom_data,
1943 .get_flash_version = qla24xx_get_flash_version,
1944 .start_scsi = qla24xx_dif_start_scsi,
1945 .abort_isp = qla2x00_abort_isp,
1946 .iospace_config = qla2x00_iospace_config,
1947 .initialize_adapter = qla2x00_initialize_adapter,
1948 };
1949
1950 static struct isp_operations qla82xx_isp_ops = {
1951 .pci_config = qla82xx_pci_config,
1952 .reset_chip = qla82xx_reset_chip,
1953 .chip_diag = qla24xx_chip_diag,
1954 .config_rings = qla82xx_config_rings,
1955 .reset_adapter = qla24xx_reset_adapter,
1956 .nvram_config = qla81xx_nvram_config,
1957 .update_fw_options = qla24xx_update_fw_options,
1958 .load_risc = qla82xx_load_risc,
1959 .pci_info_str = qla24xx_pci_info_str,
1960 .fw_version_str = qla24xx_fw_version_str,
1961 .intr_handler = qla82xx_intr_handler,
1962 .enable_intrs = qla82xx_enable_intrs,
1963 .disable_intrs = qla82xx_disable_intrs,
1964 .abort_command = qla24xx_abort_command,
1965 .target_reset = qla24xx_abort_target,
1966 .lun_reset = qla24xx_lun_reset,
1967 .fabric_login = qla24xx_login_fabric,
1968 .fabric_logout = qla24xx_fabric_logout,
1969 .calc_req_entries = NULL,
1970 .build_iocbs = NULL,
1971 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1972 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1973 .read_nvram = qla24xx_read_nvram_data,
1974 .write_nvram = qla24xx_write_nvram_data,
1975 .fw_dump = qla82xx_fw_dump,
1976 .beacon_on = qla82xx_beacon_on,
1977 .beacon_off = qla82xx_beacon_off,
1978 .beacon_blink = NULL,
1979 .read_optrom = qla82xx_read_optrom_data,
1980 .write_optrom = qla82xx_write_optrom_data,
1981 .get_flash_version = qla82xx_get_flash_version,
1982 .start_scsi = qla82xx_start_scsi,
1983 .abort_isp = qla82xx_abort_isp,
1984 .iospace_config = qla82xx_iospace_config,
1985 .initialize_adapter = qla2x00_initialize_adapter,
1986 };
1987
1988 static struct isp_operations qla8044_isp_ops = {
1989 .pci_config = qla82xx_pci_config,
1990 .reset_chip = qla82xx_reset_chip,
1991 .chip_diag = qla24xx_chip_diag,
1992 .config_rings = qla82xx_config_rings,
1993 .reset_adapter = qla24xx_reset_adapter,
1994 .nvram_config = qla81xx_nvram_config,
1995 .update_fw_options = qla24xx_update_fw_options,
1996 .load_risc = qla82xx_load_risc,
1997 .pci_info_str = qla24xx_pci_info_str,
1998 .fw_version_str = qla24xx_fw_version_str,
1999 .intr_handler = qla8044_intr_handler,
2000 .enable_intrs = qla82xx_enable_intrs,
2001 .disable_intrs = qla82xx_disable_intrs,
2002 .abort_command = qla24xx_abort_command,
2003 .target_reset = qla24xx_abort_target,
2004 .lun_reset = qla24xx_lun_reset,
2005 .fabric_login = qla24xx_login_fabric,
2006 .fabric_logout = qla24xx_fabric_logout,
2007 .calc_req_entries = NULL,
2008 .build_iocbs = NULL,
2009 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2010 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2011 .read_nvram = NULL,
2012 .write_nvram = NULL,
2013 .fw_dump = qla8044_fw_dump,
2014 .beacon_on = qla82xx_beacon_on,
2015 .beacon_off = qla82xx_beacon_off,
2016 .beacon_blink = NULL,
2017 .read_optrom = qla8044_read_optrom_data,
2018 .write_optrom = qla8044_write_optrom_data,
2019 .get_flash_version = qla82xx_get_flash_version,
2020 .start_scsi = qla82xx_start_scsi,
2021 .abort_isp = qla8044_abort_isp,
2022 .iospace_config = qla82xx_iospace_config,
2023 .initialize_adapter = qla2x00_initialize_adapter,
2024 };
2025
2026 static struct isp_operations qla83xx_isp_ops = {
2027 .pci_config = qla25xx_pci_config,
2028 .reset_chip = qla24xx_reset_chip,
2029 .chip_diag = qla24xx_chip_diag,
2030 .config_rings = qla24xx_config_rings,
2031 .reset_adapter = qla24xx_reset_adapter,
2032 .nvram_config = qla81xx_nvram_config,
2033 .update_fw_options = qla81xx_update_fw_options,
2034 .load_risc = qla81xx_load_risc,
2035 .pci_info_str = qla24xx_pci_info_str,
2036 .fw_version_str = qla24xx_fw_version_str,
2037 .intr_handler = qla24xx_intr_handler,
2038 .enable_intrs = qla24xx_enable_intrs,
2039 .disable_intrs = qla24xx_disable_intrs,
2040 .abort_command = qla24xx_abort_command,
2041 .target_reset = qla24xx_abort_target,
2042 .lun_reset = qla24xx_lun_reset,
2043 .fabric_login = qla24xx_login_fabric,
2044 .fabric_logout = qla24xx_fabric_logout,
2045 .calc_req_entries = NULL,
2046 .build_iocbs = NULL,
2047 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2048 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2049 .read_nvram = NULL,
2050 .write_nvram = NULL,
2051 .fw_dump = qla83xx_fw_dump,
2052 .beacon_on = qla24xx_beacon_on,
2053 .beacon_off = qla24xx_beacon_off,
2054 .beacon_blink = qla83xx_beacon_blink,
2055 .read_optrom = qla25xx_read_optrom_data,
2056 .write_optrom = qla24xx_write_optrom_data,
2057 .get_flash_version = qla24xx_get_flash_version,
2058 .start_scsi = qla24xx_dif_start_scsi,
2059 .abort_isp = qla2x00_abort_isp,
2060 .iospace_config = qla83xx_iospace_config,
2061 .initialize_adapter = qla2x00_initialize_adapter,
2062 };
2063
2064 static struct isp_operations qlafx00_isp_ops = {
2065 .pci_config = qlafx00_pci_config,
2066 .reset_chip = qlafx00_soft_reset,
2067 .chip_diag = qlafx00_chip_diag,
2068 .config_rings = qlafx00_config_rings,
2069 .reset_adapter = qlafx00_soft_reset,
2070 .nvram_config = NULL,
2071 .update_fw_options = NULL,
2072 .load_risc = NULL,
2073 .pci_info_str = qlafx00_pci_info_str,
2074 .fw_version_str = qlafx00_fw_version_str,
2075 .intr_handler = qlafx00_intr_handler,
2076 .enable_intrs = qlafx00_enable_intrs,
2077 .disable_intrs = qlafx00_disable_intrs,
2078 .abort_command = qla24xx_async_abort_command,
2079 .target_reset = qlafx00_abort_target,
2080 .lun_reset = qlafx00_lun_reset,
2081 .fabric_login = NULL,
2082 .fabric_logout = NULL,
2083 .calc_req_entries = NULL,
2084 .build_iocbs = NULL,
2085 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2086 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2087 .read_nvram = qla24xx_read_nvram_data,
2088 .write_nvram = qla24xx_write_nvram_data,
2089 .fw_dump = NULL,
2090 .beacon_on = qla24xx_beacon_on,
2091 .beacon_off = qla24xx_beacon_off,
2092 .beacon_blink = NULL,
2093 .read_optrom = qla24xx_read_optrom_data,
2094 .write_optrom = qla24xx_write_optrom_data,
2095 .get_flash_version = qla24xx_get_flash_version,
2096 .start_scsi = qlafx00_start_scsi,
2097 .abort_isp = qlafx00_abort_isp,
2098 .iospace_config = qlafx00_iospace_config,
2099 .initialize_adapter = qlafx00_initialize_adapter,
2100 };
2101
2102 static struct isp_operations qla27xx_isp_ops = {
2103 .pci_config = qla25xx_pci_config,
2104 .reset_chip = qla24xx_reset_chip,
2105 .chip_diag = qla24xx_chip_diag,
2106 .config_rings = qla24xx_config_rings,
2107 .reset_adapter = qla24xx_reset_adapter,
2108 .nvram_config = qla81xx_nvram_config,
2109 .update_fw_options = qla81xx_update_fw_options,
2110 .load_risc = qla81xx_load_risc,
2111 .pci_info_str = qla24xx_pci_info_str,
2112 .fw_version_str = qla24xx_fw_version_str,
2113 .intr_handler = qla24xx_intr_handler,
2114 .enable_intrs = qla24xx_enable_intrs,
2115 .disable_intrs = qla24xx_disable_intrs,
2116 .abort_command = qla24xx_abort_command,
2117 .target_reset = qla24xx_abort_target,
2118 .lun_reset = qla24xx_lun_reset,
2119 .fabric_login = qla24xx_login_fabric,
2120 .fabric_logout = qla24xx_fabric_logout,
2121 .calc_req_entries = NULL,
2122 .build_iocbs = NULL,
2123 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2124 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2125 .read_nvram = NULL,
2126 .write_nvram = NULL,
2127 .fw_dump = qla27xx_fwdump,
2128 .beacon_on = qla24xx_beacon_on,
2129 .beacon_off = qla24xx_beacon_off,
2130 .beacon_blink = qla83xx_beacon_blink,
2131 .read_optrom = qla25xx_read_optrom_data,
2132 .write_optrom = qla24xx_write_optrom_data,
2133 .get_flash_version = qla24xx_get_flash_version,
2134 .start_scsi = qla24xx_dif_start_scsi,
2135 .abort_isp = qla2x00_abort_isp,
2136 .iospace_config = qla83xx_iospace_config,
2137 .initialize_adapter = qla2x00_initialize_adapter,
2138 };
2139
2140 static inline void
2141 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2142 {
2143 ha->device_type = DT_EXTENDED_IDS;
2144 switch (ha->pdev->device) {
2145 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2146 ha->device_type |= DT_ISP2100;
2147 ha->device_type &= ~DT_EXTENDED_IDS;
2148 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2149 break;
2150 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2151 ha->device_type |= DT_ISP2200;
2152 ha->device_type &= ~DT_EXTENDED_IDS;
2153 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2154 break;
2155 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2156 ha->device_type |= DT_ISP2300;
2157 ha->device_type |= DT_ZIO_SUPPORTED;
2158 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2159 break;
2160 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2161 ha->device_type |= DT_ISP2312;
2162 ha->device_type |= DT_ZIO_SUPPORTED;
2163 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2164 break;
2165 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2166 ha->device_type |= DT_ISP2322;
2167 ha->device_type |= DT_ZIO_SUPPORTED;
2168 if (ha->pdev->subsystem_vendor == 0x1028 &&
2169 ha->pdev->subsystem_device == 0x0170)
2170 ha->device_type |= DT_OEM_001;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2172 break;
2173 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2174 ha->device_type |= DT_ISP6312;
2175 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2176 break;
2177 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2178 ha->device_type |= DT_ISP6322;
2179 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2180 break;
2181 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2182 ha->device_type |= DT_ISP2422;
2183 ha->device_type |= DT_ZIO_SUPPORTED;
2184 ha->device_type |= DT_FWI2;
2185 ha->device_type |= DT_IIDMA;
2186 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2187 break;
2188 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2189 ha->device_type |= DT_ISP2432;
2190 ha->device_type |= DT_ZIO_SUPPORTED;
2191 ha->device_type |= DT_FWI2;
2192 ha->device_type |= DT_IIDMA;
2193 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2194 break;
2195 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2196 ha->device_type |= DT_ISP8432;
2197 ha->device_type |= DT_ZIO_SUPPORTED;
2198 ha->device_type |= DT_FWI2;
2199 ha->device_type |= DT_IIDMA;
2200 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2201 break;
2202 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2203 ha->device_type |= DT_ISP5422;
2204 ha->device_type |= DT_FWI2;
2205 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2206 break;
2207 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2208 ha->device_type |= DT_ISP5432;
2209 ha->device_type |= DT_FWI2;
2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2211 break;
2212 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2213 ha->device_type |= DT_ISP2532;
2214 ha->device_type |= DT_ZIO_SUPPORTED;
2215 ha->device_type |= DT_FWI2;
2216 ha->device_type |= DT_IIDMA;
2217 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2218 break;
2219 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2220 ha->device_type |= DT_ISP8001;
2221 ha->device_type |= DT_ZIO_SUPPORTED;
2222 ha->device_type |= DT_FWI2;
2223 ha->device_type |= DT_IIDMA;
2224 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2225 break;
2226 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2227 ha->device_type |= DT_ISP8021;
2228 ha->device_type |= DT_ZIO_SUPPORTED;
2229 ha->device_type |= DT_FWI2;
2230 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2231 /* Initialize 82XX ISP flags */
2232 qla82xx_init_flags(ha);
2233 break;
2234 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2235 ha->device_type |= DT_ISP8044;
2236 ha->device_type |= DT_ZIO_SUPPORTED;
2237 ha->device_type |= DT_FWI2;
2238 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2239 /* Initialize 82XX ISP flags */
2240 qla82xx_init_flags(ha);
2241 break;
2242 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2243 ha->device_type |= DT_ISP2031;
2244 ha->device_type |= DT_ZIO_SUPPORTED;
2245 ha->device_type |= DT_FWI2;
2246 ha->device_type |= DT_IIDMA;
2247 ha->device_type |= DT_T10_PI;
2248 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2249 break;
2250 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2251 ha->device_type |= DT_ISP8031;
2252 ha->device_type |= DT_ZIO_SUPPORTED;
2253 ha->device_type |= DT_FWI2;
2254 ha->device_type |= DT_IIDMA;
2255 ha->device_type |= DT_T10_PI;
2256 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2257 break;
2258 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2259 ha->device_type |= DT_ISPFX00;
2260 break;
2261 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2262 ha->device_type |= DT_ISP2071;
2263 ha->device_type |= DT_ZIO_SUPPORTED;
2264 ha->device_type |= DT_FWI2;
2265 ha->device_type |= DT_IIDMA;
2266 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2267 break;
2268 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2269 ha->device_type |= DT_ISP2271;
2270 ha->device_type |= DT_ZIO_SUPPORTED;
2271 ha->device_type |= DT_FWI2;
2272 ha->device_type |= DT_IIDMA;
2273 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2274 break;
2275 }
2276
2277 if (IS_QLA82XX(ha))
2278 ha->port_no = ha->portnum & 1;
2279 else {
2280 /* Get adapter physical port no from interrupt pin register. */
2281 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2282 if (IS_QLA27XX(ha))
2283 ha->port_no--;
2284 else
2285 ha->port_no = !(ha->port_no & 1);
2286 }
2287
2288 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2289 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2290 ha->device_type, ha->port_no, ha->fw_srisc_address);
2291 }
2292
2293 static void
2294 qla2xxx_scan_start(struct Scsi_Host *shost)
2295 {
2296 scsi_qla_host_t *vha = shost_priv(shost);
2297
2298 if (vha->hw->flags.running_gold_fw)
2299 return;
2300
2301 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2302 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2303 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2304 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2305 }
2306
2307 static int
2308 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2309 {
2310 scsi_qla_host_t *vha = shost_priv(shost);
2311
2312 if (!vha->host)
2313 return 1;
2314 if (time > vha->hw->loop_reset_delay * HZ)
2315 return 1;
2316
2317 return atomic_read(&vha->loop_state) == LOOP_READY;
2318 }
2319
2320 /*
2321 * PCI driver interface
2322 */
2323 static int
2324 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2325 {
2326 int ret = -ENODEV;
2327 struct Scsi_Host *host;
2328 scsi_qla_host_t *base_vha = NULL;
2329 struct qla_hw_data *ha;
2330 char pci_info[30];
2331 char fw_str[30], wq_name[30];
2332 struct scsi_host_template *sht;
2333 int bars, mem_only = 0;
2334 uint16_t req_length = 0, rsp_length = 0;
2335 struct req_que *req = NULL;
2336 struct rsp_que *rsp = NULL;
2337 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2338 sht = &qla2xxx_driver_template;
2339 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2340 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2341 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2342 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2343 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2344 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
2353 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2354 mem_only = 1;
2355 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2356 "Mem only adapter.\n");
2357 }
2358 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2359 "Bars=%d.\n", bars);
2360
2361 if (mem_only) {
2362 if (pci_enable_device_mem(pdev))
2363 goto probe_out;
2364 } else {
2365 if (pci_enable_device(pdev))
2366 goto probe_out;
2367 }
2368
2369 /* This may fail but that's ok */
2370 pci_enable_pcie_error_reporting(pdev);
2371
2372 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2373 if (!ha) {
2374 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2375 "Unable to allocate memory for ha.\n");
2376 goto probe_out;
2377 }
2378 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2379 "Memory allocated for ha=%p.\n", ha);
2380 ha->pdev = pdev;
2381 ha->tgt.enable_class_2 = ql2xenableclass2;
2382 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2383 spin_lock_init(&ha->tgt.q_full_lock);
2384
2385 /* Clear our data area */
2386 ha->bars = bars;
2387 ha->mem_only = mem_only;
2388 spin_lock_init(&ha->hardware_lock);
2389 spin_lock_init(&ha->vport_slock);
2390 mutex_init(&ha->selflogin_lock);
2391 mutex_init(&ha->optrom_mutex);
2392
2393 /* Set ISP-type information. */
2394 qla2x00_set_isp_flags(ha);
2395
2396 /* Set EEH reset type to fundamental if required by hba */
2397 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2398 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2399 pdev->needs_freset = 1;
2400
2401 ha->prev_topology = 0;
2402 ha->init_cb_size = sizeof(init_cb_t);
2403 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2404 ha->optrom_size = OPTROM_SIZE_2300;
2405
2406 /* Assign ISP specific operations. */
2407 if (IS_QLA2100(ha)) {
2408 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2409 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2410 req_length = REQUEST_ENTRY_CNT_2100;
2411 rsp_length = RESPONSE_ENTRY_CNT_2100;
2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2413 ha->gid_list_info_size = 4;
2414 ha->flash_conf_off = ~0;
2415 ha->flash_data_off = ~0;
2416 ha->nvram_conf_off = ~0;
2417 ha->nvram_data_off = ~0;
2418 ha->isp_ops = &qla2100_isp_ops;
2419 } else if (IS_QLA2200(ha)) {
2420 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2421 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2422 req_length = REQUEST_ENTRY_CNT_2200;
2423 rsp_length = RESPONSE_ENTRY_CNT_2100;
2424 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2425 ha->gid_list_info_size = 4;
2426 ha->flash_conf_off = ~0;
2427 ha->flash_data_off = ~0;
2428 ha->nvram_conf_off = ~0;
2429 ha->nvram_data_off = ~0;
2430 ha->isp_ops = &qla2100_isp_ops;
2431 } else if (IS_QLA23XX(ha)) {
2432 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2433 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2434 req_length = REQUEST_ENTRY_CNT_2200;
2435 rsp_length = RESPONSE_ENTRY_CNT_2300;
2436 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2437 ha->gid_list_info_size = 6;
2438 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2439 ha->optrom_size = OPTROM_SIZE_2322;
2440 ha->flash_conf_off = ~0;
2441 ha->flash_data_off = ~0;
2442 ha->nvram_conf_off = ~0;
2443 ha->nvram_data_off = ~0;
2444 ha->isp_ops = &qla2300_isp_ops;
2445 } else if (IS_QLA24XX_TYPE(ha)) {
2446 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2447 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2448 req_length = REQUEST_ENTRY_CNT_24XX;
2449 rsp_length = RESPONSE_ENTRY_CNT_2300;
2450 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2452 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2453 ha->gid_list_info_size = 8;
2454 ha->optrom_size = OPTROM_SIZE_24XX;
2455 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2456 ha->isp_ops = &qla24xx_isp_ops;
2457 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2458 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2459 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2460 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2461 } else if (IS_QLA25XX(ha)) {
2462 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2463 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2464 req_length = REQUEST_ENTRY_CNT_24XX;
2465 rsp_length = RESPONSE_ENTRY_CNT_2300;
2466 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2467 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2468 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2469 ha->gid_list_info_size = 8;
2470 ha->optrom_size = OPTROM_SIZE_25XX;
2471 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2472 ha->isp_ops = &qla25xx_isp_ops;
2473 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2474 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2475 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2476 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2477 } else if (IS_QLA81XX(ha)) {
2478 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2479 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2480 req_length = REQUEST_ENTRY_CNT_24XX;
2481 rsp_length = RESPONSE_ENTRY_CNT_2300;
2482 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2483 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2484 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2485 ha->gid_list_info_size = 8;
2486 ha->optrom_size = OPTROM_SIZE_81XX;
2487 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2488 ha->isp_ops = &qla81xx_isp_ops;
2489 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2490 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2491 ha->nvram_conf_off = ~0;
2492 ha->nvram_data_off = ~0;
2493 } else if (IS_QLA82XX(ha)) {
2494 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2495 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2496 req_length = REQUEST_ENTRY_CNT_82XX;
2497 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2498 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2499 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2500 ha->gid_list_info_size = 8;
2501 ha->optrom_size = OPTROM_SIZE_82XX;
2502 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2503 ha->isp_ops = &qla82xx_isp_ops;
2504 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2505 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2506 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2507 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2508 } else if (IS_QLA8044(ha)) {
2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2510 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2511 req_length = REQUEST_ENTRY_CNT_82XX;
2512 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2515 ha->gid_list_info_size = 8;
2516 ha->optrom_size = OPTROM_SIZE_83XX;
2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2518 ha->isp_ops = &qla8044_isp_ops;
2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2521 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2522 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2523 } else if (IS_QLA83XX(ha)) {
2524 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2525 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2526 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2527 req_length = REQUEST_ENTRY_CNT_83XX;
2528 rsp_length = RESPONSE_ENTRY_CNT_2300;
2529 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2530 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2531 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2532 ha->gid_list_info_size = 8;
2533 ha->optrom_size = OPTROM_SIZE_83XX;
2534 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2535 ha->isp_ops = &qla83xx_isp_ops;
2536 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2537 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2538 ha->nvram_conf_off = ~0;
2539 ha->nvram_data_off = ~0;
2540 } else if (IS_QLAFX00(ha)) {
2541 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2542 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2543 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2544 req_length = REQUEST_ENTRY_CNT_FX00;
2545 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2546 ha->isp_ops = &qlafx00_isp_ops;
2547 ha->port_down_retry_count = 30; /* default value */
2548 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2549 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2550 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2551 ha->mr.fw_hbt_en = 1;
2552 ha->mr.host_info_resend = false;
2553 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2554 } else if (IS_QLA27XX(ha)) {
2555 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2556 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2557 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2558 req_length = REQUEST_ENTRY_CNT_24XX;
2559 rsp_length = RESPONSE_ENTRY_CNT_2300;
2560 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2561 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2562 ha->gid_list_info_size = 8;
2563 ha->optrom_size = OPTROM_SIZE_83XX;
2564 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2565 ha->isp_ops = &qla27xx_isp_ops;
2566 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2567 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2568 ha->nvram_conf_off = ~0;
2569 ha->nvram_data_off = ~0;
2570 }
2571
2572 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2573 "mbx_count=%d, req_length=%d, "
2574 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2575 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2576 "max_fibre_devices=%d.\n",
2577 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2578 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2579 ha->nvram_npiv_size, ha->max_fibre_devices);
2580 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2581 "isp_ops=%p, flash_conf_off=%d, "
2582 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2583 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2584 ha->nvram_conf_off, ha->nvram_data_off);
2585
2586 /* Configure PCI I/O space */
2587 ret = ha->isp_ops->iospace_config(ha);
2588 if (ret)
2589 goto iospace_config_failed;
2590
2591 ql_log_pci(ql_log_info, pdev, 0x001d,
2592 "Found an ISP%04X irq %d iobase 0x%p.\n",
2593 pdev->device, pdev->irq, ha->iobase);
2594 mutex_init(&ha->vport_lock);
2595 init_completion(&ha->mbx_cmd_comp);
2596 complete(&ha->mbx_cmd_comp);
2597 init_completion(&ha->mbx_intr_comp);
2598 init_completion(&ha->dcbx_comp);
2599 init_completion(&ha->lb_portup_comp);
2600
2601 set_bit(0, (unsigned long *) ha->vp_idx_map);
2602
2603 qla2x00_config_dma_addressing(ha);
2604 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2605 "64 Bit addressing is %s.\n",
2606 ha->flags.enable_64bit_addressing ? "enable" :
2607 "disable");
2608 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2609 if (ret) {
2610 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2611 "Failed to allocate memory for adapter, aborting.\n");
2612
2613 goto probe_hw_failed;
2614 }
2615
2616 req->max_q_depth = MAX_Q_DEPTH;
2617 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2618 req->max_q_depth = ql2xmaxqdepth;
2619
2620
2621 base_vha = qla2x00_create_host(sht, ha);
2622 if (!base_vha) {
2623 ret = -ENOMEM;
2624 qla2x00_mem_free(ha);
2625 qla2x00_free_req_que(ha, req);
2626 qla2x00_free_rsp_que(ha, rsp);
2627 goto probe_hw_failed;
2628 }
2629
2630 pci_set_drvdata(pdev, base_vha);
2631 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2632
2633 host = base_vha->host;
2634 base_vha->req = req;
2635 if (IS_QLA2XXX_MIDTYPE(ha))
2636 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2637 else
2638 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2639 base_vha->vp_idx;
2640
2641 /* Setup fcport template structure. */
2642 ha->mr.fcport.vha = base_vha;
2643 ha->mr.fcport.port_type = FCT_UNKNOWN;
2644 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2645 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2646 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2647 ha->mr.fcport.scan_state = 1;
2648
2649 /* Set the SG table size based on ISP type */
2650 if (!IS_FWI2_CAPABLE(ha)) {
2651 if (IS_QLA2100(ha))
2652 host->sg_tablesize = 32;
2653 } else {
2654 if (!IS_QLA82XX(ha))
2655 host->sg_tablesize = QLA_SG_ALL;
2656 }
2657 host->max_id = ha->max_fibre_devices;
2658 host->cmd_per_lun = 3;
2659 host->unique_id = host->host_no;
2660 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2661 host->max_cmd_len = 32;
2662 else
2663 host->max_cmd_len = MAX_CMDSZ;
2664 host->max_channel = MAX_BUSES - 1;
2665 /* Older HBAs support only 16-bit LUNs */
2666 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2667 ql2xmaxlun > 0xffff)
2668 host->max_lun = 0xffff;
2669 else
2670 host->max_lun = ql2xmaxlun;
2671 host->transportt = qla2xxx_transport_template;
2672 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2673
2674 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2675 "max_id=%d this_id=%d "
2676 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2677 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2678 host->this_id, host->cmd_per_lun, host->unique_id,
2679 host->max_cmd_len, host->max_channel, host->max_lun,
2680 host->transportt, sht->vendor_id);
2681
2682 que_init:
2683 /* Alloc arrays of request and response ring ptrs */
2684 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2685 ql_log(ql_log_fatal, base_vha, 0x003d,
2686 "Failed to allocate memory for queue pointers..."
2687 "aborting.\n");
2688 goto probe_init_failed;
2689 }
2690
2691 qlt_probe_one_stage1(base_vha, ha);
2692
2693 /* Set up the irqs */
2694 ret = qla2x00_request_irqs(ha, rsp);
2695 if (ret)
2696 goto probe_init_failed;
2697
2698 pci_save_state(pdev);
2699
2700 /* Assign back pointers */
2701 rsp->req = req;
2702 req->rsp = rsp;
2703
2704 if (IS_QLAFX00(ha)) {
2705 ha->rsp_q_map[0] = rsp;
2706 ha->req_q_map[0] = req;
2707 set_bit(0, ha->req_qid_map);
2708 set_bit(0, ha->rsp_qid_map);
2709 }
2710
2711 /* FWI2-capable only. */
2712 req->req_q_in = &ha->iobase->isp24.req_q_in;
2713 req->req_q_out = &ha->iobase->isp24.req_q_out;
2714 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2715 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2716 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2717 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2718 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2719 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2720 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2721 }
2722
2723 if (IS_QLAFX00(ha)) {
2724 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2725 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2726 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2727 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2728 }
2729
2730 if (IS_P3P_TYPE(ha)) {
2731 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2732 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2733 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2734 }
2735
2736 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2737 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2738 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2739 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2740 "req->req_q_in=%p req->req_q_out=%p "
2741 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2742 req->req_q_in, req->req_q_out,
2743 rsp->rsp_q_in, rsp->rsp_q_out);
2744 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2745 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2746 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2747 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2748 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2749 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2750
2751 if (ha->isp_ops->initialize_adapter(base_vha)) {
2752 ql_log(ql_log_fatal, base_vha, 0x00d6,
2753 "Failed to initialize adapter - Adapter flags %x.\n",
2754 base_vha->device_flags);
2755
2756 if (IS_QLA82XX(ha)) {
2757 qla82xx_idc_lock(ha);
2758 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2759 QLA8XXX_DEV_FAILED);
2760 qla82xx_idc_unlock(ha);
2761 ql_log(ql_log_fatal, base_vha, 0x00d7,
2762 "HW State: FAILED.\n");
2763 } else if (IS_QLA8044(ha)) {
2764 qla8044_idc_lock(ha);
2765 qla8044_wr_direct(base_vha,
2766 QLA8044_CRB_DEV_STATE_INDEX,
2767 QLA8XXX_DEV_FAILED);
2768 qla8044_idc_unlock(ha);
2769 ql_log(ql_log_fatal, base_vha, 0x0150,
2770 "HW State: FAILED.\n");
2771 }
2772
2773 ret = -ENODEV;
2774 goto probe_failed;
2775 }
2776
2777 if (IS_QLAFX00(ha))
2778 host->can_queue = QLAFX00_MAX_CANQUEUE;
2779 else
2780 host->can_queue = req->num_outstanding_cmds - 10;
2781
2782 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2783 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2784 host->can_queue, base_vha->req,
2785 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2786
2787 if (ha->mqenable) {
2788 if (qla25xx_setup_mode(base_vha)) {
2789 ql_log(ql_log_warn, base_vha, 0x00ec,
2790 "Failed to create queues, falling back to single queue mode.\n");
2791 goto que_init;
2792 }
2793 }
2794
2795 if (ha->flags.running_gold_fw)
2796 goto skip_dpc;
2797
2798 /*
2799 * Startup the kernel thread for this host adapter
2800 */
2801 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2802 "%s_dpc", base_vha->host_str);
2803 if (IS_ERR(ha->dpc_thread)) {
2804 ql_log(ql_log_fatal, base_vha, 0x00ed,
2805 "Failed to start DPC thread.\n");
2806 ret = PTR_ERR(ha->dpc_thread);
2807 goto probe_failed;
2808 }
2809 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2810 "DPC thread started successfully.\n");
2811
2812 /*
2813 * If we're not coming up in initiator mode, we might sit for
2814 * a while without waking up the dpc thread, which leads to a
2815 * stuck process warning. So just kick the dpc once here and
2816 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2817 */
2818 qla2xxx_wake_dpc(base_vha);
2819
2820 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2821
2822 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2823 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2824 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2825 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2826
2827 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2828 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2829 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2830 INIT_WORK(&ha->idc_state_handler,
2831 qla83xx_idc_state_handler_work);
2832 INIT_WORK(&ha->nic_core_unrecoverable,
2833 qla83xx_nic_core_unrecoverable_work);
2834 }
2835
2836 skip_dpc:
2837 list_add_tail(&base_vha->list, &ha->vp_list);
2838 base_vha->host->irq = ha->pdev->irq;
2839
2840 /* Initialized the timer */
2841 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2842 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2843 "Started qla2x00_timer with "
2844 "interval=%d.\n", WATCH_INTERVAL);
2845 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2846 "Detected hba at address=%p.\n",
2847 ha);
2848
2849 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2850 if (ha->fw_attributes & BIT_4) {
2851 int prot = 0, guard;
2852 base_vha->flags.difdix_supported = 1;
2853 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2854 "Registering for DIF/DIX type 1 and 3 protection.\n");
2855 if (ql2xenabledif == 1)
2856 prot = SHOST_DIX_TYPE0_PROTECTION;
2857 scsi_host_set_prot(host,
2858 prot | SHOST_DIF_TYPE1_PROTECTION
2859 | SHOST_DIF_TYPE2_PROTECTION
2860 | SHOST_DIF_TYPE3_PROTECTION
2861 | SHOST_DIX_TYPE1_PROTECTION
2862 | SHOST_DIX_TYPE2_PROTECTION
2863 | SHOST_DIX_TYPE3_PROTECTION);
2864
2865 guard = SHOST_DIX_GUARD_CRC;
2866
2867 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2868 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2869 guard |= SHOST_DIX_GUARD_IP;
2870
2871 scsi_host_set_guard(host, guard);
2872 } else
2873 base_vha->flags.difdix_supported = 0;
2874 }
2875
2876 ha->isp_ops->enable_intrs(ha);
2877
2878 if (IS_QLAFX00(ha)) {
2879 ret = qlafx00_fx_disc(base_vha,
2880 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2881 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2882 QLA_SG_ALL : 128;
2883 }
2884
2885 ret = scsi_add_host(host, &pdev->dev);
2886 if (ret)
2887 goto probe_failed;
2888
2889 base_vha->flags.init_done = 1;
2890 base_vha->flags.online = 1;
2891 ha->prev_minidump_failed = 0;
2892
2893 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2894 "Init done and hba is online.\n");
2895
2896 if (qla_ini_mode_enabled(base_vha))
2897 scsi_scan_host(host);
2898 else
2899 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2900 "skipping scsi_scan_host() for non-initiator port\n");
2901
2902 qla2x00_alloc_sysfs_attr(base_vha);
2903
2904 if (IS_QLAFX00(ha)) {
2905 ret = qlafx00_fx_disc(base_vha,
2906 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2907
2908 /* Register system information */
2909 ret = qlafx00_fx_disc(base_vha,
2910 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2911 }
2912
2913 qla2x00_init_host_attr(base_vha);
2914
2915 qla2x00_dfs_setup(base_vha);
2916
2917 ql_log(ql_log_info, base_vha, 0x00fb,
2918 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2919 ql_log(ql_log_info, base_vha, 0x00fc,
2920 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2921 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2922 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2923 base_vha->host_no,
2924 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2925
2926 qlt_add_target(ha, base_vha);
2927
2928 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2929 return 0;
2930
2931 probe_init_failed:
2932 qla2x00_free_req_que(ha, req);
2933 ha->req_q_map[0] = NULL;
2934 clear_bit(0, ha->req_qid_map);
2935 qla2x00_free_rsp_que(ha, rsp);
2936 ha->rsp_q_map[0] = NULL;
2937 clear_bit(0, ha->rsp_qid_map);
2938 ha->max_req_queues = ha->max_rsp_queues = 0;
2939
2940 probe_failed:
2941 if (base_vha->timer_active)
2942 qla2x00_stop_timer(base_vha);
2943 base_vha->flags.online = 0;
2944 if (ha->dpc_thread) {
2945 struct task_struct *t = ha->dpc_thread;
2946
2947 ha->dpc_thread = NULL;
2948 kthread_stop(t);
2949 }
2950
2951 qla2x00_free_device(base_vha);
2952
2953 scsi_host_put(base_vha->host);
2954
2955 probe_hw_failed:
2956 qla2x00_clear_drv_active(ha);
2957
2958 iospace_config_failed:
2959 if (IS_P3P_TYPE(ha)) {
2960 if (!ha->nx_pcibase)
2961 iounmap((device_reg_t *)ha->nx_pcibase);
2962 if (!ql2xdbwr)
2963 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2964 } else {
2965 if (ha->iobase)
2966 iounmap(ha->iobase);
2967 if (ha->cregbase)
2968 iounmap(ha->cregbase);
2969 }
2970 pci_release_selected_regions(ha->pdev, ha->bars);
2971 kfree(ha);
2972 ha = NULL;
2973
2974 probe_out:
2975 pci_disable_device(pdev);
2976 return ret;
2977 }
2978
2979 static void
2980 qla2x00_shutdown(struct pci_dev *pdev)
2981 {
2982 scsi_qla_host_t *vha;
2983 struct qla_hw_data *ha;
2984
2985 if (!atomic_read(&pdev->enable_cnt))
2986 return;
2987
2988 vha = pci_get_drvdata(pdev);
2989 ha = vha->hw;
2990
2991 /* Notify ISPFX00 firmware */
2992 if (IS_QLAFX00(ha))
2993 qlafx00_driver_shutdown(vha, 20);
2994
2995 /* Turn-off FCE trace */
2996 if (ha->flags.fce_enabled) {
2997 qla2x00_disable_fce_trace(vha, NULL, NULL);
2998 ha->flags.fce_enabled = 0;
2999 }
3000
3001 /* Turn-off EFT trace */
3002 if (ha->eft)
3003 qla2x00_disable_eft_trace(vha);
3004
3005 /* Stop currently executing firmware. */
3006 qla2x00_try_to_stop_firmware(vha);
3007
3008 /* Turn adapter off line */
3009 vha->flags.online = 0;
3010
3011 /* turn-off interrupts on the card */
3012 if (ha->interrupts_on) {
3013 vha->flags.init_done = 0;
3014 ha->isp_ops->disable_intrs(ha);
3015 }
3016
3017 qla2x00_free_irqs(vha);
3018
3019 qla2x00_free_fw_dump(ha);
3020
3021 pci_disable_pcie_error_reporting(pdev);
3022 pci_disable_device(pdev);
3023 }
3024
3025 /* Deletes all the virtual ports for a given ha */
3026 static void
3027 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3028 {
3029 struct Scsi_Host *scsi_host;
3030 scsi_qla_host_t *vha;
3031 unsigned long flags;
3032
3033 mutex_lock(&ha->vport_lock);
3034 while (ha->cur_vport_count) {
3035 spin_lock_irqsave(&ha->vport_slock, flags);
3036
3037 BUG_ON(base_vha->list.next == &ha->vp_list);
3038 /* This assumes first entry in ha->vp_list is always base vha */
3039 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3040 scsi_host = scsi_host_get(vha->host);
3041
3042 spin_unlock_irqrestore(&ha->vport_slock, flags);
3043 mutex_unlock(&ha->vport_lock);
3044
3045 fc_vport_terminate(vha->fc_vport);
3046 scsi_host_put(vha->host);
3047
3048 mutex_lock(&ha->vport_lock);
3049 }
3050 mutex_unlock(&ha->vport_lock);
3051 }
3052
3053 /* Stops all deferred work threads */
3054 static void
3055 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3056 {
3057 /* Flush the work queue and remove it */
3058 if (ha->wq) {
3059 flush_workqueue(ha->wq);
3060 destroy_workqueue(ha->wq);
3061 ha->wq = NULL;
3062 }
3063
3064 /* Cancel all work and destroy DPC workqueues */
3065 if (ha->dpc_lp_wq) {
3066 cancel_work_sync(&ha->idc_aen);
3067 destroy_workqueue(ha->dpc_lp_wq);
3068 ha->dpc_lp_wq = NULL;
3069 }
3070
3071 if (ha->dpc_hp_wq) {
3072 cancel_work_sync(&ha->nic_core_reset);
3073 cancel_work_sync(&ha->idc_state_handler);
3074 cancel_work_sync(&ha->nic_core_unrecoverable);
3075 destroy_workqueue(ha->dpc_hp_wq);
3076 ha->dpc_hp_wq = NULL;
3077 }
3078
3079 /* Kill the kernel thread for this host */
3080 if (ha->dpc_thread) {
3081 struct task_struct *t = ha->dpc_thread;
3082
3083 /*
3084 * qla2xxx_wake_dpc checks for ->dpc_thread
3085 * so we need to zero it out.
3086 */
3087 ha->dpc_thread = NULL;
3088 kthread_stop(t);
3089 }
3090 }
3091
3092 static void
3093 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3094 {
3095 if (IS_QLA82XX(ha)) {
3096
3097 iounmap((device_reg_t *)ha->nx_pcibase);
3098 if (!ql2xdbwr)
3099 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3100 } else {
3101 if (ha->iobase)
3102 iounmap(ha->iobase);
3103
3104 if (ha->cregbase)
3105 iounmap(ha->cregbase);
3106
3107 if (ha->mqiobase)
3108 iounmap(ha->mqiobase);
3109
3110 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3111 iounmap(ha->msixbase);
3112 }
3113 }
3114
3115 static void
3116 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3117 {
3118 if (IS_QLA8044(ha)) {
3119 qla8044_idc_lock(ha);
3120 qla8044_clear_drv_active(ha);
3121 qla8044_idc_unlock(ha);
3122 } else if (IS_QLA82XX(ha)) {
3123 qla82xx_idc_lock(ha);
3124 qla82xx_clear_drv_active(ha);
3125 qla82xx_idc_unlock(ha);
3126 }
3127 }
3128
3129 static void
3130 qla2x00_remove_one(struct pci_dev *pdev)
3131 {
3132 scsi_qla_host_t *base_vha;
3133 struct qla_hw_data *ha;
3134
3135 base_vha = pci_get_drvdata(pdev);
3136 ha = base_vha->hw;
3137
3138 /* Indicate device removal to prevent future board_disable and wait
3139 * until any pending board_disable has completed. */
3140 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3141 cancel_work_sync(&ha->board_disable);
3142
3143 /*
3144 * If the PCI device is disabled then there was a PCI-disconnect and
3145 * qla2x00_disable_board_on_pci_error has taken care of most of the
3146 * resources.
3147 */
3148 if (!atomic_read(&pdev->enable_cnt)) {
3149 scsi_host_put(base_vha->host);
3150 kfree(ha);
3151 pci_set_drvdata(pdev, NULL);
3152 return;
3153 }
3154
3155 qla2x00_wait_for_hba_ready(base_vha);
3156
3157 set_bit(UNLOADING, &base_vha->dpc_flags);
3158
3159 if (IS_QLAFX00(ha))
3160 qlafx00_driver_shutdown(base_vha, 20);
3161
3162 qla2x00_delete_all_vps(ha, base_vha);
3163
3164 if (IS_QLA8031(ha)) {
3165 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3166 "Clearing fcoe driver presence.\n");
3167 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3168 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3169 "Error while clearing DRV-Presence.\n");
3170 }
3171
3172 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3173
3174 qla2x00_dfs_remove(base_vha);
3175
3176 qla84xx_put_chip(base_vha);
3177
3178 /* Laser should be disabled only for ISP2031 */
3179 if (IS_QLA2031(ha))
3180 qla83xx_disable_laser(base_vha);
3181
3182 /* Disable timer */
3183 if (base_vha->timer_active)
3184 qla2x00_stop_timer(base_vha);
3185
3186 base_vha->flags.online = 0;
3187
3188 qla2x00_destroy_deferred_work(ha);
3189
3190 qlt_remove_target(ha, base_vha);
3191
3192 qla2x00_free_sysfs_attr(base_vha, true);
3193
3194 fc_remove_host(base_vha->host);
3195
3196 scsi_remove_host(base_vha->host);
3197
3198 qla2x00_free_device(base_vha);
3199
3200 qla2x00_clear_drv_active(ha);
3201
3202 scsi_host_put(base_vha->host);
3203
3204 qla2x00_unmap_iobases(ha);
3205
3206 pci_release_selected_regions(ha->pdev, ha->bars);
3207 kfree(ha);
3208 ha = NULL;
3209
3210 pci_disable_pcie_error_reporting(pdev);
3211
3212 pci_disable_device(pdev);
3213 }
3214
3215 static void
3216 qla2x00_free_device(scsi_qla_host_t *vha)
3217 {
3218 struct qla_hw_data *ha = vha->hw;
3219
3220 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3221
3222 /* Disable timer */
3223 if (vha->timer_active)
3224 qla2x00_stop_timer(vha);
3225
3226 qla25xx_delete_queues(vha);
3227
3228 if (ha->flags.fce_enabled)
3229 qla2x00_disable_fce_trace(vha, NULL, NULL);
3230
3231 if (ha->eft)
3232 qla2x00_disable_eft_trace(vha);
3233
3234 /* Stop currently executing firmware. */
3235 qla2x00_try_to_stop_firmware(vha);
3236
3237 vha->flags.online = 0;
3238
3239 /* turn-off interrupts on the card */
3240 if (ha->interrupts_on) {
3241 vha->flags.init_done = 0;
3242 ha->isp_ops->disable_intrs(ha);
3243 }
3244
3245 qla2x00_free_irqs(vha);
3246
3247 qla2x00_free_fcports(vha);
3248
3249 qla2x00_mem_free(ha);
3250
3251 qla82xx_md_free(vha);
3252
3253 qla2x00_free_queues(ha);
3254 }
3255
3256 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3257 {
3258 fc_port_t *fcport, *tfcport;
3259
3260 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3261 list_del(&fcport->list);
3262 qla2x00_clear_loop_id(fcport);
3263 kfree(fcport);
3264 fcport = NULL;
3265 }
3266 }
3267
3268 static inline void
3269 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3270 int defer)
3271 {
3272 struct fc_rport *rport;
3273 scsi_qla_host_t *base_vha;
3274 unsigned long flags;
3275
3276 if (!fcport->rport)
3277 return;
3278
3279 rport = fcport->rport;
3280 if (defer) {
3281 base_vha = pci_get_drvdata(vha->hw->pdev);
3282 spin_lock_irqsave(vha->host->host_lock, flags);
3283 fcport->drport = rport;
3284 spin_unlock_irqrestore(vha->host->host_lock, flags);
3285 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3286 qla2xxx_wake_dpc(base_vha);
3287 } else {
3288 fc_remote_port_delete(rport);
3289 qlt_fc_port_deleted(vha, fcport);
3290 }
3291 }
3292
3293 /*
3294 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3295 *
3296 * Input: ha = adapter block pointer. fcport = port structure pointer.
3297 *
3298 * Return: None.
3299 *
3300 * Context:
3301 */
3302 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3303 int do_login, int defer)
3304 {
3305 if (IS_QLAFX00(vha->hw)) {
3306 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3307 qla2x00_schedule_rport_del(vha, fcport, defer);
3308 return;
3309 }
3310
3311 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3312 vha->vp_idx == fcport->vha->vp_idx) {
3313 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3314 qla2x00_schedule_rport_del(vha, fcport, defer);
3315 }
3316 /*
3317 * We may need to retry the login, so don't change the state of the
3318 * port but do the retries.
3319 */
3320 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3321 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3322
3323 if (!do_login)
3324 return;
3325
3326 if (fcport->login_retry == 0) {
3327 fcport->login_retry = vha->hw->login_retry_count;
3328 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3329
3330 ql_dbg(ql_dbg_disc, vha, 0x2067,
3331 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3332 fcport->port_name, fcport->loop_id, fcport->login_retry);
3333 }
3334 }
3335
3336 /*
3337 * qla2x00_mark_all_devices_lost
3338 * Updates fcport state when device goes offline.
3339 *
3340 * Input:
3341 * ha = adapter block pointer.
3342 * fcport = port structure pointer.
3343 *
3344 * Return:
3345 * None.
3346 *
3347 * Context:
3348 */
3349 void
3350 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3351 {
3352 fc_port_t *fcport;
3353
3354 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3355 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3356 continue;
3357
3358 /*
3359 * No point in marking the device as lost, if the device is
3360 * already DEAD.
3361 */
3362 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3363 continue;
3364 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3365 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3366 if (defer)
3367 qla2x00_schedule_rport_del(vha, fcport, defer);
3368 else if (vha->vp_idx == fcport->vha->vp_idx)
3369 qla2x00_schedule_rport_del(vha, fcport, defer);
3370 }
3371 }
3372 }
3373
3374 /*
3375 * qla2x00_mem_alloc
3376 * Allocates adapter memory.
3377 *
3378 * Returns:
3379 * 0 = success.
3380 * !0 = failure.
3381 */
3382 static int
3383 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3384 struct req_que **req, struct rsp_que **rsp)
3385 {
3386 char name[16];
3387
3388 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3389 &ha->init_cb_dma, GFP_KERNEL);
3390 if (!ha->init_cb)
3391 goto fail;
3392
3393 if (qlt_mem_alloc(ha) < 0)
3394 goto fail_free_init_cb;
3395
3396 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3397 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3398 if (!ha->gid_list)
3399 goto fail_free_tgt_mem;
3400
3401 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3402 if (!ha->srb_mempool)
3403 goto fail_free_gid_list;
3404
3405 if (IS_P3P_TYPE(ha)) {
3406 /* Allocate cache for CT6 Ctx. */
3407 if (!ctx_cachep) {
3408 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3409 sizeof(struct ct6_dsd), 0,
3410 SLAB_HWCACHE_ALIGN, NULL);
3411 if (!ctx_cachep)
3412 goto fail_free_gid_list;
3413 }
3414 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3415 ctx_cachep);
3416 if (!ha->ctx_mempool)
3417 goto fail_free_srb_mempool;
3418 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3419 "ctx_cachep=%p ctx_mempool=%p.\n",
3420 ctx_cachep, ha->ctx_mempool);
3421 }
3422
3423 /* Get memory for cached NVRAM */
3424 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3425 if (!ha->nvram)
3426 goto fail_free_ctx_mempool;
3427
3428 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3429 ha->pdev->device);
3430 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3431 DMA_POOL_SIZE, 8, 0);
3432 if (!ha->s_dma_pool)
3433 goto fail_free_nvram;
3434
3435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3436 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3437 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3438
3439 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3440 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3441 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3442 if (!ha->dl_dma_pool) {
3443 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3444 "Failed to allocate memory for dl_dma_pool.\n");
3445 goto fail_s_dma_pool;
3446 }
3447
3448 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3449 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3450 if (!ha->fcp_cmnd_dma_pool) {
3451 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3452 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3453 goto fail_dl_dma_pool;
3454 }
3455 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3456 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3457 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3458 }
3459
3460 /* Allocate memory for SNS commands */
3461 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3462 /* Get consistent memory allocated for SNS commands */
3463 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3464 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3465 if (!ha->sns_cmd)
3466 goto fail_dma_pool;
3467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3468 "sns_cmd: %p.\n", ha->sns_cmd);
3469 } else {
3470 /* Get consistent memory allocated for MS IOCB */
3471 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3472 &ha->ms_iocb_dma);
3473 if (!ha->ms_iocb)
3474 goto fail_dma_pool;
3475 /* Get consistent memory allocated for CT SNS commands */
3476 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3477 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3478 if (!ha->ct_sns)
3479 goto fail_free_ms_iocb;
3480 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3481 "ms_iocb=%p ct_sns=%p.\n",
3482 ha->ms_iocb, ha->ct_sns);
3483 }
3484
3485 /* Allocate memory for request ring */
3486 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3487 if (!*req) {
3488 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3489 "Failed to allocate memory for req.\n");
3490 goto fail_req;
3491 }
3492 (*req)->length = req_len;
3493 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3494 ((*req)->length + 1) * sizeof(request_t),
3495 &(*req)->dma, GFP_KERNEL);
3496 if (!(*req)->ring) {
3497 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3498 "Failed to allocate memory for req_ring.\n");
3499 goto fail_req_ring;
3500 }
3501 /* Allocate memory for response ring */
3502 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3503 if (!*rsp) {
3504 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3505 "Failed to allocate memory for rsp.\n");
3506 goto fail_rsp;
3507 }
3508 (*rsp)->hw = ha;
3509 (*rsp)->length = rsp_len;
3510 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3511 ((*rsp)->length + 1) * sizeof(response_t),
3512 &(*rsp)->dma, GFP_KERNEL);
3513 if (!(*rsp)->ring) {
3514 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3515 "Failed to allocate memory for rsp_ring.\n");
3516 goto fail_rsp_ring;
3517 }
3518 (*req)->rsp = *rsp;
3519 (*rsp)->req = *req;
3520 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3521 "req=%p req->length=%d req->ring=%p rsp=%p "
3522 "rsp->length=%d rsp->ring=%p.\n",
3523 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3524 (*rsp)->ring);
3525 /* Allocate memory for NVRAM data for vports */
3526 if (ha->nvram_npiv_size) {
3527 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3528 ha->nvram_npiv_size, GFP_KERNEL);
3529 if (!ha->npiv_info) {
3530 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3531 "Failed to allocate memory for npiv_info.\n");
3532 goto fail_npiv_info;
3533 }
3534 } else
3535 ha->npiv_info = NULL;
3536
3537 /* Get consistent memory allocated for EX-INIT-CB. */
3538 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3539 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3540 &ha->ex_init_cb_dma);
3541 if (!ha->ex_init_cb)
3542 goto fail_ex_init_cb;
3543 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3544 "ex_init_cb=%p.\n", ha->ex_init_cb);
3545 }
3546
3547 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3548
3549 /* Get consistent memory allocated for Async Port-Database. */
3550 if (!IS_FWI2_CAPABLE(ha)) {
3551 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3552 &ha->async_pd_dma);
3553 if (!ha->async_pd)
3554 goto fail_async_pd;
3555 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3556 "async_pd=%p.\n", ha->async_pd);
3557 }
3558
3559 INIT_LIST_HEAD(&ha->vp_list);
3560
3561 /* Allocate memory for our loop_id bitmap */
3562 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3563 GFP_KERNEL);
3564 if (!ha->loop_id_map)
3565 goto fail_async_pd;
3566 else {
3567 qla2x00_set_reserved_loop_ids(ha);
3568 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3569 "loop_id_map=%p.\n", ha->loop_id_map);
3570 }
3571
3572 return 0;
3573
3574 fail_async_pd:
3575 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3576 fail_ex_init_cb:
3577 kfree(ha->npiv_info);
3578 fail_npiv_info:
3579 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3580 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3581 (*rsp)->ring = NULL;
3582 (*rsp)->dma = 0;
3583 fail_rsp_ring:
3584 kfree(*rsp);
3585 fail_rsp:
3586 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3587 sizeof(request_t), (*req)->ring, (*req)->dma);
3588 (*req)->ring = NULL;
3589 (*req)->dma = 0;
3590 fail_req_ring:
3591 kfree(*req);
3592 fail_req:
3593 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3594 ha->ct_sns, ha->ct_sns_dma);
3595 ha->ct_sns = NULL;
3596 ha->ct_sns_dma = 0;
3597 fail_free_ms_iocb:
3598 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3599 ha->ms_iocb = NULL;
3600 ha->ms_iocb_dma = 0;
3601 fail_dma_pool:
3602 if (IS_QLA82XX(ha) || ql2xenabledif) {
3603 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3604 ha->fcp_cmnd_dma_pool = NULL;
3605 }
3606 fail_dl_dma_pool:
3607 if (IS_QLA82XX(ha) || ql2xenabledif) {
3608 dma_pool_destroy(ha->dl_dma_pool);
3609 ha->dl_dma_pool = NULL;
3610 }
3611 fail_s_dma_pool:
3612 dma_pool_destroy(ha->s_dma_pool);
3613 ha->s_dma_pool = NULL;
3614 fail_free_nvram:
3615 kfree(ha->nvram);
3616 ha->nvram = NULL;
3617 fail_free_ctx_mempool:
3618 mempool_destroy(ha->ctx_mempool);
3619 ha->ctx_mempool = NULL;
3620 fail_free_srb_mempool:
3621 mempool_destroy(ha->srb_mempool);
3622 ha->srb_mempool = NULL;
3623 fail_free_gid_list:
3624 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3625 ha->gid_list,
3626 ha->gid_list_dma);
3627 ha->gid_list = NULL;
3628 ha->gid_list_dma = 0;
3629 fail_free_tgt_mem:
3630 qlt_mem_free(ha);
3631 fail_free_init_cb:
3632 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3633 ha->init_cb_dma);
3634 ha->init_cb = NULL;
3635 ha->init_cb_dma = 0;
3636 fail:
3637 ql_log(ql_log_fatal, NULL, 0x0030,
3638 "Memory allocation failure.\n");
3639 return -ENOMEM;
3640 }
3641
3642 /*
3643 * qla2x00_free_fw_dump
3644 * Frees fw dump stuff.
3645 *
3646 * Input:
3647 * ha = adapter block pointer
3648 */
3649 static void
3650 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3651 {
3652 if (ha->fce)
3653 dma_free_coherent(&ha->pdev->dev,
3654 FCE_SIZE, ha->fce, ha->fce_dma);
3655
3656 if (ha->eft)
3657 dma_free_coherent(&ha->pdev->dev,
3658 EFT_SIZE, ha->eft, ha->eft_dma);
3659
3660 if (ha->fw_dump)
3661 vfree(ha->fw_dump);
3662 if (ha->fw_dump_template)
3663 vfree(ha->fw_dump_template);
3664
3665 ha->fce = NULL;
3666 ha->fce_dma = 0;
3667 ha->eft = NULL;
3668 ha->eft_dma = 0;
3669 ha->fw_dumped = 0;
3670 ha->fw_dump_cap_flags = 0;
3671 ha->fw_dump_reading = 0;
3672 ha->fw_dump = NULL;
3673 ha->fw_dump_len = 0;
3674 ha->fw_dump_template = NULL;
3675 ha->fw_dump_template_len = 0;
3676 }
3677
3678 /*
3679 * qla2x00_mem_free
3680 * Frees all adapter allocated memory.
3681 *
3682 * Input:
3683 * ha = adapter block pointer.
3684 */
3685 static void
3686 qla2x00_mem_free(struct qla_hw_data *ha)
3687 {
3688 qla2x00_free_fw_dump(ha);
3689
3690 if (ha->mctp_dump)
3691 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3692 ha->mctp_dump_dma);
3693
3694 if (ha->srb_mempool)
3695 mempool_destroy(ha->srb_mempool);
3696
3697 if (ha->dcbx_tlv)
3698 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3699 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3700
3701 if (ha->xgmac_data)
3702 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3703 ha->xgmac_data, ha->xgmac_data_dma);
3704
3705 if (ha->sns_cmd)
3706 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3707 ha->sns_cmd, ha->sns_cmd_dma);
3708
3709 if (ha->ct_sns)
3710 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3711 ha->ct_sns, ha->ct_sns_dma);
3712
3713 if (ha->sfp_data)
3714 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3715
3716 if (ha->ms_iocb)
3717 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3718
3719 if (ha->ex_init_cb)
3720 dma_pool_free(ha->s_dma_pool,
3721 ha->ex_init_cb, ha->ex_init_cb_dma);
3722
3723 if (ha->async_pd)
3724 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3725
3726 if (ha->s_dma_pool)
3727 dma_pool_destroy(ha->s_dma_pool);
3728
3729 if (ha->gid_list)
3730 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3731 ha->gid_list, ha->gid_list_dma);
3732
3733 if (IS_QLA82XX(ha)) {
3734 if (!list_empty(&ha->gbl_dsd_list)) {
3735 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3736
3737 /* clean up allocated prev pool */
3738 list_for_each_entry_safe(dsd_ptr,
3739 tdsd_ptr, &ha->gbl_dsd_list, list) {
3740 dma_pool_free(ha->dl_dma_pool,
3741 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3742 list_del(&dsd_ptr->list);
3743 kfree(dsd_ptr);
3744 }
3745 }
3746 }
3747
3748 if (ha->dl_dma_pool)
3749 dma_pool_destroy(ha->dl_dma_pool);
3750
3751 if (ha->fcp_cmnd_dma_pool)
3752 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3753
3754 if (ha->ctx_mempool)
3755 mempool_destroy(ha->ctx_mempool);
3756
3757 qlt_mem_free(ha);
3758
3759 if (ha->init_cb)
3760 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3761 ha->init_cb, ha->init_cb_dma);
3762 vfree(ha->optrom_buffer);
3763 kfree(ha->nvram);
3764 kfree(ha->npiv_info);
3765 kfree(ha->swl);
3766 kfree(ha->loop_id_map);
3767
3768 ha->srb_mempool = NULL;
3769 ha->ctx_mempool = NULL;
3770 ha->sns_cmd = NULL;
3771 ha->sns_cmd_dma = 0;
3772 ha->ct_sns = NULL;
3773 ha->ct_sns_dma = 0;
3774 ha->ms_iocb = NULL;
3775 ha->ms_iocb_dma = 0;
3776 ha->init_cb = NULL;
3777 ha->init_cb_dma = 0;
3778 ha->ex_init_cb = NULL;
3779 ha->ex_init_cb_dma = 0;
3780 ha->async_pd = NULL;
3781 ha->async_pd_dma = 0;
3782
3783 ha->s_dma_pool = NULL;
3784 ha->dl_dma_pool = NULL;
3785 ha->fcp_cmnd_dma_pool = NULL;
3786
3787 ha->gid_list = NULL;
3788 ha->gid_list_dma = 0;
3789
3790 ha->tgt.atio_ring = NULL;
3791 ha->tgt.atio_dma = 0;
3792 ha->tgt.tgt_vp_map = NULL;
3793 }
3794
3795 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3796 struct qla_hw_data *ha)
3797 {
3798 struct Scsi_Host *host;
3799 struct scsi_qla_host *vha = NULL;
3800
3801 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3802 if (host == NULL) {
3803 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3804 "Failed to allocate host from the scsi layer, aborting.\n");
3805 goto fail;
3806 }
3807
3808 /* Clear our data area */
3809 vha = shost_priv(host);
3810 memset(vha, 0, sizeof(scsi_qla_host_t));
3811
3812 vha->host = host;
3813 vha->host_no = host->host_no;
3814 vha->hw = ha;
3815
3816 INIT_LIST_HEAD(&vha->vp_fcports);
3817 INIT_LIST_HEAD(&vha->work_list);
3818 INIT_LIST_HEAD(&vha->list);
3819
3820 spin_lock_init(&vha->work_lock);
3821
3822 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3823 ql_dbg(ql_dbg_init, vha, 0x0041,
3824 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3825 vha->host, vha->hw, vha,
3826 dev_name(&(ha->pdev->dev)));
3827
3828 return vha;
3829
3830 fail:
3831 return vha;
3832 }
3833
3834 static struct qla_work_evt *
3835 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3836 {
3837 struct qla_work_evt *e;
3838 uint8_t bail;
3839
3840 QLA_VHA_MARK_BUSY(vha, bail);
3841 if (bail)
3842 return NULL;
3843
3844 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3845 if (!e) {
3846 QLA_VHA_MARK_NOT_BUSY(vha);
3847 return NULL;
3848 }
3849
3850 INIT_LIST_HEAD(&e->list);
3851 e->type = type;
3852 e->flags = QLA_EVT_FLAG_FREE;
3853 return e;
3854 }
3855
3856 static int
3857 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3858 {
3859 unsigned long flags;
3860
3861 spin_lock_irqsave(&vha->work_lock, flags);
3862 list_add_tail(&e->list, &vha->work_list);
3863 spin_unlock_irqrestore(&vha->work_lock, flags);
3864 qla2xxx_wake_dpc(vha);
3865
3866 return QLA_SUCCESS;
3867 }
3868
3869 int
3870 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3871 u32 data)
3872 {
3873 struct qla_work_evt *e;
3874
3875 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3876 if (!e)
3877 return QLA_FUNCTION_FAILED;
3878
3879 e->u.aen.code = code;
3880 e->u.aen.data = data;
3881 return qla2x00_post_work(vha, e);
3882 }
3883
3884 int
3885 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3886 {
3887 struct qla_work_evt *e;
3888
3889 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3890 if (!e)
3891 return QLA_FUNCTION_FAILED;
3892
3893 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3894 return qla2x00_post_work(vha, e);
3895 }
3896
3897 #define qla2x00_post_async_work(name, type) \
3898 int qla2x00_post_async_##name##_work( \
3899 struct scsi_qla_host *vha, \
3900 fc_port_t *fcport, uint16_t *data) \
3901 { \
3902 struct qla_work_evt *e; \
3903 \
3904 e = qla2x00_alloc_work(vha, type); \
3905 if (!e) \
3906 return QLA_FUNCTION_FAILED; \
3907 \
3908 e->u.logio.fcport = fcport; \
3909 if (data) { \
3910 e->u.logio.data[0] = data[0]; \
3911 e->u.logio.data[1] = data[1]; \
3912 } \
3913 return qla2x00_post_work(vha, e); \
3914 }
3915
3916 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3917 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3918 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3919 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3920 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3921 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3922
3923 int
3924 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3925 {
3926 struct qla_work_evt *e;
3927
3928 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3929 if (!e)
3930 return QLA_FUNCTION_FAILED;
3931
3932 e->u.uevent.code = code;
3933 return qla2x00_post_work(vha, e);
3934 }
3935
3936 static void
3937 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3938 {
3939 char event_string[40];
3940 char *envp[] = { event_string, NULL };
3941
3942 switch (code) {
3943 case QLA_UEVENT_CODE_FW_DUMP:
3944 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3945 vha->host_no);
3946 break;
3947 default:
3948 /* do nothing */
3949 break;
3950 }
3951 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3952 }
3953
3954 int
3955 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3956 uint32_t *data, int cnt)
3957 {
3958 struct qla_work_evt *e;
3959
3960 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3961 if (!e)
3962 return QLA_FUNCTION_FAILED;
3963
3964 e->u.aenfx.evtcode = evtcode;
3965 e->u.aenfx.count = cnt;
3966 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3967 return qla2x00_post_work(vha, e);
3968 }
3969
3970 void
3971 qla2x00_do_work(struct scsi_qla_host *vha)
3972 {
3973 struct qla_work_evt *e, *tmp;
3974 unsigned long flags;
3975 LIST_HEAD(work);
3976
3977 spin_lock_irqsave(&vha->work_lock, flags);
3978 list_splice_init(&vha->work_list, &work);
3979 spin_unlock_irqrestore(&vha->work_lock, flags);
3980
3981 list_for_each_entry_safe(e, tmp, &work, list) {
3982 list_del_init(&e->list);
3983
3984 switch (e->type) {
3985 case QLA_EVT_AEN:
3986 fc_host_post_event(vha->host, fc_get_event_number(),
3987 e->u.aen.code, e->u.aen.data);
3988 break;
3989 case QLA_EVT_IDC_ACK:
3990 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3991 break;
3992 case QLA_EVT_ASYNC_LOGIN:
3993 qla2x00_async_login(vha, e->u.logio.fcport,
3994 e->u.logio.data);
3995 break;
3996 case QLA_EVT_ASYNC_LOGIN_DONE:
3997 qla2x00_async_login_done(vha, e->u.logio.fcport,
3998 e->u.logio.data);
3999 break;
4000 case QLA_EVT_ASYNC_LOGOUT:
4001 qla2x00_async_logout(vha, e->u.logio.fcport);
4002 break;
4003 case QLA_EVT_ASYNC_LOGOUT_DONE:
4004 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4005 e->u.logio.data);
4006 break;
4007 case QLA_EVT_ASYNC_ADISC:
4008 qla2x00_async_adisc(vha, e->u.logio.fcport,
4009 e->u.logio.data);
4010 break;
4011 case QLA_EVT_ASYNC_ADISC_DONE:
4012 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4013 e->u.logio.data);
4014 break;
4015 case QLA_EVT_UEVENT:
4016 qla2x00_uevent_emit(vha, e->u.uevent.code);
4017 break;
4018 case QLA_EVT_AENFX:
4019 qlafx00_process_aen(vha, e);
4020 break;
4021 }
4022 if (e->flags & QLA_EVT_FLAG_FREE)
4023 kfree(e);
4024
4025 /* For each work completed decrement vha ref count */
4026 QLA_VHA_MARK_NOT_BUSY(vha);
4027 }
4028 }
4029
4030 /* Relogins all the fcports of a vport
4031 * Context: dpc thread
4032 */
4033 void qla2x00_relogin(struct scsi_qla_host *vha)
4034 {
4035 fc_port_t *fcport;
4036 int status;
4037 uint16_t next_loopid = 0;
4038 struct qla_hw_data *ha = vha->hw;
4039 uint16_t data[2];
4040
4041 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4042 /*
4043 * If the port is not ONLINE then try to login
4044 * to it if we haven't run out of retries.
4045 */
4046 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4047 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4048 fcport->login_retry--;
4049 if (fcport->flags & FCF_FABRIC_DEVICE) {
4050 if (fcport->flags & FCF_FCP2_DEVICE)
4051 ha->isp_ops->fabric_logout(vha,
4052 fcport->loop_id,
4053 fcport->d_id.b.domain,
4054 fcport->d_id.b.area,
4055 fcport->d_id.b.al_pa);
4056
4057 if (fcport->loop_id == FC_NO_LOOP_ID) {
4058 fcport->loop_id = next_loopid =
4059 ha->min_external_loopid;
4060 status = qla2x00_find_new_loop_id(
4061 vha, fcport);
4062 if (status != QLA_SUCCESS) {
4063 /* Ran out of IDs to use */
4064 break;
4065 }
4066 }
4067
4068 if (IS_ALOGIO_CAPABLE(ha)) {
4069 fcport->flags |= FCF_ASYNC_SENT;
4070 data[0] = 0;
4071 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4072 status = qla2x00_post_async_login_work(
4073 vha, fcport, data);
4074 if (status == QLA_SUCCESS)
4075 continue;
4076 /* Attempt a retry. */
4077 status = 1;
4078 } else {
4079 status = qla2x00_fabric_login(vha,
4080 fcport, &next_loopid);
4081 if (status == QLA_SUCCESS) {
4082 int status2;
4083 uint8_t opts;
4084
4085 opts = 0;
4086 if (fcport->flags &
4087 FCF_FCP2_DEVICE)
4088 opts |= BIT_1;
4089 status2 =
4090 qla2x00_get_port_database(
4091 vha, fcport, opts);
4092 if (status2 != QLA_SUCCESS)
4093 status = 1;
4094 }
4095 }
4096 } else
4097 status = qla2x00_local_device_login(vha,
4098 fcport);
4099
4100 if (status == QLA_SUCCESS) {
4101 fcport->old_loop_id = fcport->loop_id;
4102
4103 ql_dbg(ql_dbg_disc, vha, 0x2003,
4104 "Port login OK: logged in ID 0x%x.\n",
4105 fcport->loop_id);
4106
4107 qla2x00_update_fcport(vha, fcport);
4108
4109 } else if (status == 1) {
4110 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4111 /* retry the login again */
4112 ql_dbg(ql_dbg_disc, vha, 0x2007,
4113 "Retrying %d login again loop_id 0x%x.\n",
4114 fcport->login_retry, fcport->loop_id);
4115 } else {
4116 fcport->login_retry = 0;
4117 }
4118
4119 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4120 qla2x00_clear_loop_id(fcport);
4121 }
4122 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4123 break;
4124 }
4125 }
4126
4127 /* Schedule work on any of the dpc-workqueues */
4128 void
4129 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4130 {
4131 struct qla_hw_data *ha = base_vha->hw;
4132
4133 switch (work_code) {
4134 case MBA_IDC_AEN: /* 0x8200 */
4135 if (ha->dpc_lp_wq)
4136 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4137 break;
4138
4139 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4140 if (!ha->flags.nic_core_reset_hdlr_active) {
4141 if (ha->dpc_hp_wq)
4142 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4143 } else
4144 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4145 "NIC Core reset is already active. Skip "
4146 "scheduling it again.\n");
4147 break;
4148 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4149 if (ha->dpc_hp_wq)
4150 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4151 break;
4152 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4153 if (ha->dpc_hp_wq)
4154 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4155 break;
4156 default:
4157 ql_log(ql_log_warn, base_vha, 0xb05f,
4158 "Unknow work-code=0x%x.\n", work_code);
4159 }
4160
4161 return;
4162 }
4163
4164 /* Work: Perform NIC Core Unrecoverable state handling */
4165 void
4166 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4167 {
4168 struct qla_hw_data *ha =
4169 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4171 uint32_t dev_state = 0;
4172
4173 qla83xx_idc_lock(base_vha, 0);
4174 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4175 qla83xx_reset_ownership(base_vha);
4176 if (ha->flags.nic_core_reset_owner) {
4177 ha->flags.nic_core_reset_owner = 0;
4178 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4179 QLA8XXX_DEV_FAILED);
4180 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4181 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4182 }
4183 qla83xx_idc_unlock(base_vha, 0);
4184 }
4185
4186 /* Work: Execute IDC state handler */
4187 void
4188 qla83xx_idc_state_handler_work(struct work_struct *work)
4189 {
4190 struct qla_hw_data *ha =
4191 container_of(work, struct qla_hw_data, idc_state_handler);
4192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4193 uint32_t dev_state = 0;
4194
4195 qla83xx_idc_lock(base_vha, 0);
4196 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4197 if (dev_state == QLA8XXX_DEV_FAILED ||
4198 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4199 qla83xx_idc_state_handler(base_vha);
4200 qla83xx_idc_unlock(base_vha, 0);
4201 }
4202
4203 static int
4204 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4205 {
4206 int rval = QLA_SUCCESS;
4207 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4208 uint32_t heart_beat_counter1, heart_beat_counter2;
4209
4210 do {
4211 if (time_after(jiffies, heart_beat_wait)) {
4212 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4213 "Nic Core f/w is not alive.\n");
4214 rval = QLA_FUNCTION_FAILED;
4215 break;
4216 }
4217
4218 qla83xx_idc_lock(base_vha, 0);
4219 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4220 &heart_beat_counter1);
4221 qla83xx_idc_unlock(base_vha, 0);
4222 msleep(100);
4223 qla83xx_idc_lock(base_vha, 0);
4224 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4225 &heart_beat_counter2);
4226 qla83xx_idc_unlock(base_vha, 0);
4227 } while (heart_beat_counter1 == heart_beat_counter2);
4228
4229 return rval;
4230 }
4231
4232 /* Work: Perform NIC Core Reset handling */
4233 void
4234 qla83xx_nic_core_reset_work(struct work_struct *work)
4235 {
4236 struct qla_hw_data *ha =
4237 container_of(work, struct qla_hw_data, nic_core_reset);
4238 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4239 uint32_t dev_state = 0;
4240
4241 if (IS_QLA2031(ha)) {
4242 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4243 ql_log(ql_log_warn, base_vha, 0xb081,
4244 "Failed to dump mctp\n");
4245 return;
4246 }
4247
4248 if (!ha->flags.nic_core_reset_hdlr_active) {
4249 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4250 qla83xx_idc_lock(base_vha, 0);
4251 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4252 &dev_state);
4253 qla83xx_idc_unlock(base_vha, 0);
4254 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4255 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4256 "Nic Core f/w is alive.\n");
4257 return;
4258 }
4259 }
4260
4261 ha->flags.nic_core_reset_hdlr_active = 1;
4262 if (qla83xx_nic_core_reset(base_vha)) {
4263 /* NIC Core reset failed. */
4264 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4265 "NIC Core reset failed.\n");
4266 }
4267 ha->flags.nic_core_reset_hdlr_active = 0;
4268 }
4269 }
4270
4271 /* Work: Handle 8200 IDC aens */
4272 void
4273 qla83xx_service_idc_aen(struct work_struct *work)
4274 {
4275 struct qla_hw_data *ha =
4276 container_of(work, struct qla_hw_data, idc_aen);
4277 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4278 uint32_t dev_state, idc_control;
4279
4280 qla83xx_idc_lock(base_vha, 0);
4281 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4282 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4283 qla83xx_idc_unlock(base_vha, 0);
4284 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4285 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4286 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4287 "Application requested NIC Core Reset.\n");
4288 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4289 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4290 QLA_SUCCESS) {
4291 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4292 "Other protocol driver requested NIC Core Reset.\n");
4293 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4294 }
4295 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4296 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4297 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4298 }
4299 }
4300
4301 static void
4302 qla83xx_wait_logic(void)
4303 {
4304 int i;
4305
4306 /* Yield CPU */
4307 if (!in_interrupt()) {
4308 /*
4309 * Wait about 200ms before retrying again.
4310 * This controls the number of retries for single
4311 * lock operation.
4312 */
4313 msleep(100);
4314 schedule();
4315 } else {
4316 for (i = 0; i < 20; i++)
4317 cpu_relax(); /* This a nop instr on i386 */
4318 }
4319 }
4320
4321 static int
4322 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4323 {
4324 int rval;
4325 uint32_t data;
4326 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4327 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4328 struct qla_hw_data *ha = base_vha->hw;
4329 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4330 "Trying force recovery of the IDC lock.\n");
4331
4332 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4333 if (rval)
4334 return rval;
4335
4336 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4337 return QLA_SUCCESS;
4338 } else {
4339 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4340 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4341 data);
4342 if (rval)
4343 return rval;
4344
4345 msleep(200);
4346
4347 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4348 &data);
4349 if (rval)
4350 return rval;
4351
4352 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4353 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4354 ~(idc_lck_rcvry_stage_mask));
4355 rval = qla83xx_wr_reg(base_vha,
4356 QLA83XX_IDC_LOCK_RECOVERY, data);
4357 if (rval)
4358 return rval;
4359
4360 /* Forcefully perform IDC UnLock */
4361 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4362 &data);
4363 if (rval)
4364 return rval;
4365 /* Clear lock-id by setting 0xff */
4366 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4367 0xff);
4368 if (rval)
4369 return rval;
4370 /* Clear lock-recovery by setting 0x0 */
4371 rval = qla83xx_wr_reg(base_vha,
4372 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4373 if (rval)
4374 return rval;
4375 } else
4376 return QLA_SUCCESS;
4377 }
4378
4379 return rval;
4380 }
4381
4382 static int
4383 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4384 {
4385 int rval = QLA_SUCCESS;
4386 uint32_t o_drv_lockid, n_drv_lockid;
4387 unsigned long lock_recovery_timeout;
4388
4389 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4390 retry_lockid:
4391 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4392 if (rval)
4393 goto exit;
4394
4395 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4396 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4397 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4398 return QLA_SUCCESS;
4399 else
4400 return QLA_FUNCTION_FAILED;
4401 }
4402
4403 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4404 if (rval)
4405 goto exit;
4406
4407 if (o_drv_lockid == n_drv_lockid) {
4408 qla83xx_wait_logic();
4409 goto retry_lockid;
4410 } else
4411 return QLA_SUCCESS;
4412
4413 exit:
4414 return rval;
4415 }
4416
4417 void
4418 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4419 {
4420 uint16_t options = (requester_id << 15) | BIT_6;
4421 uint32_t data;
4422 uint32_t lock_owner;
4423 struct qla_hw_data *ha = base_vha->hw;
4424
4425 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4426 retry_lock:
4427 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4428 == QLA_SUCCESS) {
4429 if (data) {
4430 /* Setting lock-id to our function-number */
4431 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4432 ha->portnum);
4433 } else {
4434 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4435 &lock_owner);
4436 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4437 "Failed to acquire IDC lock, acquired by %d, "
4438 "retrying...\n", lock_owner);
4439
4440 /* Retry/Perform IDC-Lock recovery */
4441 if (qla83xx_idc_lock_recovery(base_vha)
4442 == QLA_SUCCESS) {
4443 qla83xx_wait_logic();
4444 goto retry_lock;
4445 } else
4446 ql_log(ql_log_warn, base_vha, 0xb075,
4447 "IDC Lock recovery FAILED.\n");
4448 }
4449
4450 }
4451
4452 return;
4453
4454 /* XXX: IDC-lock implementation using access-control mbx */
4455 retry_lock2:
4456 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4457 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4458 "Failed to acquire IDC lock. retrying...\n");
4459 /* Retry/Perform IDC-Lock recovery */
4460 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4461 qla83xx_wait_logic();
4462 goto retry_lock2;
4463 } else
4464 ql_log(ql_log_warn, base_vha, 0xb076,
4465 "IDC Lock recovery FAILED.\n");
4466 }
4467
4468 return;
4469 }
4470
4471 void
4472 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4473 {
4474 uint16_t options = (requester_id << 15) | BIT_7, retry;
4475 uint32_t data;
4476 struct qla_hw_data *ha = base_vha->hw;
4477
4478 /* IDC-unlock implementation using driver-unlock/lock-id
4479 * remote registers
4480 */
4481 retry = 0;
4482 retry_unlock:
4483 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4484 == QLA_SUCCESS) {
4485 if (data == ha->portnum) {
4486 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4487 /* Clearing lock-id by setting 0xff */
4488 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4489 } else if (retry < 10) {
4490 /* SV: XXX: IDC unlock retrying needed here? */
4491
4492 /* Retry for IDC-unlock */
4493 qla83xx_wait_logic();
4494 retry++;
4495 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4496 "Failed to release IDC lock, retyring=%d\n", retry);
4497 goto retry_unlock;
4498 }
4499 } else if (retry < 10) {
4500 /* Retry for IDC-unlock */
4501 qla83xx_wait_logic();
4502 retry++;
4503 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4504 "Failed to read drv-lockid, retyring=%d\n", retry);
4505 goto retry_unlock;
4506 }
4507
4508 return;
4509
4510 /* XXX: IDC-unlock implementation using access-control mbx */
4511 retry = 0;
4512 retry_unlock2:
4513 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4514 if (retry < 10) {
4515 /* Retry for IDC-unlock */
4516 qla83xx_wait_logic();
4517 retry++;
4518 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4519 "Failed to release IDC lock, retyring=%d\n", retry);
4520 goto retry_unlock2;
4521 }
4522 }
4523
4524 return;
4525 }
4526
4527 int
4528 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4529 {
4530 int rval = QLA_SUCCESS;
4531 struct qla_hw_data *ha = vha->hw;
4532 uint32_t drv_presence;
4533
4534 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4535 if (rval == QLA_SUCCESS) {
4536 drv_presence |= (1 << ha->portnum);
4537 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4538 drv_presence);
4539 }
4540
4541 return rval;
4542 }
4543
4544 int
4545 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4546 {
4547 int rval = QLA_SUCCESS;
4548
4549 qla83xx_idc_lock(vha, 0);
4550 rval = __qla83xx_set_drv_presence(vha);
4551 qla83xx_idc_unlock(vha, 0);
4552
4553 return rval;
4554 }
4555
4556 int
4557 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4558 {
4559 int rval = QLA_SUCCESS;
4560 struct qla_hw_data *ha = vha->hw;
4561 uint32_t drv_presence;
4562
4563 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4564 if (rval == QLA_SUCCESS) {
4565 drv_presence &= ~(1 << ha->portnum);
4566 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4567 drv_presence);
4568 }
4569
4570 return rval;
4571 }
4572
4573 int
4574 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4575 {
4576 int rval = QLA_SUCCESS;
4577
4578 qla83xx_idc_lock(vha, 0);
4579 rval = __qla83xx_clear_drv_presence(vha);
4580 qla83xx_idc_unlock(vha, 0);
4581
4582 return rval;
4583 }
4584
4585 static void
4586 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4587 {
4588 struct qla_hw_data *ha = vha->hw;
4589 uint32_t drv_ack, drv_presence;
4590 unsigned long ack_timeout;
4591
4592 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4593 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4594 while (1) {
4595 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4596 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4597 if ((drv_ack & drv_presence) == drv_presence)
4598 break;
4599
4600 if (time_after_eq(jiffies, ack_timeout)) {
4601 ql_log(ql_log_warn, vha, 0xb067,
4602 "RESET ACK TIMEOUT! drv_presence=0x%x "
4603 "drv_ack=0x%x\n", drv_presence, drv_ack);
4604 /*
4605 * The function(s) which did not ack in time are forced
4606 * to withdraw any further participation in the IDC
4607 * reset.
4608 */
4609 if (drv_ack != drv_presence)
4610 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4611 drv_ack);
4612 break;
4613 }
4614
4615 qla83xx_idc_unlock(vha, 0);
4616 msleep(1000);
4617 qla83xx_idc_lock(vha, 0);
4618 }
4619
4620 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4621 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4622 }
4623
4624 static int
4625 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4626 {
4627 int rval = QLA_SUCCESS;
4628 uint32_t idc_control;
4629
4630 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4631 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4632
4633 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4634 __qla83xx_get_idc_control(vha, &idc_control);
4635 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4636 __qla83xx_set_idc_control(vha, 0);
4637
4638 qla83xx_idc_unlock(vha, 0);
4639 rval = qla83xx_restart_nic_firmware(vha);
4640 qla83xx_idc_lock(vha, 0);
4641
4642 if (rval != QLA_SUCCESS) {
4643 ql_log(ql_log_fatal, vha, 0xb06a,
4644 "Failed to restart NIC f/w.\n");
4645 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4646 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4647 } else {
4648 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4649 "Success in restarting nic f/w.\n");
4650 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4651 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4652 }
4653
4654 return rval;
4655 }
4656
4657 /* Assumes idc_lock always held on entry */
4658 int
4659 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4660 {
4661 struct qla_hw_data *ha = base_vha->hw;
4662 int rval = QLA_SUCCESS;
4663 unsigned long dev_init_timeout;
4664 uint32_t dev_state;
4665
4666 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4667 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4668
4669 while (1) {
4670
4671 if (time_after_eq(jiffies, dev_init_timeout)) {
4672 ql_log(ql_log_warn, base_vha, 0xb06e,
4673 "Initialization TIMEOUT!\n");
4674 /* Init timeout. Disable further NIC Core
4675 * communication.
4676 */
4677 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4678 QLA8XXX_DEV_FAILED);
4679 ql_log(ql_log_info, base_vha, 0xb06f,
4680 "HW State: FAILED.\n");
4681 }
4682
4683 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4684 switch (dev_state) {
4685 case QLA8XXX_DEV_READY:
4686 if (ha->flags.nic_core_reset_owner)
4687 qla83xx_idc_audit(base_vha,
4688 IDC_AUDIT_COMPLETION);
4689 ha->flags.nic_core_reset_owner = 0;
4690 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4691 "Reset_owner reset by 0x%x.\n",
4692 ha->portnum);
4693 goto exit;
4694 case QLA8XXX_DEV_COLD:
4695 if (ha->flags.nic_core_reset_owner)
4696 rval = qla83xx_device_bootstrap(base_vha);
4697 else {
4698 /* Wait for AEN to change device-state */
4699 qla83xx_idc_unlock(base_vha, 0);
4700 msleep(1000);
4701 qla83xx_idc_lock(base_vha, 0);
4702 }
4703 break;
4704 case QLA8XXX_DEV_INITIALIZING:
4705 /* Wait for AEN to change device-state */
4706 qla83xx_idc_unlock(base_vha, 0);
4707 msleep(1000);
4708 qla83xx_idc_lock(base_vha, 0);
4709 break;
4710 case QLA8XXX_DEV_NEED_RESET:
4711 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4712 qla83xx_need_reset_handler(base_vha);
4713 else {
4714 /* Wait for AEN to change device-state */
4715 qla83xx_idc_unlock(base_vha, 0);
4716 msleep(1000);
4717 qla83xx_idc_lock(base_vha, 0);
4718 }
4719 /* reset timeout value after need reset handler */
4720 dev_init_timeout = jiffies +
4721 (ha->fcoe_dev_init_timeout * HZ);
4722 break;
4723 case QLA8XXX_DEV_NEED_QUIESCENT:
4724 /* XXX: DEBUG for now */
4725 qla83xx_idc_unlock(base_vha, 0);
4726 msleep(1000);
4727 qla83xx_idc_lock(base_vha, 0);
4728 break;
4729 case QLA8XXX_DEV_QUIESCENT:
4730 /* XXX: DEBUG for now */
4731 if (ha->flags.quiesce_owner)
4732 goto exit;
4733
4734 qla83xx_idc_unlock(base_vha, 0);
4735 msleep(1000);
4736 qla83xx_idc_lock(base_vha, 0);
4737 dev_init_timeout = jiffies +
4738 (ha->fcoe_dev_init_timeout * HZ);
4739 break;
4740 case QLA8XXX_DEV_FAILED:
4741 if (ha->flags.nic_core_reset_owner)
4742 qla83xx_idc_audit(base_vha,
4743 IDC_AUDIT_COMPLETION);
4744 ha->flags.nic_core_reset_owner = 0;
4745 __qla83xx_clear_drv_presence(base_vha);
4746 qla83xx_idc_unlock(base_vha, 0);
4747 qla8xxx_dev_failed_handler(base_vha);
4748 rval = QLA_FUNCTION_FAILED;
4749 qla83xx_idc_lock(base_vha, 0);
4750 goto exit;
4751 case QLA8XXX_BAD_VALUE:
4752 qla83xx_idc_unlock(base_vha, 0);
4753 msleep(1000);
4754 qla83xx_idc_lock(base_vha, 0);
4755 break;
4756 default:
4757 ql_log(ql_log_warn, base_vha, 0xb071,
4758 "Unknow Device State: %x.\n", dev_state);
4759 qla83xx_idc_unlock(base_vha, 0);
4760 qla8xxx_dev_failed_handler(base_vha);
4761 rval = QLA_FUNCTION_FAILED;
4762 qla83xx_idc_lock(base_vha, 0);
4763 goto exit;
4764 }
4765 }
4766
4767 exit:
4768 return rval;
4769 }
4770
4771 void
4772 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4773 {
4774 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4775 board_disable);
4776 struct pci_dev *pdev = ha->pdev;
4777 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4778
4779 ql_log(ql_log_warn, base_vha, 0x015b,
4780 "Disabling adapter.\n");
4781
4782 set_bit(UNLOADING, &base_vha->dpc_flags);
4783
4784 qla2x00_delete_all_vps(ha, base_vha);
4785
4786 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4787
4788 qla2x00_dfs_remove(base_vha);
4789
4790 qla84xx_put_chip(base_vha);
4791
4792 if (base_vha->timer_active)
4793 qla2x00_stop_timer(base_vha);
4794
4795 base_vha->flags.online = 0;
4796
4797 qla2x00_destroy_deferred_work(ha);
4798
4799 /*
4800 * Do not try to stop beacon blink as it will issue a mailbox
4801 * command.
4802 */
4803 qla2x00_free_sysfs_attr(base_vha, false);
4804
4805 fc_remove_host(base_vha->host);
4806
4807 scsi_remove_host(base_vha->host);
4808
4809 base_vha->flags.init_done = 0;
4810 qla25xx_delete_queues(base_vha);
4811 qla2x00_free_irqs(base_vha);
4812 qla2x00_free_fcports(base_vha);
4813 qla2x00_mem_free(ha);
4814 qla82xx_md_free(base_vha);
4815 qla2x00_free_queues(ha);
4816
4817 qla2x00_unmap_iobases(ha);
4818
4819 pci_release_selected_regions(ha->pdev, ha->bars);
4820 pci_disable_pcie_error_reporting(pdev);
4821 pci_disable_device(pdev);
4822
4823 /*
4824 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4825 */
4826 }
4827
4828 /**************************************************************************
4829 * qla2x00_do_dpc
4830 * This kernel thread is a task that is schedule by the interrupt handler
4831 * to perform the background processing for interrupts.
4832 *
4833 * Notes:
4834 * This task always run in the context of a kernel thread. It
4835 * is kick-off by the driver's detect code and starts up
4836 * up one per adapter. It immediately goes to sleep and waits for
4837 * some fibre event. When either the interrupt handler or
4838 * the timer routine detects a event it will one of the task
4839 * bits then wake us up.
4840 **************************************************************************/
4841 static int
4842 qla2x00_do_dpc(void *data)
4843 {
4844 int rval;
4845 scsi_qla_host_t *base_vha;
4846 struct qla_hw_data *ha;
4847
4848 ha = (struct qla_hw_data *)data;
4849 base_vha = pci_get_drvdata(ha->pdev);
4850
4851 set_user_nice(current, MIN_NICE);
4852
4853 set_current_state(TASK_INTERRUPTIBLE);
4854 while (!kthread_should_stop()) {
4855 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4856 "DPC handler sleeping.\n");
4857
4858 schedule();
4859
4860 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4861 goto end_loop;
4862
4863 if (ha->flags.eeh_busy) {
4864 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4865 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4866 goto end_loop;
4867 }
4868
4869 ha->dpc_active = 1;
4870
4871 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4872 "DPC handler waking up, dpc_flags=0x%lx.\n",
4873 base_vha->dpc_flags);
4874
4875 qla2x00_do_work(base_vha);
4876
4877 if (IS_P3P_TYPE(ha)) {
4878 if (IS_QLA8044(ha)) {
4879 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4880 &base_vha->dpc_flags)) {
4881 qla8044_idc_lock(ha);
4882 qla8044_wr_direct(base_vha,
4883 QLA8044_CRB_DEV_STATE_INDEX,
4884 QLA8XXX_DEV_FAILED);
4885 qla8044_idc_unlock(ha);
4886 ql_log(ql_log_info, base_vha, 0x4004,
4887 "HW State: FAILED.\n");
4888 qla8044_device_state_handler(base_vha);
4889 continue;
4890 }
4891
4892 } else {
4893 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4894 &base_vha->dpc_flags)) {
4895 qla82xx_idc_lock(ha);
4896 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4897 QLA8XXX_DEV_FAILED);
4898 qla82xx_idc_unlock(ha);
4899 ql_log(ql_log_info, base_vha, 0x0151,
4900 "HW State: FAILED.\n");
4901 qla82xx_device_state_handler(base_vha);
4902 continue;
4903 }
4904 }
4905
4906 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4907 &base_vha->dpc_flags)) {
4908
4909 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4910 "FCoE context reset scheduled.\n");
4911 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4912 &base_vha->dpc_flags))) {
4913 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4914 /* FCoE-ctx reset failed.
4915 * Escalate to chip-reset
4916 */
4917 set_bit(ISP_ABORT_NEEDED,
4918 &base_vha->dpc_flags);
4919 }
4920 clear_bit(ABORT_ISP_ACTIVE,
4921 &base_vha->dpc_flags);
4922 }
4923
4924 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4925 "FCoE context reset end.\n");
4926 }
4927 } else if (IS_QLAFX00(ha)) {
4928 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4929 &base_vha->dpc_flags)) {
4930 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4931 "Firmware Reset Recovery\n");
4932 if (qlafx00_reset_initialize(base_vha)) {
4933 /* Failed. Abort isp later. */
4934 if (!test_bit(UNLOADING,
4935 &base_vha->dpc_flags)) {
4936 set_bit(ISP_UNRECOVERABLE,
4937 &base_vha->dpc_flags);
4938 ql_dbg(ql_dbg_dpc, base_vha,
4939 0x4021,
4940 "Reset Recovery Failed\n");
4941 }
4942 }
4943 }
4944
4945 if (test_and_clear_bit(FX00_TARGET_SCAN,
4946 &base_vha->dpc_flags)) {
4947 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4948 "ISPFx00 Target Scan scheduled\n");
4949 if (qlafx00_rescan_isp(base_vha)) {
4950 if (!test_bit(UNLOADING,
4951 &base_vha->dpc_flags))
4952 set_bit(ISP_UNRECOVERABLE,
4953 &base_vha->dpc_flags);
4954 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4955 "ISPFx00 Target Scan Failed\n");
4956 }
4957 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4958 "ISPFx00 Target Scan End\n");
4959 }
4960 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4961 &base_vha->dpc_flags)) {
4962 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4963 "ISPFx00 Host Info resend scheduled\n");
4964 qlafx00_fx_disc(base_vha,
4965 &base_vha->hw->mr.fcport,
4966 FXDISC_REG_HOST_INFO);
4967 }
4968 }
4969
4970 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4971 &base_vha->dpc_flags)) {
4972
4973 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4974 "ISP abort scheduled.\n");
4975 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4976 &base_vha->dpc_flags))) {
4977
4978 if (ha->isp_ops->abort_isp(base_vha)) {
4979 /* failed. retry later */
4980 set_bit(ISP_ABORT_NEEDED,
4981 &base_vha->dpc_flags);
4982 }
4983 clear_bit(ABORT_ISP_ACTIVE,
4984 &base_vha->dpc_flags);
4985 }
4986
4987 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4988 "ISP abort end.\n");
4989 }
4990
4991 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4992 &base_vha->dpc_flags)) {
4993 qla2x00_update_fcports(base_vha);
4994 }
4995
4996 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4997 int ret;
4998 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4999 if (ret != QLA_SUCCESS)
5000 ql_log(ql_log_warn, base_vha, 0x121,
5001 "Failed to enable receiving of RSCN "
5002 "requests: 0x%x.\n", ret);
5003 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5004 }
5005
5006 if (IS_QLAFX00(ha))
5007 goto loop_resync_check;
5008
5009 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5010 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5011 "Quiescence mode scheduled.\n");
5012 if (IS_P3P_TYPE(ha)) {
5013 if (IS_QLA82XX(ha))
5014 qla82xx_device_state_handler(base_vha);
5015 if (IS_QLA8044(ha))
5016 qla8044_device_state_handler(base_vha);
5017 clear_bit(ISP_QUIESCE_NEEDED,
5018 &base_vha->dpc_flags);
5019 if (!ha->flags.quiesce_owner) {
5020 qla2x00_perform_loop_resync(base_vha);
5021 if (IS_QLA82XX(ha)) {
5022 qla82xx_idc_lock(ha);
5023 qla82xx_clear_qsnt_ready(
5024 base_vha);
5025 qla82xx_idc_unlock(ha);
5026 } else if (IS_QLA8044(ha)) {
5027 qla8044_idc_lock(ha);
5028 qla8044_clear_qsnt_ready(
5029 base_vha);
5030 qla8044_idc_unlock(ha);
5031 }
5032 }
5033 } else {
5034 clear_bit(ISP_QUIESCE_NEEDED,
5035 &base_vha->dpc_flags);
5036 qla2x00_quiesce_io(base_vha);
5037 }
5038 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5039 "Quiescence mode end.\n");
5040 }
5041
5042 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5043 &base_vha->dpc_flags) &&
5044 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5045
5046 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5047 "Reset marker scheduled.\n");
5048 qla2x00_rst_aen(base_vha);
5049 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5050 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5051 "Reset marker end.\n");
5052 }
5053
5054 /* Retry each device up to login retry count */
5055 if ((test_and_clear_bit(RELOGIN_NEEDED,
5056 &base_vha->dpc_flags)) &&
5057 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5058 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5059
5060 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5061 "Relogin scheduled.\n");
5062 qla2x00_relogin(base_vha);
5063 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5064 "Relogin end.\n");
5065 }
5066 loop_resync_check:
5067 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5068 &base_vha->dpc_flags)) {
5069
5070 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5071 "Loop resync scheduled.\n");
5072
5073 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5074 &base_vha->dpc_flags))) {
5075
5076 rval = qla2x00_loop_resync(base_vha);
5077
5078 clear_bit(LOOP_RESYNC_ACTIVE,
5079 &base_vha->dpc_flags);
5080 }
5081
5082 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5083 "Loop resync end.\n");
5084 }
5085
5086 if (IS_QLAFX00(ha))
5087 goto intr_on_check;
5088
5089 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5090 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5091 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5092 qla2xxx_flash_npiv_conf(base_vha);
5093 }
5094
5095 intr_on_check:
5096 if (!ha->interrupts_on)
5097 ha->isp_ops->enable_intrs(ha);
5098
5099 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5100 &base_vha->dpc_flags)) {
5101 if (ha->beacon_blink_led == 1)
5102 ha->isp_ops->beacon_blink(base_vha);
5103 }
5104
5105 if (!IS_QLAFX00(ha))
5106 qla2x00_do_dpc_all_vps(base_vha);
5107
5108 ha->dpc_active = 0;
5109 end_loop:
5110 set_current_state(TASK_INTERRUPTIBLE);
5111 } /* End of while(1) */
5112 __set_current_state(TASK_RUNNING);
5113
5114 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5115 "DPC handler exiting.\n");
5116
5117 /*
5118 * Make sure that nobody tries to wake us up again.
5119 */
5120 ha->dpc_active = 0;
5121
5122 /* Cleanup any residual CTX SRBs. */
5123 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5124
5125 return 0;
5126 }
5127
5128 void
5129 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5130 {
5131 struct qla_hw_data *ha = vha->hw;
5132 struct task_struct *t = ha->dpc_thread;
5133
5134 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5135 wake_up_process(t);
5136 }
5137
5138 /*
5139 * qla2x00_rst_aen
5140 * Processes asynchronous reset.
5141 *
5142 * Input:
5143 * ha = adapter block pointer.
5144 */
5145 static void
5146 qla2x00_rst_aen(scsi_qla_host_t *vha)
5147 {
5148 if (vha->flags.online && !vha->flags.reset_active &&
5149 !atomic_read(&vha->loop_down_timer) &&
5150 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5151 do {
5152 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5153
5154 /*
5155 * Issue marker command only when we are going to start
5156 * the I/O.
5157 */
5158 vha->marker_needed = 1;
5159 } while (!atomic_read(&vha->loop_down_timer) &&
5160 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5161 }
5162 }
5163
5164 /**************************************************************************
5165 * qla2x00_timer
5166 *
5167 * Description:
5168 * One second timer
5169 *
5170 * Context: Interrupt
5171 ***************************************************************************/
5172 void
5173 qla2x00_timer(scsi_qla_host_t *vha)
5174 {
5175 unsigned long cpu_flags = 0;
5176 int start_dpc = 0;
5177 int index;
5178 srb_t *sp;
5179 uint16_t w;
5180 struct qla_hw_data *ha = vha->hw;
5181 struct req_que *req;
5182
5183 if (ha->flags.eeh_busy) {
5184 ql_dbg(ql_dbg_timer, vha, 0x6000,
5185 "EEH = %d, restarting timer.\n",
5186 ha->flags.eeh_busy);
5187 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5188 return;
5189 }
5190
5191 /*
5192 * Hardware read to raise pending EEH errors during mailbox waits. If
5193 * the read returns -1 then disable the board.
5194 */
5195 if (!pci_channel_offline(ha->pdev)) {
5196 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5197 qla2x00_check_reg16_for_disconnect(vha, w);
5198 }
5199
5200 /* Make sure qla82xx_watchdog is run only for physical port */
5201 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5202 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5203 start_dpc++;
5204 if (IS_QLA82XX(ha))
5205 qla82xx_watchdog(vha);
5206 else if (IS_QLA8044(ha))
5207 qla8044_watchdog(vha);
5208 }
5209
5210 if (!vha->vp_idx && IS_QLAFX00(ha))
5211 qlafx00_timer_routine(vha);
5212
5213 /* Loop down handler. */
5214 if (atomic_read(&vha->loop_down_timer) > 0 &&
5215 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5216 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5217 && vha->flags.online) {
5218
5219 if (atomic_read(&vha->loop_down_timer) ==
5220 vha->loop_down_abort_time) {
5221
5222 ql_log(ql_log_info, vha, 0x6008,
5223 "Loop down - aborting the queues before time expires.\n");
5224
5225 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5226 atomic_set(&vha->loop_state, LOOP_DEAD);
5227
5228 /*
5229 * Schedule an ISP abort to return any FCP2-device
5230 * commands.
5231 */
5232 /* NPIV - scan physical port only */
5233 if (!vha->vp_idx) {
5234 spin_lock_irqsave(&ha->hardware_lock,
5235 cpu_flags);
5236 req = ha->req_q_map[0];
5237 for (index = 1;
5238 index < req->num_outstanding_cmds;
5239 index++) {
5240 fc_port_t *sfcp;
5241
5242 sp = req->outstanding_cmds[index];
5243 if (!sp)
5244 continue;
5245 if (sp->type != SRB_SCSI_CMD)
5246 continue;
5247 sfcp = sp->fcport;
5248 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5249 continue;
5250
5251 if (IS_QLA82XX(ha))
5252 set_bit(FCOE_CTX_RESET_NEEDED,
5253 &vha->dpc_flags);
5254 else
5255 set_bit(ISP_ABORT_NEEDED,
5256 &vha->dpc_flags);
5257 break;
5258 }
5259 spin_unlock_irqrestore(&ha->hardware_lock,
5260 cpu_flags);
5261 }
5262 start_dpc++;
5263 }
5264
5265 /* if the loop has been down for 4 minutes, reinit adapter */
5266 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5267 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5268 ql_log(ql_log_warn, vha, 0x6009,
5269 "Loop down - aborting ISP.\n");
5270
5271 if (IS_QLA82XX(ha))
5272 set_bit(FCOE_CTX_RESET_NEEDED,
5273 &vha->dpc_flags);
5274 else
5275 set_bit(ISP_ABORT_NEEDED,
5276 &vha->dpc_flags);
5277 }
5278 }
5279 ql_dbg(ql_dbg_timer, vha, 0x600a,
5280 "Loop down - seconds remaining %d.\n",
5281 atomic_read(&vha->loop_down_timer));
5282 }
5283 /* Check if beacon LED needs to be blinked for physical host only */
5284 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5285 /* There is no beacon_blink function for ISP82xx */
5286 if (!IS_P3P_TYPE(ha)) {
5287 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5288 start_dpc++;
5289 }
5290 }
5291
5292 /* Process any deferred work. */
5293 if (!list_empty(&vha->work_list))
5294 start_dpc++;
5295
5296 /* Schedule the DPC routine if needed */
5297 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5298 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5299 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5300 start_dpc ||
5301 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5302 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5303 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5304 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5305 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5306 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5307 ql_dbg(ql_dbg_timer, vha, 0x600b,
5308 "isp_abort_needed=%d loop_resync_needed=%d "
5309 "fcport_update_needed=%d start_dpc=%d "
5310 "reset_marker_needed=%d",
5311 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5312 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5313 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5314 start_dpc,
5315 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5316 ql_dbg(ql_dbg_timer, vha, 0x600c,
5317 "beacon_blink_needed=%d isp_unrecoverable=%d "
5318 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5319 "relogin_needed=%d.\n",
5320 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5321 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5322 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5323 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5324 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5325 qla2xxx_wake_dpc(vha);
5326 }
5327
5328 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5329 }
5330
5331 /* Firmware interface routines. */
5332
5333 #define FW_BLOBS 11
5334 #define FW_ISP21XX 0
5335 #define FW_ISP22XX 1
5336 #define FW_ISP2300 2
5337 #define FW_ISP2322 3
5338 #define FW_ISP24XX 4
5339 #define FW_ISP25XX 5
5340 #define FW_ISP81XX 6
5341 #define FW_ISP82XX 7
5342 #define FW_ISP2031 8
5343 #define FW_ISP8031 9
5344 #define FW_ISP27XX 10
5345
5346 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5347 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5348 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5349 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5350 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5351 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5352 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5353 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5354 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5355 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5356 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5357
5358
5359 static DEFINE_MUTEX(qla_fw_lock);
5360
5361 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5362 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5363 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5364 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5365 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5366 { .name = FW_FILE_ISP24XX, },
5367 { .name = FW_FILE_ISP25XX, },
5368 { .name = FW_FILE_ISP81XX, },
5369 { .name = FW_FILE_ISP82XX, },
5370 { .name = FW_FILE_ISP2031, },
5371 { .name = FW_FILE_ISP8031, },
5372 { .name = FW_FILE_ISP27XX, },
5373 };
5374
5375 struct fw_blob *
5376 qla2x00_request_firmware(scsi_qla_host_t *vha)
5377 {
5378 struct qla_hw_data *ha = vha->hw;
5379 struct fw_blob *blob;
5380
5381 if (IS_QLA2100(ha)) {
5382 blob = &qla_fw_blobs[FW_ISP21XX];
5383 } else if (IS_QLA2200(ha)) {
5384 blob = &qla_fw_blobs[FW_ISP22XX];
5385 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5386 blob = &qla_fw_blobs[FW_ISP2300];
5387 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5388 blob = &qla_fw_blobs[FW_ISP2322];
5389 } else if (IS_QLA24XX_TYPE(ha)) {
5390 blob = &qla_fw_blobs[FW_ISP24XX];
5391 } else if (IS_QLA25XX(ha)) {
5392 blob = &qla_fw_blobs[FW_ISP25XX];
5393 } else if (IS_QLA81XX(ha)) {
5394 blob = &qla_fw_blobs[FW_ISP81XX];
5395 } else if (IS_QLA82XX(ha)) {
5396 blob = &qla_fw_blobs[FW_ISP82XX];
5397 } else if (IS_QLA2031(ha)) {
5398 blob = &qla_fw_blobs[FW_ISP2031];
5399 } else if (IS_QLA8031(ha)) {
5400 blob = &qla_fw_blobs[FW_ISP8031];
5401 } else if (IS_QLA27XX(ha)) {
5402 blob = &qla_fw_blobs[FW_ISP27XX];
5403 } else {
5404 return NULL;
5405 }
5406
5407 mutex_lock(&qla_fw_lock);
5408 if (blob->fw)
5409 goto out;
5410
5411 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5412 ql_log(ql_log_warn, vha, 0x0063,
5413 "Failed to load firmware image (%s).\n", blob->name);
5414 blob->fw = NULL;
5415 blob = NULL;
5416 goto out;
5417 }
5418
5419 out:
5420 mutex_unlock(&qla_fw_lock);
5421 return blob;
5422 }
5423
5424 static void
5425 qla2x00_release_firmware(void)
5426 {
5427 int idx;
5428
5429 mutex_lock(&qla_fw_lock);
5430 for (idx = 0; idx < FW_BLOBS; idx++)
5431 release_firmware(qla_fw_blobs[idx].fw);
5432 mutex_unlock(&qla_fw_lock);
5433 }
5434
5435 static pci_ers_result_t
5436 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5437 {
5438 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5439 struct qla_hw_data *ha = vha->hw;
5440
5441 ql_dbg(ql_dbg_aer, vha, 0x9000,
5442 "PCI error detected, state %x.\n", state);
5443
5444 switch (state) {
5445 case pci_channel_io_normal:
5446 ha->flags.eeh_busy = 0;
5447 return PCI_ERS_RESULT_CAN_RECOVER;
5448 case pci_channel_io_frozen:
5449 ha->flags.eeh_busy = 1;
5450 /* For ISP82XX complete any pending mailbox cmd */
5451 if (IS_QLA82XX(ha)) {
5452 ha->flags.isp82xx_fw_hung = 1;
5453 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5454 qla82xx_clear_pending_mbx(vha);
5455 }
5456 qla2x00_free_irqs(vha);
5457 pci_disable_device(pdev);
5458 /* Return back all IOs */
5459 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5460 return PCI_ERS_RESULT_NEED_RESET;
5461 case pci_channel_io_perm_failure:
5462 ha->flags.pci_channel_io_perm_failure = 1;
5463 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5464 return PCI_ERS_RESULT_DISCONNECT;
5465 }
5466 return PCI_ERS_RESULT_NEED_RESET;
5467 }
5468
5469 static pci_ers_result_t
5470 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5471 {
5472 int risc_paused = 0;
5473 uint32_t stat;
5474 unsigned long flags;
5475 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5476 struct qla_hw_data *ha = base_vha->hw;
5477 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5478 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5479
5480 if (IS_QLA82XX(ha))
5481 return PCI_ERS_RESULT_RECOVERED;
5482
5483 spin_lock_irqsave(&ha->hardware_lock, flags);
5484 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5485 stat = RD_REG_DWORD(&reg->hccr);
5486 if (stat & HCCR_RISC_PAUSE)
5487 risc_paused = 1;
5488 } else if (IS_QLA23XX(ha)) {
5489 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5490 if (stat & HSR_RISC_PAUSED)
5491 risc_paused = 1;
5492 } else if (IS_FWI2_CAPABLE(ha)) {
5493 stat = RD_REG_DWORD(&reg24->host_status);
5494 if (stat & HSRX_RISC_PAUSED)
5495 risc_paused = 1;
5496 }
5497 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5498
5499 if (risc_paused) {
5500 ql_log(ql_log_info, base_vha, 0x9003,
5501 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5502 ha->isp_ops->fw_dump(base_vha, 0);
5503
5504 return PCI_ERS_RESULT_NEED_RESET;
5505 } else
5506 return PCI_ERS_RESULT_RECOVERED;
5507 }
5508
5509 static uint32_t
5510 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5511 {
5512 uint32_t rval = QLA_FUNCTION_FAILED;
5513 uint32_t drv_active = 0;
5514 struct qla_hw_data *ha = base_vha->hw;
5515 int fn;
5516 struct pci_dev *other_pdev = NULL;
5517
5518 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5519 "Entered %s.\n", __func__);
5520
5521 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5522
5523 if (base_vha->flags.online) {
5524 /* Abort all outstanding commands,
5525 * so as to be requeued later */
5526 qla2x00_abort_isp_cleanup(base_vha);
5527 }
5528
5529
5530 fn = PCI_FUNC(ha->pdev->devfn);
5531 while (fn > 0) {
5532 fn--;
5533 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5534 "Finding pci device at function = 0x%x.\n", fn);
5535 other_pdev =
5536 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5537 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5538 fn));
5539
5540 if (!other_pdev)
5541 continue;
5542 if (atomic_read(&other_pdev->enable_cnt)) {
5543 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5544 "Found PCI func available and enable at 0x%x.\n",
5545 fn);
5546 pci_dev_put(other_pdev);
5547 break;
5548 }
5549 pci_dev_put(other_pdev);
5550 }
5551
5552 if (!fn) {
5553 /* Reset owner */
5554 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5555 "This devfn is reset owner = 0x%x.\n",
5556 ha->pdev->devfn);
5557 qla82xx_idc_lock(ha);
5558
5559 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5560 QLA8XXX_DEV_INITIALIZING);
5561
5562 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5563 QLA82XX_IDC_VERSION);
5564
5565 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5566 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5567 "drv_active = 0x%x.\n", drv_active);
5568
5569 qla82xx_idc_unlock(ha);
5570 /* Reset if device is not already reset
5571 * drv_active would be 0 if a reset has already been done
5572 */
5573 if (drv_active)
5574 rval = qla82xx_start_firmware(base_vha);
5575 else
5576 rval = QLA_SUCCESS;
5577 qla82xx_idc_lock(ha);
5578
5579 if (rval != QLA_SUCCESS) {
5580 ql_log(ql_log_info, base_vha, 0x900b,
5581 "HW State: FAILED.\n");
5582 qla82xx_clear_drv_active(ha);
5583 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5584 QLA8XXX_DEV_FAILED);
5585 } else {
5586 ql_log(ql_log_info, base_vha, 0x900c,
5587 "HW State: READY.\n");
5588 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5589 QLA8XXX_DEV_READY);
5590 qla82xx_idc_unlock(ha);
5591 ha->flags.isp82xx_fw_hung = 0;
5592 rval = qla82xx_restart_isp(base_vha);
5593 qla82xx_idc_lock(ha);
5594 /* Clear driver state register */
5595 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5596 qla82xx_set_drv_active(base_vha);
5597 }
5598 qla82xx_idc_unlock(ha);
5599 } else {
5600 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5601 "This devfn is not reset owner = 0x%x.\n",
5602 ha->pdev->devfn);
5603 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5604 QLA8XXX_DEV_READY)) {
5605 ha->flags.isp82xx_fw_hung = 0;
5606 rval = qla82xx_restart_isp(base_vha);
5607 qla82xx_idc_lock(ha);
5608 qla82xx_set_drv_active(base_vha);
5609 qla82xx_idc_unlock(ha);
5610 }
5611 }
5612 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5613
5614 return rval;
5615 }
5616
5617 static pci_ers_result_t
5618 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5619 {
5620 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5621 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5622 struct qla_hw_data *ha = base_vha->hw;
5623 struct rsp_que *rsp;
5624 int rc, retries = 10;
5625
5626 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5627 "Slot Reset.\n");
5628
5629 /* Workaround: qla2xxx driver which access hardware earlier
5630 * needs error state to be pci_channel_io_online.
5631 * Otherwise mailbox command timesout.
5632 */
5633 pdev->error_state = pci_channel_io_normal;
5634
5635 pci_restore_state(pdev);
5636
5637 /* pci_restore_state() clears the saved_state flag of the device
5638 * save restored state which resets saved_state flag
5639 */
5640 pci_save_state(pdev);
5641
5642 if (ha->mem_only)
5643 rc = pci_enable_device_mem(pdev);
5644 else
5645 rc = pci_enable_device(pdev);
5646
5647 if (rc) {
5648 ql_log(ql_log_warn, base_vha, 0x9005,
5649 "Can't re-enable PCI device after reset.\n");
5650 goto exit_slot_reset;
5651 }
5652
5653 rsp = ha->rsp_q_map[0];
5654 if (qla2x00_request_irqs(ha, rsp))
5655 goto exit_slot_reset;
5656
5657 if (ha->isp_ops->pci_config(base_vha))
5658 goto exit_slot_reset;
5659
5660 if (IS_QLA82XX(ha)) {
5661 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5662 ret = PCI_ERS_RESULT_RECOVERED;
5663 goto exit_slot_reset;
5664 } else
5665 goto exit_slot_reset;
5666 }
5667
5668 while (ha->flags.mbox_busy && retries--)
5669 msleep(1000);
5670
5671 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5672 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5673 ret = PCI_ERS_RESULT_RECOVERED;
5674 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5675
5676
5677 exit_slot_reset:
5678 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5679 "slot_reset return %x.\n", ret);
5680
5681 return ret;
5682 }
5683
5684 static void
5685 qla2xxx_pci_resume(struct pci_dev *pdev)
5686 {
5687 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5688 struct qla_hw_data *ha = base_vha->hw;
5689 int ret;
5690
5691 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5692 "pci_resume.\n");
5693
5694 ret = qla2x00_wait_for_hba_online(base_vha);
5695 if (ret != QLA_SUCCESS) {
5696 ql_log(ql_log_fatal, base_vha, 0x9002,
5697 "The device failed to resume I/O from slot/link_reset.\n");
5698 }
5699
5700 pci_cleanup_aer_uncorrect_error_status(pdev);
5701
5702 ha->flags.eeh_busy = 0;
5703 }
5704
5705 static void
5706 qla83xx_disable_laser(scsi_qla_host_t *vha)
5707 {
5708 uint32_t reg, data, fn;
5709 struct qla_hw_data *ha = vha->hw;
5710 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5711
5712 /* pci func #/port # */
5713 ql_dbg(ql_dbg_init, vha, 0x004b,
5714 "Disabling Laser for hba: %p\n", vha);
5715
5716 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5717 (BIT_15|BIT_14|BIT_13|BIT_12));
5718
5719 fn = (fn >> 12);
5720
5721 if (fn & 1)
5722 reg = PORT_1_2031;
5723 else
5724 reg = PORT_0_2031;
5725
5726 data = LASER_OFF_2031;
5727
5728 qla83xx_wr_reg(vha, reg, data);
5729 }
5730
5731 static const struct pci_error_handlers qla2xxx_err_handler = {
5732 .error_detected = qla2xxx_pci_error_detected,
5733 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5734 .slot_reset = qla2xxx_pci_slot_reset,
5735 .resume = qla2xxx_pci_resume,
5736 };
5737
5738 static struct pci_device_id qla2xxx_pci_tbl[] = {
5739 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5740 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5741 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5742 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5743 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5744 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5745 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5746 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5747 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5748 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5749 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5750 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5751 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5752 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5753 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5754 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5760 { 0 },
5761 };
5762 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5763
5764 static struct pci_driver qla2xxx_pci_driver = {
5765 .name = QLA2XXX_DRIVER_NAME,
5766 .driver = {
5767 .owner = THIS_MODULE,
5768 },
5769 .id_table = qla2xxx_pci_tbl,
5770 .probe = qla2x00_probe_one,
5771 .remove = qla2x00_remove_one,
5772 .shutdown = qla2x00_shutdown,
5773 .err_handler = &qla2xxx_err_handler,
5774 };
5775
5776 static const struct file_operations apidev_fops = {
5777 .owner = THIS_MODULE,
5778 .llseek = noop_llseek,
5779 };
5780
5781 /**
5782 * qla2x00_module_init - Module initialization.
5783 **/
5784 static int __init
5785 qla2x00_module_init(void)
5786 {
5787 int ret = 0;
5788
5789 /* Allocate cache for SRBs. */
5790 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5791 SLAB_HWCACHE_ALIGN, NULL);
5792 if (srb_cachep == NULL) {
5793 ql_log(ql_log_fatal, NULL, 0x0001,
5794 "Unable to allocate SRB cache...Failing load!.\n");
5795 return -ENOMEM;
5796 }
5797
5798 /* Initialize target kmem_cache and mem_pools */
5799 ret = qlt_init();
5800 if (ret < 0) {
5801 kmem_cache_destroy(srb_cachep);
5802 return ret;
5803 } else if (ret > 0) {
5804 /*
5805 * If initiator mode is explictly disabled by qlt_init(),
5806 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5807 * performing scsi_scan_target() during LOOP UP event.
5808 */
5809 qla2xxx_transport_functions.disable_target_scan = 1;
5810 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5811 }
5812
5813 /* Derive version string. */
5814 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5815 if (ql2xextended_error_logging)
5816 strcat(qla2x00_version_str, "-debug");
5817
5818 qla2xxx_transport_template =
5819 fc_attach_transport(&qla2xxx_transport_functions);
5820 if (!qla2xxx_transport_template) {
5821 kmem_cache_destroy(srb_cachep);
5822 ql_log(ql_log_fatal, NULL, 0x0002,
5823 "fc_attach_transport failed...Failing load!.\n");
5824 qlt_exit();
5825 return -ENODEV;
5826 }
5827
5828 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5829 if (apidev_major < 0) {
5830 ql_log(ql_log_fatal, NULL, 0x0003,
5831 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5832 }
5833
5834 qla2xxx_transport_vport_template =
5835 fc_attach_transport(&qla2xxx_transport_vport_functions);
5836 if (!qla2xxx_transport_vport_template) {
5837 kmem_cache_destroy(srb_cachep);
5838 qlt_exit();
5839 fc_release_transport(qla2xxx_transport_template);
5840 ql_log(ql_log_fatal, NULL, 0x0004,
5841 "fc_attach_transport vport failed...Failing load!.\n");
5842 return -ENODEV;
5843 }
5844 ql_log(ql_log_info, NULL, 0x0005,
5845 "QLogic Fibre Channel HBA Driver: %s.\n",
5846 qla2x00_version_str);
5847 ret = pci_register_driver(&qla2xxx_pci_driver);
5848 if (ret) {
5849 kmem_cache_destroy(srb_cachep);
5850 qlt_exit();
5851 fc_release_transport(qla2xxx_transport_template);
5852 fc_release_transport(qla2xxx_transport_vport_template);
5853 ql_log(ql_log_fatal, NULL, 0x0006,
5854 "pci_register_driver failed...ret=%d Failing load!.\n",
5855 ret);
5856 }
5857 return ret;
5858 }
5859
5860 /**
5861 * qla2x00_module_exit - Module cleanup.
5862 **/
5863 static void __exit
5864 qla2x00_module_exit(void)
5865 {
5866 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5867 pci_unregister_driver(&qla2xxx_pci_driver);
5868 qla2x00_release_firmware();
5869 kmem_cache_destroy(srb_cachep);
5870 qlt_exit();
5871 if (ctx_cachep)
5872 kmem_cache_destroy(ctx_cachep);
5873 fc_release_transport(qla2xxx_transport_template);
5874 fc_release_transport(qla2xxx_transport_vport_template);
5875 }
5876
5877 module_init(qla2x00_module_init);
5878 module_exit(qla2x00_module_exit);
5879
5880 MODULE_AUTHOR("QLogic Corporation");
5881 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5882 MODULE_LICENSE("GPL");
5883 MODULE_VERSION(QLA2XXX_VERSION);
5884 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5885 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5886 MODULE_FIRMWARE(FW_FILE_ISP2300);
5887 MODULE_FIRMWARE(FW_FILE_ISP2322);
5888 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5889 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux kernel - Deliverables
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