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[libata sata_nv] eliminate duplicate codepaths with iomap
[deliverable/linux.git] / drivers / scsi / sata_nv.c
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.8"
48
49 enum {
50 NV_PORTS = 2,
51 NV_PIO_MASK = 0x1f,
52 NV_MWDMA_MASK = 0x07,
53 NV_UDMA_MASK = 0x7f,
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
56
57 NV_INT_STATUS = 0x10,
58 NV_INT_STATUS_CK804 = 0x440,
59 NV_INT_STATUS_PDEV_INT = 0x01,
60 NV_INT_STATUS_PDEV_PM = 0x02,
61 NV_INT_STATUS_PDEV_ADDED = 0x04,
62 NV_INT_STATUS_PDEV_REMOVED = 0x08,
63 NV_INT_STATUS_SDEV_INT = 0x10,
64 NV_INT_STATUS_SDEV_PM = 0x20,
65 NV_INT_STATUS_SDEV_ADDED = 0x40,
66 NV_INT_STATUS_SDEV_REMOVED = 0x80,
67 NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
68 NV_INT_STATUS_PDEV_REMOVED),
69 NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
70 NV_INT_STATUS_SDEV_REMOVED),
71 NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
72 NV_INT_STATUS_SDEV_HOTPLUG),
73
74 NV_INT_ENABLE = 0x11,
75 NV_INT_ENABLE_CK804 = 0x441,
76 NV_INT_ENABLE_PDEV_MASK = 0x01,
77 NV_INT_ENABLE_PDEV_PM = 0x02,
78 NV_INT_ENABLE_PDEV_ADDED = 0x04,
79 NV_INT_ENABLE_PDEV_REMOVED = 0x08,
80 NV_INT_ENABLE_SDEV_MASK = 0x10,
81 NV_INT_ENABLE_SDEV_PM = 0x20,
82 NV_INT_ENABLE_SDEV_ADDED = 0x40,
83 NV_INT_ENABLE_SDEV_REMOVED = 0x80,
84 NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
85 NV_INT_ENABLE_PDEV_REMOVED),
86 NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
87 NV_INT_ENABLE_SDEV_REMOVED),
88 NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
89 NV_INT_ENABLE_SDEV_HOTPLUG),
90
91 NV_INT_CONFIG = 0x12,
92 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
93
94 // For PCI config register 20
95 NV_MCP_SATA_CFG_20 = 0x50,
96 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
97 };
98
99 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
100 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
101 struct pt_regs *regs);
102 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
103 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
104 static void nv_host_stop (struct ata_host_set *host_set);
105 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
106 static void nv_disable_hotplug(struct ata_host_set *host_set);
107 static int nv_check_hotplug(struct ata_host_set *host_set);
108 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
109 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
110 static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
111
112 enum nv_host_type
113 {
114 GENERIC,
115 NFORCE2,
116 NFORCE3,
117 CK804
118 };
119
120 static const struct pci_device_id nv_pci_tbl[] = {
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
143 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
144 PCI_ANY_ID, PCI_ANY_ID,
145 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
146 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
147 PCI_ANY_ID, PCI_ANY_ID,
148 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
149 { 0, } /* terminate list */
150 };
151
152 struct nv_host_desc
153 {
154 enum nv_host_type host_type;
155 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
156 void (*disable_hotplug)(struct ata_host_set *host_set);
157 int (*check_hotplug)(struct ata_host_set *host_set);
158
159 };
160 static struct nv_host_desc nv_device_tbl[] = {
161 {
162 .host_type = GENERIC,
163 .enable_hotplug = NULL,
164 .disable_hotplug= NULL,
165 .check_hotplug = NULL,
166 },
167 {
168 .host_type = NFORCE2,
169 .enable_hotplug = nv_enable_hotplug,
170 .disable_hotplug= nv_disable_hotplug,
171 .check_hotplug = nv_check_hotplug,
172 },
173 {
174 .host_type = NFORCE3,
175 .enable_hotplug = nv_enable_hotplug,
176 .disable_hotplug= nv_disable_hotplug,
177 .check_hotplug = nv_check_hotplug,
178 },
179 { .host_type = CK804,
180 .enable_hotplug = nv_enable_hotplug_ck804,
181 .disable_hotplug= nv_disable_hotplug_ck804,
182 .check_hotplug = nv_check_hotplug_ck804,
183 },
184 };
185
186 struct nv_host
187 {
188 struct nv_host_desc *host_desc;
189 unsigned long host_flags;
190 };
191
192 static struct pci_driver nv_pci_driver = {
193 .name = DRV_NAME,
194 .id_table = nv_pci_tbl,
195 .probe = nv_init_one,
196 .remove = ata_pci_remove_one,
197 };
198
199 static struct scsi_host_template nv_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .eh_strategy_handler = ata_scsi_error,
205 .can_queue = ATA_DEF_QUEUE,
206 .this_id = ATA_SHT_THIS_ID,
207 .sg_tablesize = LIBATA_MAX_PRD,
208 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
209 .emulated = ATA_SHT_EMULATED,
210 .use_clustering = ATA_SHT_USE_CLUSTERING,
211 .proc_name = DRV_NAME,
212 .dma_boundary = ATA_DMA_BOUNDARY,
213 .slave_configure = ata_scsi_slave_config,
214 .bios_param = ata_std_bios_param,
215 };
216
217 static const struct ata_port_operations nv_ops = {
218 .port_disable = ata_port_disable,
219 .tf_load = ata_tf_load,
220 .tf_read = ata_tf_read,
221 .exec_command = ata_exec_command,
222 .check_status = ata_check_status,
223 .dev_select = ata_std_dev_select,
224 .phy_reset = sata_phy_reset,
225 .bmdma_setup = ata_bmdma_setup,
226 .bmdma_start = ata_bmdma_start,
227 .bmdma_stop = ata_bmdma_stop,
228 .bmdma_status = ata_bmdma_status,
229 .qc_prep = ata_qc_prep,
230 .qc_issue = ata_qc_issue_prot,
231 .eng_timeout = ata_eng_timeout,
232 .irq_handler = nv_interrupt,
233 .irq_clear = ata_bmdma_irq_clear,
234 .scr_read = nv_scr_read,
235 .scr_write = nv_scr_write,
236 .port_start = ata_port_start,
237 .port_stop = ata_port_stop,
238 .host_stop = nv_host_stop,
239 };
240
241 /* FIXME: The hardware provides the necessary SATA PHY controls
242 * to support ATA_FLAG_SATA_RESET. However, it is currently
243 * necessary to disable that flag, to solve misdetection problems.
244 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
245 *
246 * This problem really needs to be investigated further. But in the
247 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
248 */
249 static struct ata_port_info nv_port_info = {
250 .sht = &nv_sht,
251 .host_flags = ATA_FLAG_SATA |
252 /* ATA_FLAG_SATA_RESET | */
253 ATA_FLAG_SRST |
254 ATA_FLAG_NO_LEGACY,
255 .pio_mask = NV_PIO_MASK,
256 .mwdma_mask = NV_MWDMA_MASK,
257 .udma_mask = NV_UDMA_MASK,
258 .port_ops = &nv_ops,
259 };
260
261 MODULE_AUTHOR("NVIDIA");
262 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
263 MODULE_LICENSE("GPL");
264 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
265 MODULE_VERSION(DRV_VERSION);
266
267 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
268 struct pt_regs *regs)
269 {
270 struct ata_host_set *host_set = dev_instance;
271 struct nv_host *host = host_set->private_data;
272 unsigned int i;
273 unsigned int handled = 0;
274 unsigned long flags;
275
276 spin_lock_irqsave(&host_set->lock, flags);
277
278 for (i = 0; i < host_set->n_ports; i++) {
279 struct ata_port *ap;
280
281 ap = host_set->ports[i];
282 if (ap &&
283 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
284 struct ata_queued_cmd *qc;
285
286 qc = ata_qc_from_tag(ap, ap->active_tag);
287 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
288 handled += ata_host_intr(ap, qc);
289 else
290 // No request pending? Clear interrupt status
291 // anyway, in case there's one pending.
292 ap->ops->check_status(ap);
293 }
294
295 }
296
297 if (host->host_desc->check_hotplug)
298 handled += host->host_desc->check_hotplug(host_set);
299
300 spin_unlock_irqrestore(&host_set->lock, flags);
301
302 return IRQ_RETVAL(handled);
303 }
304
305 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
306 {
307 if (sc_reg > SCR_CONTROL)
308 return 0xffffffffU;
309
310 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
311 }
312
313 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
314 {
315 if (sc_reg > SCR_CONTROL)
316 return;
317
318 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
319 }
320
321 static void nv_host_stop (struct ata_host_set *host_set)
322 {
323 struct nv_host *host = host_set->private_data;
324
325 // Disable hotplug event interrupts.
326 if (host->host_desc->disable_hotplug)
327 host->host_desc->disable_hotplug(host_set);
328
329 kfree(host);
330
331 ata_pci_host_stop(host_set);
332 }
333
334 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
335 {
336 static int printed_version = 0;
337 struct nv_host *host;
338 struct ata_port_info *ppi;
339 struct ata_probe_ent *probe_ent;
340 int pci_dev_busy = 0;
341 int rc;
342 u32 bar;
343 unsigned long base;
344
345 // Make sure this is a SATA controller by counting the number of bars
346 // (NVIDIA SATA controllers will always have six bars). Otherwise,
347 // it's an IDE controller and we ignore it.
348 for (bar=0; bar<6; bar++)
349 if (pci_resource_start(pdev, bar) == 0)
350 return -ENODEV;
351
352 if (!printed_version++)
353 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
354
355 rc = pci_enable_device(pdev);
356 if (rc)
357 goto err_out;
358
359 rc = pci_request_regions(pdev, DRV_NAME);
360 if (rc) {
361 pci_dev_busy = 1;
362 goto err_out_disable;
363 }
364
365 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
366 if (rc)
367 goto err_out_regions;
368 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
369 if (rc)
370 goto err_out_regions;
371
372 rc = -ENOMEM;
373
374 ppi = &nv_port_info;
375 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
376 if (!probe_ent)
377 goto err_out_regions;
378
379 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
380 if (!host)
381 goto err_out_free_ent;
382
383 memset(host, 0, sizeof(struct nv_host));
384 host->host_desc = &nv_device_tbl[ent->driver_data];
385
386 probe_ent->private_data = host;
387
388 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
389 if (!probe_ent->mmio_base) {
390 rc = -EIO;
391 goto err_out_free_host;
392 }
393
394 base = (unsigned long)probe_ent->mmio_base;
395
396 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
397 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
398
399 pci_set_master(pdev);
400
401 rc = ata_device_add(probe_ent);
402 if (rc != NV_PORTS)
403 goto err_out_iounmap;
404
405 // Enable hotplug event interrupts.
406 if (host->host_desc->enable_hotplug)
407 host->host_desc->enable_hotplug(probe_ent);
408
409 kfree(probe_ent);
410
411 return 0;
412
413 err_out_iounmap:
414 pci_iounmap(pdev, probe_ent->mmio_base);
415 err_out_free_host:
416 kfree(host);
417 err_out_free_ent:
418 kfree(probe_ent);
419 err_out_regions:
420 pci_release_regions(pdev);
421 err_out_disable:
422 if (!pci_dev_busy)
423 pci_disable_device(pdev);
424 err_out:
425 return rc;
426 }
427
428 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
429 {
430 u8 intr_mask;
431
432 outb(NV_INT_STATUS_HOTPLUG,
433 probe_ent->port[0].scr_addr + NV_INT_STATUS);
434
435 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
436 intr_mask |= NV_INT_ENABLE_HOTPLUG;
437
438 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
439 }
440
441 static void nv_disable_hotplug(struct ata_host_set *host_set)
442 {
443 u8 intr_mask;
444
445 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
446
447 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
448
449 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
450 }
451
452 static int nv_check_hotplug(struct ata_host_set *host_set)
453 {
454 u8 intr_status;
455
456 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
457
458 // Clear interrupt status.
459 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
460
461 if (intr_status & NV_INT_STATUS_HOTPLUG) {
462 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
463 printk(KERN_WARNING "nv_sata: "
464 "Primary device added\n");
465
466 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
467 printk(KERN_WARNING "nv_sata: "
468 "Primary device removed\n");
469
470 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
471 printk(KERN_WARNING "nv_sata: "
472 "Secondary device added\n");
473
474 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
475 printk(KERN_WARNING "nv_sata: "
476 "Secondary device removed\n");
477
478 return 1;
479 }
480
481 return 0;
482 }
483
484 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
485 {
486 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
487 u8 intr_mask;
488 u8 regval;
489
490 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
491 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
492 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
493
494 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
495
496 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
497 intr_mask |= NV_INT_ENABLE_HOTPLUG;
498
499 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
500 }
501
502 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
503 {
504 struct pci_dev *pdev = to_pci_dev(host_set->dev);
505 u8 intr_mask;
506 u8 regval;
507
508 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
509
510 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
511
512 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
513
514 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
515 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
516 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
517 }
518
519 static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
520 {
521 u8 intr_status;
522
523 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
524
525 // Clear interrupt status.
526 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
527
528 if (intr_status & NV_INT_STATUS_HOTPLUG) {
529 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
530 printk(KERN_WARNING "nv_sata: "
531 "Primary device added\n");
532
533 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
534 printk(KERN_WARNING "nv_sata: "
535 "Primary device removed\n");
536
537 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
538 printk(KERN_WARNING "nv_sata: "
539 "Secondary device added\n");
540
541 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
542 printk(KERN_WARNING "nv_sata: "
543 "Secondary device removed\n");
544
545 return 1;
546 }
547
548 return 0;
549 }
550
551 static int __init nv_init(void)
552 {
553 return pci_module_init(&nv_pci_driver);
554 }
555
556 static void __exit nv_exit(void)
557 {
558 pci_unregister_driver(&nv_pci_driver);
559 }
560
561 module_init(nv_init);
562 module_exit(nv_exit);
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