drivers/scsi/sata_qstor.c

   1 /*
   2  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Pacific Digital Corporation.
   7  *  (OSL/GPL code release authorized by Jalil Fadavi).
   8  *
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; see the file COPYING.  If not, write to
  22  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  *
  25  *  libata documentation is available via 'make {ps|pdf}docs',
  26  *  as Documentation/DocBook/libata.*
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/init.h>
  34 #include <linux/blkdev.h>
  35 #include <linux/delay.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/sched.h>
  38 #include "scsi.h"
  39 #include <scsi/scsi_host.h>
  40 #include <asm/io.h>
  41 #include <linux/libata.h>
  42
  43 #define DRV_NAME        "sata_qstor"
  44 #define DRV_VERSION     "0.04"
  45
  46 enum {
  47         QS_PORTS                = 4,
  48         QS_MAX_PRD              = LIBATA_MAX_PRD,
  49         QS_CPB_ORDER            = 6,
  50         QS_CPB_BYTES            = (1 << QS_CPB_ORDER),
  51         QS_PRD_BYTES            = QS_MAX_PRD * 16,
  52         QS_PKT_BYTES            = QS_CPB_BYTES + QS_PRD_BYTES,
  53
  54         /* global register offsets */
  55         QS_HCF_CNFG3            = 0x0003, /* host configuration offset */
  56         QS_HID_HPHY             = 0x0004, /* host physical interface info */
  57         QS_HCT_CTRL             = 0x00e4, /* global interrupt mask offset */
  58         QS_HST_SFF              = 0x0100, /* host status fifo offset */
  59         QS_HVS_SERD3            = 0x0393, /* PHY enable offset */
  60
  61         /* global control bits */
  62         QS_HPHY_64BIT           = (1 << 1), /* 64-bit bus detected */
  63         QS_CNFG3_GSRST          = 0x01,     /* global chip reset */
  64         QS_SERD3_PHY_ENA        = 0xf0,     /* PHY detection ENAble*/
  65
  66         /* per-channel register offsets */
  67         QS_CCF_CPBA             = 0x0710, /* chan CPB base address */
  68         QS_CCF_CSEP             = 0x0718, /* chan CPB separation factor */
  69         QS_CFC_HUFT             = 0x0800, /* host upstream fifo threshold */
  70         QS_CFC_HDFT             = 0x0804, /* host downstream fifo threshold */
  71         QS_CFC_DUFT             = 0x0808, /* dev upstream fifo threshold */
  72         QS_CFC_DDFT             = 0x080c, /* dev downstream fifo threshold */
  73         QS_CCT_CTR0             = 0x0900, /* chan control-0 offset */
  74         QS_CCT_CTR1             = 0x0901, /* chan control-1 offset */
  75         QS_CCT_CFF              = 0x0a00, /* chan command fifo offset */
  76
  77         /* channel control bits */
  78         QS_CTR0_REG             = (1 << 1),   /* register mode (vs. pkt mode) */
  79         QS_CTR0_CLER            = (1 << 2),   /* clear channel errors */
  80         QS_CTR1_RDEV            = (1 << 1),   /* sata phy/comms reset */
  81         QS_CTR1_RCHN            = (1 << 4),   /* reset channel logic */
  82         QS_CCF_RUN_PKT          = 0x107,      /* RUN a new dma PKT */
  83
  84         /* pkt sub-field headers */
  85         QS_HCB_HDR              = 0x01,   /* Host Control Block header */
  86         QS_DCB_HDR              = 0x02,   /* Device Control Block header */
  87
  88         /* pkt HCB flag bits */
  89         QS_HF_DIRO              = (1 << 0),   /* data DIRection Out */
  90         QS_HF_DAT               = (1 << 3),   /* DATa pkt */
  91         QS_HF_IEN               = (1 << 4),   /* Interrupt ENable */
  92         QS_HF_VLD               = (1 << 5),   /* VaLiD pkt */
  93
  94         /* pkt DCB flag bits */
  95         QS_DF_PORD              = (1 << 2),   /* Pio OR Dma */
  96         QS_DF_ELBA              = (1 << 3),   /* Extended LBA (lba48) */
  97
  98         /* PCI device IDs */
  99         board_2068_idx          = 0,    /* QStor 4-port SATA/RAID */
 100 };
 101
 102 enum {
 103         QS_DMA_BOUNDARY         = ~0UL
 104 };
 105
 106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
 107
 108 struct qs_port_priv {
 109         u8                      *pkt;
 110         dma_addr_t              pkt_dma;
 111         qs_state_t              state;
 112 };
 113
 114 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
 115 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
 116 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 117 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
 118 static int qs_port_start(struct ata_port *ap);
 119 static void qs_host_stop(struct ata_host_set *host_set);
 120 static void qs_port_stop(struct ata_port *ap);
 121 static void qs_phy_reset(struct ata_port *ap);
 122 static void qs_qc_prep(struct ata_queued_cmd *qc);
 123 static int qs_qc_issue(struct ata_queued_cmd *qc);
 124 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
 125 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
 126 static u8 qs_bmdma_status(struct ata_port *ap);
 127 static void qs_irq_clear(struct ata_port *ap);
 128 static void qs_eng_timeout(struct ata_port *ap);
 129
 130 static Scsi_Host_Template qs_ata_sht = {
 131         .module                 = THIS_MODULE,
 132         .name                   = DRV_NAME,
 133         .ioctl                  = ata_scsi_ioctl,
 134         .queuecommand           = ata_scsi_queuecmd,
 135         .eh_strategy_handler    = ata_scsi_error,
 136         .can_queue              = ATA_DEF_QUEUE,
 137         .this_id                = ATA_SHT_THIS_ID,
 138         .sg_tablesize           = QS_MAX_PRD,
 139         .max_sectors            = ATA_MAX_SECTORS,
 140         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 141         .emulated               = ATA_SHT_EMULATED,
 142         //FIXME .use_clustering         = ATA_SHT_USE_CLUSTERING,
 143         .use_clustering         = ENABLE_CLUSTERING,
 144         .proc_name              = DRV_NAME,
 145         .dma_boundary           = QS_DMA_BOUNDARY,
 146         .slave_configure        = ata_scsi_slave_config,
 147         .bios_param             = ata_std_bios_param,
 148 };
 149
 150 static const struct ata_port_operations qs_ata_ops = {
 151         .port_disable           = ata_port_disable,
 152         .tf_load                = ata_tf_load,
 153         .tf_read                = ata_tf_read,
 154         .check_status           = ata_check_status,
 155         .check_atapi_dma        = qs_check_atapi_dma,
 156         .exec_command           = ata_exec_command,
 157         .dev_select             = ata_std_dev_select,
 158         .phy_reset              = qs_phy_reset,
 159         .qc_prep                = qs_qc_prep,
 160         .qc_issue               = qs_qc_issue,
 161         .eng_timeout            = qs_eng_timeout,
 162         .irq_handler            = qs_intr,
 163         .irq_clear              = qs_irq_clear,
 164         .scr_read               = qs_scr_read,
 165         .scr_write              = qs_scr_write,
 166         .port_start             = qs_port_start,
 167         .port_stop              = qs_port_stop,
 168         .host_stop              = qs_host_stop,
 169         .bmdma_stop             = qs_bmdma_stop,
 170         .bmdma_status           = qs_bmdma_status,
 171 };
 172
 173 static struct ata_port_info qs_port_info[] = {
 174         /* board_2068_idx */
 175         {
 176                 .sht            = &qs_ata_sht,
 177                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 178                                   ATA_FLAG_SATA_RESET |
 179                                   //FIXME ATA_FLAG_SRST |
 180                                   ATA_FLAG_MMIO,
 181                 .pio_mask       = 0x10, /* pio4 */
 182                 .udma_mask      = 0x7f, /* udma0-6 */
 183                 .port_ops       = &qs_ata_ops,
 184         },
 185 };
 186
 187 static struct pci_device_id qs_ata_pci_tbl[] = {
 188         { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 189           board_2068_idx },
 190
 191         { }     /* terminate list */
 192 };
 193
 194 static struct pci_driver qs_ata_pci_driver = {
 195         .name                   = DRV_NAME,
 196         .id_table               = qs_ata_pci_tbl,
 197         .probe                  = qs_ata_init_one,
 198         .remove                 = ata_pci_remove_one,
 199 };
 200
 201 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
 202 {
 203         return 1;       /* ATAPI DMA not supported */
 204 }
 205
 206 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
 207 {
 208         /* nothing */
 209 }
 210
 211 static u8 qs_bmdma_status(struct ata_port *ap)
 212 {
 213         return 0;
 214 }
 215
 216 static void qs_irq_clear(struct ata_port *ap)
 217 {
 218         /* nothing */
 219 }
 220
 221 static inline void qs_enter_reg_mode(struct ata_port *ap)
 222 {
 223         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 224
 225         writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 226         readb(chan + QS_CCT_CTR0);        /* flush */
 227 }
 228
 229 static inline void qs_reset_channel_logic(struct ata_port *ap)
 230 {
 231         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 232
 233         writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 234         readb(chan + QS_CCT_CTR0);        /* flush */
 235         qs_enter_reg_mode(ap);
 236 }
 237
 238 static void qs_phy_reset(struct ata_port *ap)
 239 {
 240         struct qs_port_priv *pp = ap->private_data;
 241
 242         pp->state = qs_state_idle;
 243         qs_reset_channel_logic(ap);
 244         sata_phy_reset(ap);
 245 }
 246
 247 static void qs_eng_timeout(struct ata_port *ap)
 248 {
 249         struct qs_port_priv *pp = ap->private_data;
 250
 251         if (pp->state != qs_state_idle) /* healthy paranoia */
 252                 pp->state = qs_state_mmio;
 253         qs_reset_channel_logic(ap);
 254         ata_eng_timeout(ap);
 255 }
 256
 257 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
 258 {
 259         if (sc_reg > SCR_CONTROL)
 260                 return ~0U;
 261         return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
 262 }
 263
 264 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 265 {
 266         if (sc_reg > SCR_CONTROL)
 267                 return;
 268         writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
 269 }
 270
 271 static void qs_fill_sg(struct ata_queued_cmd *qc)
 272 {
 273         struct scatterlist *sg = qc->sg;
 274         struct ata_port *ap = qc->ap;
 275         struct qs_port_priv *pp = ap->private_data;
 276         unsigned int nelem;
 277         u8 *prd = pp->pkt + QS_CPB_BYTES;
 278
 279         assert(sg != NULL);
 280         assert(qc->n_elem > 0);
 281
 282         for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
 283                 u64 addr;
 284                 u32 len;
 285
 286                 addr = sg_dma_address(sg);
 287                 *(__le64 *)prd = cpu_to_le64(addr);
 288                 prd += sizeof(u64);
 289
 290                 len = sg_dma_len(sg);
 291                 *(__le32 *)prd = cpu_to_le32(len);
 292                 prd += sizeof(u64);
 293
 294                 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
 295                                         (unsigned long long)addr, len);
 296         }
 297 }
 298
 299 static void qs_qc_prep(struct ata_queued_cmd *qc)
 300 {
 301         struct qs_port_priv *pp = qc->ap->private_data;
 302         u8 dflags = QS_DF_PORD, *buf = pp->pkt;
 303         u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
 304         u64 addr;
 305
 306         VPRINTK("ENTER\n");
 307
 308         qs_enter_reg_mode(qc->ap);
 309         if (qc->tf.protocol != ATA_PROT_DMA) {
 310                 ata_qc_prep(qc);
 311                 return;
 312         }
 313
 314         qs_fill_sg(qc);
 315
 316         if ((qc->tf.flags & ATA_TFLAG_WRITE))
 317                 hflags |= QS_HF_DIRO;
 318         if ((qc->tf.flags & ATA_TFLAG_LBA48))
 319                 dflags |= QS_DF_ELBA;
 320
 321         /* host control block (HCB) */
 322         buf[ 0] = QS_HCB_HDR;
 323         buf[ 1] = hflags;
 324         *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
 325         *(__le32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem);
 326         addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
 327         *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
 328
 329         /* device control block (DCB) */
 330         buf[24] = QS_DCB_HDR;
 331         buf[28] = dflags;
 332
 333         /* frame information structure (FIS) */
 334         ata_tf_to_fis(&qc->tf, &buf[32], 0);
 335 }
 336
 337 static inline void qs_packet_start(struct ata_queued_cmd *qc)
 338 {
 339         struct ata_port *ap = qc->ap;
 340         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 341
 342         VPRINTK("ENTER, ap %p\n", ap);
 343
 344         writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
 345         wmb();                             /* flush PRDs and pkt to memory */
 346         writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
 347         readl(chan + QS_CCT_CFF);          /* flush */
 348 }
 349
 350 static int qs_qc_issue(struct ata_queued_cmd *qc)
 351 {
 352         struct qs_port_priv *pp = qc->ap->private_data;
 353
 354         switch (qc->tf.protocol) {
 355         case ATA_PROT_DMA:
 356
 357                 pp->state = qs_state_pkt;
 358                 qs_packet_start(qc);
 359                 return 0;
 360
 361         case ATA_PROT_ATAPI_DMA:
 362                 BUG();
 363                 break;
 364
 365         default:
 366                 break;
 367         }
 368
 369         pp->state = qs_state_mmio;
 370         return ata_qc_issue_prot(qc);
 371 }
 372
 373 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
 374 {
 375         unsigned int handled = 0;
 376         u8 sFFE;
 377         u8 __iomem *mmio_base = host_set->mmio_base;
 378
 379         do {
 380                 u32 sff0 = readl(mmio_base + QS_HST_SFF);
 381                 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
 382                 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
 383                 sFFE  = sff1 >> 31;             /* empty flag */
 384
 385                 if (sEVLD) {
 386                         u8 sDST = sff0 >> 16;   /* dev status */
 387                         u8 sHST = sff1 & 0x3f;  /* host status */
 388                         unsigned int port_no = (sff1 >> 8) & 0x03;
 389                         struct ata_port *ap = host_set->ports[port_no];
 390
 391                         DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
 392                                         sff1, sff0, port_no, sHST, sDST);
 393                         handled = 1;
 394                         if (ap && !(ap->flags &
 395                                     (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
 396                                 struct ata_queued_cmd *qc;
 397                                 struct qs_port_priv *pp = ap->private_data;
 398                                 if (!pp || pp->state != qs_state_pkt)
 399                                         continue;
 400                                 qc = ata_qc_from_tag(ap, ap->active_tag);
 401                                 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
 402                                         switch (sHST) {
 403                                         case 0: /* successful CPB */
 404                                         case 3: /* device error */
 405                                                 pp->state = qs_state_idle;
 406                                                 qs_enter_reg_mode(qc->ap);
 407                                                 ata_qc_complete(qc,
 408                                                         ac_err_mask(sDST));
 409                                                 break;
 410                                         default:
 411                                                 break;
 412                                         }
 413                                 }
 414                         }
 415                 }
 416         } while (!sFFE);
 417         return handled;
 418 }
 419
 420 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
 421 {
 422         unsigned int handled = 0, port_no;
 423
 424         for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
 425                 struct ata_port *ap;
 426                 ap = host_set->ports[port_no];
 427                 if (ap &&
 428                     !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
 429                         struct ata_queued_cmd *qc;
 430                         struct qs_port_priv *pp = ap->private_data;
 431                         if (!pp || pp->state != qs_state_mmio)
 432                                 continue;
 433                         qc = ata_qc_from_tag(ap, ap->active_tag);
 434                         if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
 435
 436                                 /* check main status, clearing INTRQ */
 437                                 u8 status = ata_check_status(ap);
 438                                 if ((status & ATA_BUSY))
 439                                         continue;
 440                                 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
 441                                         ap->id, qc->tf.protocol, status);
 442
 443                                 /* complete taskfile transaction */
 444                                 pp->state = qs_state_idle;
 445                                 ata_qc_complete(qc, ac_err_mask(status));
 446                                 handled = 1;
 447                         }
 448                 }
 449         }
 450         return handled;
 451 }
 452
 453 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
 454 {
 455         struct ata_host_set *host_set = dev_instance;
 456         unsigned int handled = 0;
 457
 458         VPRINTK("ENTER\n");
 459
 460         spin_lock(&host_set->lock);
 461         handled  = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
 462         spin_unlock(&host_set->lock);
 463
 464         VPRINTK("EXIT\n");
 465
 466         return IRQ_RETVAL(handled);
 467 }
 468
 469 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
 470 {
 471         port->cmd_addr          =
 472         port->data_addr         = base + 0x400;
 473         port->error_addr        =
 474         port->feature_addr      = base + 0x408; /* hob_feature = 0x409 */
 475         port->nsect_addr        = base + 0x410; /* hob_nsect   = 0x411 */
 476         port->lbal_addr         = base + 0x418; /* hob_lbal    = 0x419 */
 477         port->lbam_addr         = base + 0x420; /* hob_lbam    = 0x421 */
 478         port->lbah_addr         = base + 0x428; /* hob_lbah    = 0x429 */
 479         port->device_addr       = base + 0x430;
 480         port->status_addr       =
 481         port->command_addr      = base + 0x438;
 482         port->altstatus_addr    =
 483         port->ctl_addr          = base + 0x440;
 484         port->scr_addr          = base + 0xc00;
 485 }
 486
 487 static int qs_port_start(struct ata_port *ap)
 488 {
 489         struct device *dev = ap->host_set->dev;
 490         struct qs_port_priv *pp;
 491         void __iomem *mmio_base = ap->host_set->mmio_base;
 492         void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
 493         u64 addr;
 494         int rc;
 495
 496         rc = ata_port_start(ap);
 497         if (rc)
 498                 return rc;
 499         qs_enter_reg_mode(ap);
 500         pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 501         if (!pp) {
 502                 rc = -ENOMEM;
 503                 goto err_out;
 504         }
 505         pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
 506                                                                 GFP_KERNEL);
 507         if (!pp->pkt) {
 508                 rc = -ENOMEM;
 509                 goto err_out_kfree;
 510         }
 511         memset(pp->pkt, 0, QS_PKT_BYTES);
 512         ap->private_data = pp;
 513
 514         addr = (u64)pp->pkt_dma;
 515         writel((u32) addr,        chan + QS_CCF_CPBA);
 516         writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
 517         return 0;
 518
 519 err_out_kfree:
 520         kfree(pp);
 521 err_out:
 522         ata_port_stop(ap);
 523         return rc;
 524 }
 525
 526 static void qs_port_stop(struct ata_port *ap)
 527 {
 528         struct device *dev = ap->host_set->dev;
 529         struct qs_port_priv *pp = ap->private_data;
 530
 531         if (pp != NULL) {
 532                 ap->private_data = NULL;
 533                 if (pp->pkt != NULL)
 534                         dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
 535                                                                 pp->pkt_dma);
 536                 kfree(pp);
 537         }
 538         ata_port_stop(ap);
 539 }
 540
 541 static void qs_host_stop(struct ata_host_set *host_set)
 542 {
 543         void __iomem *mmio_base = host_set->mmio_base;
 544         struct pci_dev *pdev = to_pci_dev(host_set->dev);
 545
 546         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 547         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 548
 549         pci_iounmap(pdev, mmio_base);
 550 }
 551
 552 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
 553 {
 554         void __iomem *mmio_base = pe->mmio_base;
 555         unsigned int port_no;
 556
 557         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 558         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 559
 560         /* reset each channel in turn */
 561         for (port_no = 0; port_no < pe->n_ports; ++port_no) {
 562                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 563                 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 564                 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 565                 readb(chan + QS_CCT_CTR0);        /* flush */
 566         }
 567         writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
 568
 569         for (port_no = 0; port_no < pe->n_ports; ++port_no) {
 570                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 571                 /* set FIFO depths to same settings as Windows driver */
 572                 writew(32, chan + QS_CFC_HUFT);
 573                 writew(32, chan + QS_CFC_HDFT);
 574                 writew(10, chan + QS_CFC_DUFT);
 575                 writew( 8, chan + QS_CFC_DDFT);
 576                 /* set CPB size in bytes, as a power of two */
 577                 writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
 578         }
 579         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 580 }
 581
 582 /*
 583  * The QStor understands 64-bit buses, and uses 64-bit fields
 584  * for DMA pointers regardless of bus width.  We just have to
 585  * make sure our DMA masks are set appropriately for whatever
 586  * bridge lies between us and the QStor, and then the DMA mapping
 587  * code will ensure we only ever "see" appropriate buffer addresses.
 588  * If we're 32-bit limited somewhere, then our 64-bit fields will
 589  * just end up with zeros in the upper 32-bits, without any special
 590  * logic required outside of this routine (below).
 591  */
 592 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 593 {
 594         u32 bus_info = readl(mmio_base + QS_HID_HPHY);
 595         int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
 596
 597         if (have_64bit_bus &&
 598             !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
 599                 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
 600                 if (rc) {
 601                         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 602                         if (rc) {
 603                                 printk(KERN_ERR DRV_NAME
 604                                         "(%s): 64-bit DMA enable failed\n",
 605                                         pci_name(pdev));
 606                                 return rc;
 607                         }
 608                 }
 609         } else {
 610                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 611                 if (rc) {
 612                         printk(KERN_ERR DRV_NAME
 613                                 "(%s): 32-bit DMA enable failed\n",
 614                                 pci_name(pdev));
 615                         return rc;
 616                 }
 617                 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 618                 if (rc) {
 619                         printk(KERN_ERR DRV_NAME
 620                                 "(%s): 32-bit consistent DMA enable failed\n",
 621                                 pci_name(pdev));
 622                         return rc;
 623                 }
 624         }
 625         return 0;
 626 }
 627
 628 static int qs_ata_init_one(struct pci_dev *pdev,
 629                                 const struct pci_device_id *ent)
 630 {
 631         static int printed_version;
 632         struct ata_probe_ent *probe_ent = NULL;
 633         void __iomem *mmio_base;
 634         unsigned int board_idx = (unsigned int) ent->driver_data;
 635         int rc, port_no;
 636
 637         if (!printed_version++)
 638                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
 639
 640         rc = pci_enable_device(pdev);
 641         if (rc)
 642                 return rc;
 643
 644         rc = pci_request_regions(pdev, DRV_NAME);
 645         if (rc)
 646                 goto err_out;
 647
 648         if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
 649                 rc = -ENODEV;
 650                 goto err_out_regions;
 651         }
 652
 653         mmio_base = pci_iomap(pdev, 4, 0);
 654         if (mmio_base == NULL) {
 655                 rc = -ENOMEM;
 656                 goto err_out_regions;
 657         }
 658
 659         rc = qs_set_dma_masks(pdev, mmio_base);
 660         if (rc)
 661                 goto err_out_iounmap;
 662
 663         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 664         if (probe_ent == NULL) {
 665                 rc = -ENOMEM;
 666                 goto err_out_iounmap;
 667         }
 668
 669         memset(probe_ent, 0, sizeof(*probe_ent));
 670         probe_ent->dev = pci_dev_to_dev(pdev);
 671         INIT_LIST_HEAD(&probe_ent->node);
 672
 673         probe_ent->sht          = qs_port_info[board_idx].sht;
 674         probe_ent->host_flags   = qs_port_info[board_idx].host_flags;
 675         probe_ent->pio_mask     = qs_port_info[board_idx].pio_mask;
 676         probe_ent->mwdma_mask   = qs_port_info[board_idx].mwdma_mask;
 677         probe_ent->udma_mask    = qs_port_info[board_idx].udma_mask;
 678         probe_ent->port_ops     = qs_port_info[board_idx].port_ops;
 679
 680         probe_ent->irq          = pdev->irq;
 681         probe_ent->irq_flags    = SA_SHIRQ;
 682         probe_ent->mmio_base    = mmio_base;
 683         probe_ent->n_ports      = QS_PORTS;
 684
 685         for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
 686                 unsigned long chan = (unsigned long)mmio_base +
 687                                                         (port_no * 0x4000);
 688                 qs_ata_setup_port(&probe_ent->port[port_no], chan);
 689         }
 690
 691         pci_set_master(pdev);
 692
 693         /* initialize adapter */
 694         qs_host_init(board_idx, probe_ent);
 695
 696         rc = ata_device_add(probe_ent);
 697         kfree(probe_ent);
 698         if (rc != QS_PORTS)
 699                 goto err_out_iounmap;
 700         return 0;
 701
 702 err_out_iounmap:
 703         pci_iounmap(pdev, mmio_base);
 704 err_out_regions:
 705         pci_release_regions(pdev);
 706 err_out:
 707         pci_disable_device(pdev);
 708         return rc;
 709 }
 710
 711 static int __init qs_ata_init(void)
 712 {
 713         return pci_module_init(&qs_ata_pci_driver);
 714 }
 715
 716 static void __exit qs_ata_exit(void)
 717 {
 718         pci_unregister_driver(&qs_ata_pci_driver);
 719 }
 720
 721 MODULE_AUTHOR("Mark Lord");
 722 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
 723 MODULE_LICENSE("GPL");
 724 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
 725 MODULE_VERSION(DRV_VERSION);
 726
 727 module_init(qs_ata_init);
 728 module_exit(qs_ata_exit);