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[deliverable/linux.git] / drivers / scsi / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <scsi/scsi_host.h>
39 #include "scsi.h"
40 #include <linux/libata.h>
41 #include <asm/io.h>
42
43 #define DRV_NAME "sata_sil24"
44 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
45
46 /*
47 * Port request block (PRB) 32 bytes
48 */
49 struct sil24_prb {
50 u16 ctrl;
51 u16 prot;
52 u32 rx_cnt;
53 u8 fis[6 * 4];
54 };
55
56 /*
57 * Scatter gather entry (SGE) 16 bytes
58 */
59 struct sil24_sge {
60 u64 addr;
61 u32 cnt;
62 u32 flags;
63 };
64
65 /*
66 * Port multiplier
67 */
68 struct sil24_port_multiplier {
69 u32 diag;
70 u32 sactive;
71 };
72
73 enum {
74 /*
75 * Global controller registers (128 bytes @ BAR0)
76 */
77 /* 32 bit regs */
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 /* 32 bit regs */
108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
114 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
115 PORT_CMD_ERR = 0x1024, /* command error number */
116 PORT_FIS_CFG = 0x1028,
117 PORT_FIFO_THRES = 0x102c,
118 /* 16 bit regs */
119 PORT_DECODE_ERR_CNT = 0x1040,
120 PORT_DECODE_ERR_THRESH = 0x1042,
121 PORT_CRC_ERR_CNT = 0x1044,
122 PORT_CRC_ERR_THRESH = 0x1046,
123 PORT_HSHK_ERR_CNT = 0x1048,
124 PORT_HSHK_ERR_THRESH = 0x104a,
125 /* 32 bit regs */
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00,
132 PORT_SSTATUS = 0x1f04,
133 PORT_SERROR = 0x1f08,
134 PORT_SACTIVE = 0x1f0c,
135
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST = (1 << 0), /* port reset */
138 PORT_CS_DEV_RST = (1 << 1), /* device reset */
139 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
155 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
156
157 /* bits[27:16] are unmasked (raw) */
158 PORT_IRQ_RAW_SHIFT = 16,
159 PORT_IRQ_MASKED_MASK = 0x7ff,
160 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
161
162 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
163 PORT_IRQ_STEER_SHIFT = 30,
164 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
165
166 /* PORT_CMD_ERR constants */
167 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
168 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
169 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
170 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
171 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
172 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
173 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
174 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
175 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
176 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
177 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
178 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
179 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
180 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
181 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
182 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
183 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
184 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
185 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
186 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
187 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
188 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
189
190 /*
191 * Other constants
192 */
193 SGE_TRM = (1 << 31), /* Last SGE in chain */
194 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
195
196 /* board id */
197 BID_SIL3124 = 0,
198 BID_SIL3132 = 1,
199 BID_SIL3131 = 2,
200
201 IRQ_STAT_4PORTS = 0xf,
202 };
203
204 struct sil24_cmd_block {
205 struct sil24_prb prb;
206 struct sil24_sge sge[LIBATA_MAX_PRD];
207 };
208
209 /*
210 * ap->private_data
211 *
212 * The preview driver always returned 0 for status. We emulate it
213 * here from the previous interrupt.
214 */
215 struct sil24_port_priv {
216 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
217 dma_addr_t cmd_block_dma; /* DMA base addr for them */
218 struct ata_taskfile tf; /* Cached taskfile registers */
219 };
220
221 /* ap->host_set->private_data */
222 struct sil24_host_priv {
223 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
224 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
225 };
226
227 static u8 sil24_check_status(struct ata_port *ap);
228 static u8 sil24_check_err(struct ata_port *ap);
229 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
230 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
231 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
232 static void sil24_phy_reset(struct ata_port *ap);
233 static void sil24_qc_prep(struct ata_queued_cmd *qc);
234 static int sil24_qc_issue(struct ata_queued_cmd *qc);
235 static void sil24_irq_clear(struct ata_port *ap);
236 static void sil24_eng_timeout(struct ata_port *ap);
237 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
238 static int sil24_port_start(struct ata_port *ap);
239 static void sil24_port_stop(struct ata_port *ap);
240 static void sil24_host_stop(struct ata_host_set *host_set);
241 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
242
243 static struct pci_device_id sil24_pci_tbl[] = {
244 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
245 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
246 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
247 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
248 { } /* terminate list */
249 };
250
251 static struct pci_driver sil24_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = sil24_pci_tbl,
254 .probe = sil24_init_one,
255 .remove = ata_pci_remove_one, /* safe? */
256 };
257
258 static Scsi_Host_Template sil24_sht = {
259 .module = THIS_MODULE,
260 .name = DRV_NAME,
261 .ioctl = ata_scsi_ioctl,
262 .queuecommand = ata_scsi_queuecmd,
263 .eh_strategy_handler = ata_scsi_error,
264 .can_queue = ATA_DEF_QUEUE,
265 .this_id = ATA_SHT_THIS_ID,
266 .sg_tablesize = LIBATA_MAX_PRD,
267 .max_sectors = ATA_MAX_SECTORS,
268 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
269 .emulated = ATA_SHT_EMULATED,
270 .use_clustering = ATA_SHT_USE_CLUSTERING,
271 .proc_name = DRV_NAME,
272 .dma_boundary = ATA_DMA_BOUNDARY,
273 .slave_configure = ata_scsi_slave_config,
274 .bios_param = ata_std_bios_param,
275 .ordered_flush = 1, /* NCQ not supported yet */
276 };
277
278 static const struct ata_port_operations sil24_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = sil24_check_status,
282 .check_altstatus = sil24_check_status,
283 .check_err = sil24_check_err,
284 .dev_select = ata_noop_dev_select,
285
286 .tf_read = sil24_tf_read,
287
288 .phy_reset = sil24_phy_reset,
289
290 .qc_prep = sil24_qc_prep,
291 .qc_issue = sil24_qc_issue,
292
293 .eng_timeout = sil24_eng_timeout,
294
295 .irq_handler = sil24_interrupt,
296 .irq_clear = sil24_irq_clear,
297
298 .scr_read = sil24_scr_read,
299 .scr_write = sil24_scr_write,
300
301 .port_start = sil24_port_start,
302 .port_stop = sil24_port_stop,
303 .host_stop = sil24_host_stop,
304 };
305
306 /*
307 * Use bits 30-31 of host_flags to encode available port numbers.
308 * Current maxium is 4.
309 */
310 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
311 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
312
313 static struct ata_port_info sil24_port_info[] = {
314 /* sil_3124 */
315 {
316 .sht = &sil24_sht,
317 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
318 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
319 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
320 .pio_mask = 0x1f, /* pio0-4 */
321 .mwdma_mask = 0x07, /* mwdma0-2 */
322 .udma_mask = 0x3f, /* udma0-5 */
323 .port_ops = &sil24_ops,
324 },
325 /* sil_3132 */
326 {
327 .sht = &sil24_sht,
328 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
329 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
330 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
331 .pio_mask = 0x1f, /* pio0-4 */
332 .mwdma_mask = 0x07, /* mwdma0-2 */
333 .udma_mask = 0x3f, /* udma0-5 */
334 .port_ops = &sil24_ops,
335 },
336 /* sil_3131/sil_3531 */
337 {
338 .sht = &sil24_sht,
339 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
340 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
341 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
342 .pio_mask = 0x1f, /* pio0-4 */
343 .mwdma_mask = 0x07, /* mwdma0-2 */
344 .udma_mask = 0x3f, /* udma0-5 */
345 .port_ops = &sil24_ops,
346 },
347 };
348
349 static inline void sil24_update_tf(struct ata_port *ap)
350 {
351 struct sil24_port_priv *pp = ap->private_data;
352 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
353 struct sil24_prb __iomem *prb = port;
354 u8 fis[6 * 4];
355
356 memcpy_fromio(fis, prb->fis, 6 * 4);
357 ata_tf_from_fis(fis, &pp->tf);
358 }
359
360 static u8 sil24_check_status(struct ata_port *ap)
361 {
362 struct sil24_port_priv *pp = ap->private_data;
363 return pp->tf.command;
364 }
365
366 static u8 sil24_check_err(struct ata_port *ap)
367 {
368 struct sil24_port_priv *pp = ap->private_data;
369 return pp->tf.feature;
370 }
371
372 static int sil24_scr_map[] = {
373 [SCR_CONTROL] = 0,
374 [SCR_STATUS] = 1,
375 [SCR_ERROR] = 2,
376 [SCR_ACTIVE] = 3,
377 };
378
379 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
380 {
381 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
382 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
383 void __iomem *addr;
384 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
385 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
386 }
387 return 0xffffffffU;
388 }
389
390 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
391 {
392 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
393 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
394 void __iomem *addr;
395 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
396 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
397 }
398 }
399
400 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
401 {
402 struct sil24_port_priv *pp = ap->private_data;
403 *tf = pp->tf;
404 }
405
406 static void sil24_phy_reset(struct ata_port *ap)
407 {
408 __sata_phy_reset(ap);
409 /*
410 * No ATAPI yet. Just unconditionally indicate ATA device.
411 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
412 * and libata core will ignore the device.
413 */
414 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
415 ap->device[0].class = ATA_DEV_ATA;
416 }
417
418 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
419 struct sil24_cmd_block *cb)
420 {
421 struct scatterlist *sg = qc->sg;
422 struct sil24_sge *sge = cb->sge;
423 unsigned i;
424
425 for (i = 0; i < qc->n_elem; i++, sg++, sge++) {
426 sge->addr = cpu_to_le64(sg_dma_address(sg));
427 sge->cnt = cpu_to_le32(sg_dma_len(sg));
428 sge->flags = 0;
429 sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM);
430 }
431 }
432
433 static void sil24_qc_prep(struct ata_queued_cmd *qc)
434 {
435 struct ata_port *ap = qc->ap;
436 struct sil24_port_priv *pp = ap->private_data;
437 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
438 struct sil24_prb *prb = &cb->prb;
439
440 switch (qc->tf.protocol) {
441 case ATA_PROT_PIO:
442 case ATA_PROT_DMA:
443 case ATA_PROT_NODATA:
444 break;
445 default:
446 /* ATAPI isn't supported yet */
447 BUG();
448 }
449
450 ata_tf_to_fis(&qc->tf, prb->fis, 0);
451
452 if (qc->flags & ATA_QCFLAG_DMAMAP)
453 sil24_fill_sg(qc, cb);
454 }
455
456 static int sil24_qc_issue(struct ata_queued_cmd *qc)
457 {
458 struct ata_port *ap = qc->ap;
459 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
460 struct sil24_port_priv *pp = ap->private_data;
461 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
462
463 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
464 return 0;
465 }
466
467 static void sil24_irq_clear(struct ata_port *ap)
468 {
469 /* unused */
470 }
471
472 static int __sil24_reset_controller(void __iomem *port)
473 {
474 int cnt;
475 u32 tmp;
476
477 /* Reset controller state. Is this correct? */
478 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
479 readl(port + PORT_CTRL_STAT); /* sync */
480
481 /* Max ~100ms */
482 for (cnt = 0; cnt < 1000; cnt++) {
483 udelay(100);
484 tmp = readl(port + PORT_CTRL_STAT);
485 if (!(tmp & PORT_CS_DEV_RST))
486 break;
487 }
488
489 if (tmp & PORT_CS_DEV_RST)
490 return -1;
491 return 0;
492 }
493
494 static void sil24_reset_controller(struct ata_port *ap)
495 {
496 printk(KERN_NOTICE DRV_NAME
497 " ata%u: resetting controller...\n", ap->id);
498 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
499 printk(KERN_ERR DRV_NAME
500 " ata%u: failed to reset controller\n", ap->id);
501 }
502
503 static void sil24_eng_timeout(struct ata_port *ap)
504 {
505 struct ata_queued_cmd *qc;
506
507 qc = ata_qc_from_tag(ap, ap->active_tag);
508 if (!qc) {
509 printk(KERN_ERR "ata%u: BUG: tiemout without command\n",
510 ap->id);
511 return;
512 }
513
514 /*
515 * hack alert! We cannot use the supplied completion
516 * function from inside the ->eh_strategy_handler() thread.
517 * libata is the only user of ->eh_strategy_handler() in
518 * any kernel, so the default scsi_done() assumes it is
519 * not being called from the SCSI EH.
520 */
521 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
522 qc->scsidone = scsi_finish_command;
523 ata_qc_complete(qc, ATA_ERR);
524
525 sil24_reset_controller(ap);
526 }
527
528 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
529 {
530 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
531 struct sil24_port_priv *pp = ap->private_data;
532 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
533 u32 irq_stat, cmd_err, sstatus, serror;
534
535 irq_stat = readl(port + PORT_IRQ_STAT);
536 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
537
538 if (!(irq_stat & PORT_IRQ_ERROR)) {
539 /* ignore non-completion, non-error irqs for now */
540 printk(KERN_WARNING DRV_NAME
541 "ata%u: non-error exception irq (irq_stat %x)\n",
542 ap->id, irq_stat);
543 return;
544 }
545
546 cmd_err = readl(port + PORT_CMD_ERR);
547 sstatus = readl(port + PORT_SSTATUS);
548 serror = readl(port + PORT_SERROR);
549 if (serror)
550 writel(serror, port + PORT_SERROR);
551
552 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
553 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
554 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
555
556 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
557 /*
558 * Device is reporting error, tf registers are valid.
559 */
560 sil24_update_tf(ap);
561 } else {
562 /*
563 * Other errors. libata currently doesn't have any
564 * mechanism to report these errors. Just turn on
565 * ATA_ERR.
566 */
567 pp->tf.command = ATA_ERR;
568 }
569
570 if (qc)
571 ata_qc_complete(qc, pp->tf.command);
572
573 sil24_reset_controller(ap);
574 }
575
576 static inline void sil24_host_intr(struct ata_port *ap)
577 {
578 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
579 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
580 u32 slot_stat;
581
582 slot_stat = readl(port + PORT_SLOT_STAT);
583 if (!(slot_stat & HOST_SSTAT_ATTN)) {
584 struct sil24_port_priv *pp = ap->private_data;
585 /*
586 * !HOST_SSAT_ATTN guarantees successful completion,
587 * so reading back tf registers is unnecessary for
588 * most commands. TODO: read tf registers for
589 * commands which require these values on successful
590 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
591 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
592 */
593 sil24_update_tf(ap);
594
595 if (qc)
596 ata_qc_complete(qc, pp->tf.command);
597 } else
598 sil24_error_intr(ap, slot_stat);
599 }
600
601 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
602 {
603 struct ata_host_set *host_set = dev_instance;
604 struct sil24_host_priv *hpriv = host_set->private_data;
605 unsigned handled = 0;
606 u32 status;
607 int i;
608
609 status = readl(hpriv->host_base + HOST_IRQ_STAT);
610
611 if (status == 0xffffffff) {
612 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
613 "PCI fault or device removal?\n");
614 goto out;
615 }
616
617 if (!(status & IRQ_STAT_4PORTS))
618 goto out;
619
620 spin_lock(&host_set->lock);
621
622 for (i = 0; i < host_set->n_ports; i++)
623 if (status & (1 << i)) {
624 struct ata_port *ap = host_set->ports[i];
625 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
626 sil24_host_intr(host_set->ports[i]);
627 handled++;
628 } else
629 printk(KERN_ERR DRV_NAME
630 ": interrupt from disabled port %d\n", i);
631 }
632
633 spin_unlock(&host_set->lock);
634 out:
635 return IRQ_RETVAL(handled);
636 }
637
638 static int sil24_port_start(struct ata_port *ap)
639 {
640 struct device *dev = ap->host_set->dev;
641 struct sil24_port_priv *pp;
642 struct sil24_cmd_block *cb;
643 size_t cb_size = sizeof(*cb);
644 dma_addr_t cb_dma;
645
646 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
647 if (!pp)
648 return -ENOMEM;
649 memset(pp, 0, sizeof(*pp));
650
651 pp->tf.command = ATA_DRDY;
652
653 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
654 if (!cb) {
655 kfree(pp);
656 return -ENOMEM;
657 }
658 memset(cb, 0, cb_size);
659
660 pp->cmd_block = cb;
661 pp->cmd_block_dma = cb_dma;
662
663 ap->private_data = pp;
664
665 return 0;
666 }
667
668 static void sil24_port_stop(struct ata_port *ap)
669 {
670 struct device *dev = ap->host_set->dev;
671 struct sil24_port_priv *pp = ap->private_data;
672 size_t cb_size = sizeof(*pp->cmd_block);
673
674 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
675 kfree(pp);
676 }
677
678 static void sil24_host_stop(struct ata_host_set *host_set)
679 {
680 struct sil24_host_priv *hpriv = host_set->private_data;
681
682 iounmap(hpriv->host_base);
683 iounmap(hpriv->port_base);
684 kfree(hpriv);
685 }
686
687 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
688 {
689 static int printed_version = 0;
690 unsigned int board_id = (unsigned int)ent->driver_data;
691 struct ata_port_info *pinfo = &sil24_port_info[board_id];
692 struct ata_probe_ent *probe_ent = NULL;
693 struct sil24_host_priv *hpriv = NULL;
694 void __iomem *host_base = NULL;
695 void __iomem *port_base = NULL;
696 int i, rc;
697
698 if (!printed_version++)
699 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
700
701 rc = pci_enable_device(pdev);
702 if (rc)
703 return rc;
704
705 rc = pci_request_regions(pdev, DRV_NAME);
706 if (rc)
707 goto out_disable;
708
709 rc = -ENOMEM;
710 /* ioremap mmio registers */
711 host_base = ioremap(pci_resource_start(pdev, 0),
712 pci_resource_len(pdev, 0));
713 if (!host_base)
714 goto out_free;
715 port_base = ioremap(pci_resource_start(pdev, 2),
716 pci_resource_len(pdev, 2));
717 if (!port_base)
718 goto out_free;
719
720 /* allocate & init probe_ent and hpriv */
721 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
722 if (!probe_ent)
723 goto out_free;
724
725 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
726 if (!hpriv)
727 goto out_free;
728
729 memset(probe_ent, 0, sizeof(*probe_ent));
730 probe_ent->dev = pci_dev_to_dev(pdev);
731 INIT_LIST_HEAD(&probe_ent->node);
732
733 probe_ent->sht = pinfo->sht;
734 probe_ent->host_flags = pinfo->host_flags;
735 probe_ent->pio_mask = pinfo->pio_mask;
736 probe_ent->udma_mask = pinfo->udma_mask;
737 probe_ent->port_ops = pinfo->port_ops;
738 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
739
740 probe_ent->irq = pdev->irq;
741 probe_ent->irq_flags = SA_SHIRQ;
742 probe_ent->mmio_base = port_base;
743 probe_ent->private_data = hpriv;
744
745 memset(hpriv, 0, sizeof(*hpriv));
746 hpriv->host_base = host_base;
747 hpriv->port_base = port_base;
748
749 /*
750 * Configure the device
751 */
752 /*
753 * FIXME: This device is certainly 64-bit capable. We just
754 * don't know how to use it. After fixing 32bit activation in
755 * this function, enable 64bit masks here.
756 */
757 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
758 if (rc) {
759 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
760 pci_name(pdev));
761 goto out_free;
762 }
763 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
764 if (rc) {
765 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
766 pci_name(pdev));
767 goto out_free;
768 }
769
770 /* GPIO off */
771 writel(0, host_base + HOST_FLASH_CMD);
772
773 /* Mask interrupts during initialization */
774 writel(0, host_base + HOST_CTRL);
775
776 for (i = 0; i < probe_ent->n_ports; i++) {
777 void __iomem *port = port_base + i * PORT_REGS_SIZE;
778 unsigned long portu = (unsigned long)port;
779 u32 tmp;
780 int cnt;
781
782 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
783 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
784
785 ata_std_ports(&probe_ent->port[i]);
786
787 /* Initial PHY setting */
788 writel(0x20c, port + PORT_PHY_CFG);
789
790 /* Clear port RST */
791 tmp = readl(port + PORT_CTRL_STAT);
792 if (tmp & PORT_CS_PORT_RST) {
793 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
794 readl(port + PORT_CTRL_STAT); /* sync */
795 for (cnt = 0; cnt < 10; cnt++) {
796 msleep(10);
797 tmp = readl(port + PORT_CTRL_STAT);
798 if (!(tmp & PORT_CS_PORT_RST))
799 break;
800 }
801 if (tmp & PORT_CS_PORT_RST)
802 printk(KERN_ERR DRV_NAME
803 "(%s): failed to clear port RST\n",
804 pci_name(pdev));
805 }
806
807 /* Zero error counters. */
808 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
809 writel(0x8000, port + PORT_CRC_ERR_THRESH);
810 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
811 writel(0x0000, port + PORT_DECODE_ERR_CNT);
812 writel(0x0000, port + PORT_CRC_ERR_CNT);
813 writel(0x0000, port + PORT_HSHK_ERR_CNT);
814
815 /* FIXME: 32bit activation? */
816 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
817 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
818
819 /* Configure interrupts */
820 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
821 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
822 port + PORT_IRQ_ENABLE_SET);
823
824 /* Clear interrupts */
825 writel(0x0fff0fff, port + PORT_IRQ_STAT);
826 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
827
828 /* Clear port multiplier enable and resume bits */
829 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
830
831 /* Reset itself */
832 if (__sil24_reset_controller(port))
833 printk(KERN_ERR DRV_NAME
834 "(%s): failed to reset controller\n",
835 pci_name(pdev));
836 }
837
838 /* Turn on interrupts */
839 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
840
841 pci_set_master(pdev);
842
843 /* FIXME: check ata_device_add return value */
844 ata_device_add(probe_ent);
845
846 kfree(probe_ent);
847 return 0;
848
849 out_free:
850 if (host_base)
851 iounmap(host_base);
852 if (port_base)
853 iounmap(port_base);
854 kfree(probe_ent);
855 kfree(hpriv);
856 pci_release_regions(pdev);
857 out_disable:
858 pci_disable_device(pdev);
859 return rc;
860 }
861
862 static int __init sil24_init(void)
863 {
864 return pci_module_init(&sil24_pci_driver);
865 }
866
867 static void __exit sil24_exit(void)
868 {
869 pci_unregister_driver(&sil24_pci_driver);
870 }
871
872 MODULE_AUTHOR("Tejun Heo");
873 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
874 MODULE_LICENSE("GPL");
875 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
876
877 module_init(sil24_init);
878 module_exit(sil24_exit);
Linux kernel - Deliverables
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