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976a6b124af94f7173629f12b9eff70992379098
[deliverable/linux.git] / drivers / scsi / sata_vsc.c
1 /*
2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3 *
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 SGI
9 *
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
11 *
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * libata documentation is available via 'make {ps|pdf}docs',
29 * as Documentation/DocBook/libata.*
30 *
31 * Vitesse hardware documentation presumably available under NDA.
32 * Intel 31244 (same hardware interface) documentation presumably
33 * available from http://developer.intel.com/
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "sata_vsc"
50 #define DRV_VERSION "1.1"
51
52 /* Interrupt register offsets (from chip base address) */
53 #define VSC_SATA_INT_STAT_OFFSET 0x00
54 #define VSC_SATA_INT_MASK_OFFSET 0x04
55
56 /* Taskfile registers offsets */
57 #define VSC_SATA_TF_CMD_OFFSET 0x00
58 #define VSC_SATA_TF_DATA_OFFSET 0x00
59 #define VSC_SATA_TF_ERROR_OFFSET 0x04
60 #define VSC_SATA_TF_FEATURE_OFFSET 0x06
61 #define VSC_SATA_TF_NSECT_OFFSET 0x08
62 #define VSC_SATA_TF_LBAL_OFFSET 0x0c
63 #define VSC_SATA_TF_LBAM_OFFSET 0x10
64 #define VSC_SATA_TF_LBAH_OFFSET 0x14
65 #define VSC_SATA_TF_DEVICE_OFFSET 0x18
66 #define VSC_SATA_TF_STATUS_OFFSET 0x1c
67 #define VSC_SATA_TF_COMMAND_OFFSET 0x1d
68 #define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
69 #define VSC_SATA_TF_CTL_OFFSET 0x29
70
71 /* DMA base */
72 #define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
73 #define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
74 #define VSC_SATA_DMA_CMD_OFFSET 0x70
75
76 /* SCRs base */
77 #define VSC_SATA_SCR_STATUS_OFFSET 0x100
78 #define VSC_SATA_SCR_ERROR_OFFSET 0x104
79 #define VSC_SATA_SCR_CONTROL_OFFSET 0x108
80
81 /* Port stride */
82 #define VSC_SATA_PORT_OFFSET 0x200
83
84
85 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
86 {
87 if (sc_reg > SCR_CONTROL)
88 return 0xffffffffU;
89 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
90 }
91
92
93 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
94 u32 val)
95 {
96 if (sc_reg > SCR_CONTROL)
97 return;
98 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
99 }
100
101
102 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
103 {
104 void __iomem *mask_addr;
105 u8 mask;
106
107 mask_addr = ap->host_set->mmio_base +
108 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
109 mask = readb(mask_addr);
110 if (ctl & ATA_NIEN)
111 mask |= 0x80;
112 else
113 mask &= 0x7F;
114 writeb(mask, mask_addr);
115 }
116
117
118 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
119 {
120 struct ata_ioports *ioaddr = &ap->ioaddr;
121 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
122
123 /*
124 * The only thing the ctl register is used for is SRST.
125 * That is not enabled or disabled via tf_load.
126 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
127 */
128 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
129 ap->last_ctl = tf->ctl;
130 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
131 }
132 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
133 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
134 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
135 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
136 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
137 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
138 } else if (is_addr) {
139 writew(tf->feature, ioaddr->feature_addr);
140 writew(tf->nsect, ioaddr->nsect_addr);
141 writew(tf->lbal, ioaddr->lbal_addr);
142 writew(tf->lbam, ioaddr->lbam_addr);
143 writew(tf->lbah, ioaddr->lbah_addr);
144 }
145
146 if (tf->flags & ATA_TFLAG_DEVICE)
147 writeb(tf->device, ioaddr->device_addr);
148
149 ata_wait_idle(ap);
150 }
151
152
153 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
154 {
155 struct ata_ioports *ioaddr = &ap->ioaddr;
156 u16 nsect, lbal, lbam, lbah, feature;
157
158 tf->command = ata_check_status(ap);
159 tf->device = readw(ioaddr->device_addr);
160 feature = readw(ioaddr->error_addr);
161 nsect = readw(ioaddr->nsect_addr);
162 lbal = readw(ioaddr->lbal_addr);
163 lbam = readw(ioaddr->lbam_addr);
164 lbah = readw(ioaddr->lbah_addr);
165
166 tf->feature = feature;
167 tf->nsect = nsect;
168 tf->lbal = lbal;
169 tf->lbam = lbam;
170 tf->lbah = lbah;
171
172 if (tf->flags & ATA_TFLAG_LBA48) {
173 tf->hob_feature = feature >> 8;
174 tf->hob_nsect = nsect >> 8;
175 tf->hob_lbal = lbal >> 8;
176 tf->hob_lbam = lbam >> 8;
177 tf->hob_lbah = lbah >> 8;
178 }
179 }
180
181
182 /*
183 * vsc_sata_interrupt
184 *
185 * Read the interrupt register and process for the devices that have them pending.
186 */
187 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
188 struct pt_regs *regs)
189 {
190 struct ata_host_set *host_set = dev_instance;
191 unsigned int i;
192 unsigned int handled = 0;
193 u32 int_status;
194
195 spin_lock(&host_set->lock);
196
197 int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
198
199 for (i = 0; i < host_set->n_ports; i++) {
200 if (int_status & ((u32) 0xFF << (8 * i))) {
201 struct ata_port *ap;
202
203 ap = host_set->ports[i];
204 if (ap &&
205 !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
206 struct ata_queued_cmd *qc;
207
208 qc = ata_qc_from_tag(ap, ap->active_tag);
209 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
210 handled += ata_host_intr(ap, qc);
211 }
212 }
213 }
214
215 spin_unlock(&host_set->lock);
216
217 return IRQ_RETVAL(handled);
218 }
219
220
221 static struct scsi_host_template vsc_sata_sht = {
222 .module = THIS_MODULE,
223 .name = DRV_NAME,
224 .ioctl = ata_scsi_ioctl,
225 .queuecommand = ata_scsi_queuecmd,
226 .eh_timed_out = ata_scsi_timed_out,
227 .eh_strategy_handler = ata_scsi_error,
228 .can_queue = ATA_DEF_QUEUE,
229 .this_id = ATA_SHT_THIS_ID,
230 .sg_tablesize = LIBATA_MAX_PRD,
231 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
232 .emulated = ATA_SHT_EMULATED,
233 .use_clustering = ATA_SHT_USE_CLUSTERING,
234 .proc_name = DRV_NAME,
235 .dma_boundary = ATA_DMA_BOUNDARY,
236 .slave_configure = ata_scsi_slave_config,
237 .bios_param = ata_std_bios_param,
238 };
239
240
241 static const struct ata_port_operations vsc_sata_ops = {
242 .port_disable = ata_port_disable,
243 .tf_load = vsc_sata_tf_load,
244 .tf_read = vsc_sata_tf_read,
245 .exec_command = ata_exec_command,
246 .check_status = ata_check_status,
247 .dev_select = ata_std_dev_select,
248 .phy_reset = sata_phy_reset,
249 .bmdma_setup = ata_bmdma_setup,
250 .bmdma_start = ata_bmdma_start,
251 .bmdma_stop = ata_bmdma_stop,
252 .bmdma_status = ata_bmdma_status,
253 .qc_prep = ata_qc_prep,
254 .qc_issue = ata_qc_issue_prot,
255 .eng_timeout = ata_eng_timeout,
256 .irq_handler = vsc_sata_interrupt,
257 .irq_clear = ata_bmdma_irq_clear,
258 .scr_read = vsc_sata_scr_read,
259 .scr_write = vsc_sata_scr_write,
260 .port_start = ata_port_start,
261 .port_stop = ata_port_stop,
262 .host_stop = ata_pci_host_stop,
263 };
264
265 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
266 {
267 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
268 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
269 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
270 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
271 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
272 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
273 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
274 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
275 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
276 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
277 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
278 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
279 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
280 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
281 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
282 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
283 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
284 }
285
286
287 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
288 {
289 static int printed_version;
290 struct ata_probe_ent *probe_ent = NULL;
291 unsigned long base;
292 int pci_dev_busy = 0;
293 void __iomem *mmio_base;
294 int rc;
295
296 if (!printed_version++)
297 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
298
299 rc = pci_enable_device(pdev);
300 if (rc)
301 return rc;
302
303 /*
304 * Check if we have needed resource mapped.
305 */
306 if (pci_resource_len(pdev, 0) == 0) {
307 rc = -ENODEV;
308 goto err_out;
309 }
310
311 rc = pci_request_regions(pdev, DRV_NAME);
312 if (rc) {
313 pci_dev_busy = 1;
314 goto err_out;
315 }
316
317 /*
318 * Use 32 bit DMA mask, because 64 bit address support is poor.
319 */
320 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
321 if (rc)
322 goto err_out_regions;
323 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
324 if (rc)
325 goto err_out_regions;
326
327 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
328 if (probe_ent == NULL) {
329 rc = -ENOMEM;
330 goto err_out_regions;
331 }
332 memset(probe_ent, 0, sizeof(*probe_ent));
333 probe_ent->dev = pci_dev_to_dev(pdev);
334 INIT_LIST_HEAD(&probe_ent->node);
335
336 mmio_base = pci_iomap(pdev, 0, 0);
337 if (mmio_base == NULL) {
338 rc = -ENOMEM;
339 goto err_out_free_ent;
340 }
341 base = (unsigned long) mmio_base;
342
343 /*
344 * Due to a bug in the chip, the default cache line size can't be used
345 */
346 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
347
348 probe_ent->sht = &vsc_sata_sht;
349 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
350 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
351 probe_ent->port_ops = &vsc_sata_ops;
352 probe_ent->n_ports = 4;
353 probe_ent->irq = pdev->irq;
354 probe_ent->irq_flags = SA_SHIRQ;
355 probe_ent->mmio_base = mmio_base;
356
357 /* We don't care much about the PIO/UDMA masks, but the core won't like us
358 * if we don't fill these
359 */
360 probe_ent->pio_mask = 0x1f;
361 probe_ent->mwdma_mask = 0x07;
362 probe_ent->udma_mask = 0x7f;
363
364 /* We have 4 ports per PCI function */
365 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
366 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
367 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
368 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
369
370 pci_set_master(pdev);
371
372 /*
373 * Config offset 0x98 is "Extended Control and Status Register 0"
374 * Default value is (1 << 28). All bits except bit 28 are reserved in
375 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
376 * If bit 28 is clear, each port has its own LED.
377 */
378 pci_write_config_dword(pdev, 0x98, 0);
379
380 /* FIXME: check ata_device_add return value */
381 ata_device_add(probe_ent);
382 kfree(probe_ent);
383
384 return 0;
385
386 err_out_free_ent:
387 kfree(probe_ent);
388 err_out_regions:
389 pci_release_regions(pdev);
390 err_out:
391 if (!pci_dev_busy)
392 pci_disable_device(pdev);
393 return rc;
394 }
395
396
397 /*
398 * 0x1725/0x7174 is the Vitesse VSC-7174
399 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
400 * compatibility is untested as of yet
401 */
402 static const struct pci_device_id vsc_sata_pci_tbl[] = {
403 { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
404 { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
405 { }
406 };
407
408
409 static struct pci_driver vsc_sata_pci_driver = {
410 .name = DRV_NAME,
411 .id_table = vsc_sata_pci_tbl,
412 .probe = vsc_sata_init_one,
413 .remove = ata_pci_remove_one,
414 };
415
416
417 static int __init vsc_sata_init(void)
418 {
419 return pci_module_init(&vsc_sata_pci_driver);
420 }
421
422
423 static void __exit vsc_sata_exit(void)
424 {
425 pci_unregister_driver(&vsc_sata_pci_driver);
426 }
427
428
429 MODULE_AUTHOR("Jeremy Higdon");
430 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
431 MODULE_LICENSE("GPL");
432 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
433 MODULE_VERSION(DRV_VERSION);
434
435 module_init(vsc_sata_init);
436 module_exit(vsc_sata_exit);
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