2 * File: linux/drivers/serial/bfin_sport_uart.h
4 * Based on: include/asm-blackfin/mach-533/bfin_serial_5xx.h
5 * Author: Roy Huang <roy.huang>analog.com>
7 * Created: Nov 22, 2006
8 * Copyright: (C) Analog Device Inc.
9 * Description: this driver enable SPORTs on Blackfin emulate UART.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see the file COPYING, or write
23 * to the Free Software Foundation, Inc.,
24 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
29 #define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
30 #define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
31 #define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
32 #define OFFSET_TX 0x10 /* Transmit Data Register */
33 #define OFFSET_RX 0x18 /* Receive Data Register */
34 #define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
35 #define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
36 #define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
37 #define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
38 #define OFFSET_STAT 0x30 /* Status Register */
40 #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
41 #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
42 #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
43 #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
44 #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
45 #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
46 #define SPORT_GET_RX32(sport) bfin_read32(((sport)->port.membase + OFFSET_RX))
47 #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
48 #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
49 #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
50 #define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
51 #define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
53 #define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
54 #define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
55 #define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
56 #define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
57 #define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
58 #define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
59 #define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
60 #define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
61 #define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
62 #define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
63 #define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
This page took 0.032779 seconds and 6 git commands to generate.