2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
51 #include <asm/clock.h>
52 #include <asm/sh_bios.h>
59 struct uart_port port
;
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs
[SCIx_NR_IRQS
];
67 /* Port pin configuration */
68 void (*init_pins
)(struct uart_port
*port
,
71 /* Port enable callback */
72 void (*enable
)(struct uart_port
*port
);
74 /* Port disable callback */
75 void (*disable
)(struct uart_port
*port
);
78 struct timer_list break_timer
;
88 static struct sci_port
*kgdb_sci_port
;
91 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
92 static struct sci_port
*serial_console_port
;
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port
*port
);
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
100 static struct sci_port sci_ports
[SCI_NPORTS
];
101 static struct uart_driver sci_uart_driver
;
103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
104 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
105 static inline void handle_error(struct uart_port
*port
)
107 /* Clear error flags */
108 sci_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
111 static int get_char(struct uart_port
*port
)
114 unsigned short status
;
117 spin_lock_irqsave(&port
->lock
, flags
);
119 status
= sci_in(port
, SCxSR
);
120 if (status
& SCxSR_ERRORS(port
)) {
124 } while (!(status
& SCxSR_RDxF(port
)));
125 c
= sci_in(port
, SCxRDR
);
126 sci_in(port
, SCxSR
); /* Dummy read */
127 sci_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
128 spin_unlock_irqrestore(&port
->lock
, flags
);
132 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
134 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
135 static void put_char(struct uart_port
*port
, char c
)
138 unsigned short status
;
140 spin_lock_irqsave(&port
->lock
, flags
);
143 status
= sci_in(port
, SCxSR
);
144 } while (!(status
& SCxSR_TDxE(port
)));
146 sci_out(port
, SCxTDR
, c
);
147 sci_in(port
, SCxSR
); /* Dummy read */
148 sci_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
150 spin_unlock_irqrestore(&port
->lock
, flags
);
154 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
155 static void put_string(struct sci_port
*sci_port
, const char *buffer
, int count
)
157 struct uart_port
*port
= &sci_port
->port
;
158 const unsigned char *p
= buffer
;
161 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
165 #ifdef CONFIG_SH_STANDARD_BIOS
166 /* This call only does a trap the first time it is
167 * called, and so is safe to do here unconditionally
169 usegdb
|= sh_bios_in_gdb_mode();
171 #ifdef CONFIG_SH_KGDB
172 usegdb
|= (kgdb_in_gdb_mode
&& (sci_port
== kgdb_sci_port
));
176 /* $<packet info>#<checksum>. */
180 put_char(port
, 'O'); /* 'O'utput to console */
183 for (i
=0; i
<count
; i
++) { /* Don't use run length encoding */
194 put_char(port
, hex_asc_hi(checksum
));
195 put_char(port
, hex_asc_lo(checksum
));
196 } while (get_char(port
) != '+');
198 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
199 for (i
=0; i
<count
; i
++) {
201 put_char(port
, '\r');
202 put_char(port
, *p
++);
205 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
207 #ifdef CONFIG_SH_KGDB
208 static int kgdb_sci_getchar(void)
212 /* Keep trying to read a character, this could be neater */
213 while ((c
= get_char(&kgdb_sci_port
->port
)) < 0)
219 static inline void kgdb_sci_putchar(int c
)
221 put_char(&kgdb_sci_port
->port
, c
);
223 #endif /* CONFIG_SH_KGDB */
225 #if defined(__H8300S__)
226 enum { sci_disable
, sci_enable
};
228 static void h8300_sci_config(struct uart_port
* port
, unsigned int ctrl
)
230 volatile unsigned char *mstpcrl
=(volatile unsigned char *)MSTPCRL
;
231 int ch
= (port
->mapbase
- SMR0
) >> 3;
232 unsigned char mask
= 1 << (ch
+1);
234 if (ctrl
== sci_disable
) {
241 static inline void h8300_sci_enable(struct uart_port
*port
)
243 h8300_sci_config(port
, sci_enable
);
246 static inline void h8300_sci_disable(struct uart_port
*port
)
248 h8300_sci_config(port
, sci_disable
);
252 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
253 defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port
* port
, unsigned int cflag
)
256 int ch
= (port
->mapbase
- SMR0
) >> 3;
259 H8300_GPIO_DDR(h8300_sci_pins
[ch
].port
,
260 h8300_sci_pins
[ch
].rx
,
262 H8300_GPIO_DDR(h8300_sci_pins
[ch
].port
,
263 h8300_sci_pins
[ch
].tx
,
267 H8300_SCI_DR(ch
) |= h8300_sci_pins
[ch
].tx
;
270 #define sci_init_pins_sci NULL
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port
*port
, unsigned int cflag
)
276 unsigned int fcr_val
= 0;
279 fcr_val
|= SCFCR_MCE
;
281 sci_out(port
, SCFCR
, fcr_val
);
284 #define sci_init_pins_irda NULL
288 #define sci_init_pins_scif NULL
291 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
293 static void sci_init_pins_scif(struct uart_port
* port
, unsigned int cflag
)
295 unsigned int fcr_val
= 0;
297 set_sh771x_scif_pfc(port
);
298 if (cflag
& CRTSCTS
) {
299 fcr_val
|= SCFCR_MCE
;
301 sci_out(port
, SCFCR
, fcr_val
);
303 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
304 static void sci_init_pins_scif(struct uart_port
*port
, unsigned int cflag
)
306 unsigned int fcr_val
= 0;
309 if (cflag
& CRTSCTS
) {
311 if (port
->mapbase
== 0xa4430000) { /* SCIF0 */
312 /* Clear PTCR bit 9-2; enable all scif pins but sck */
313 data
= ctrl_inw(PORT_PTCR
);
314 ctrl_outw((data
& 0xfc03), PORT_PTCR
);
315 } else if (port
->mapbase
== 0xa4438000) { /* SCIF1 */
316 /* Clear PVCR bit 9-2 */
317 data
= ctrl_inw(PORT_PVCR
);
318 ctrl_outw((data
& 0xfc03), PORT_PVCR
);
320 fcr_val
|= SCFCR_MCE
;
322 if (port
->mapbase
== 0xa4430000) { /* SCIF0 */
323 /* Clear PTCR bit 5-2; enable only tx and rx */
324 data
= ctrl_inw(PORT_PTCR
);
325 ctrl_outw((data
& 0xffc3), PORT_PTCR
);
326 } else if (port
->mapbase
== 0xa4438000) { /* SCIF1 */
327 /* Clear PVCR bit 5-2 */
328 data
= ctrl_inw(PORT_PVCR
);
329 ctrl_outw((data
& 0xffc3), PORT_PVCR
);
332 sci_out(port
, SCFCR
, fcr_val
);
334 #elif defined(CONFIG_CPU_SH3)
335 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
336 static void sci_init_pins_scif(struct uart_port
*port
, unsigned int cflag
)
338 unsigned int fcr_val
= 0;
341 /* We need to set SCPCR to enable RTS/CTS */
342 data
= ctrl_inw(SCPCR
);
343 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
344 ctrl_outw(data
& 0x0fcf, SCPCR
);
347 fcr_val
|= SCFCR_MCE
;
349 /* We need to set SCPCR to enable RTS/CTS */
350 data
= ctrl_inw(SCPCR
);
351 /* Clear out SCP7MD1,0, SCP4MD1,0,
352 Set SCP6MD1,0 = {01} (output) */
353 ctrl_outw((data
& 0x0fcf) | 0x1000, SCPCR
);
355 data
= ctrl_inb(SCPDR
);
356 /* Set /RTS2 (bit6) = 0 */
357 ctrl_outb(data
& 0xbf, SCPDR
);
360 sci_out(port
, SCFCR
, fcr_val
);
362 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
363 static void sci_init_pins_scif(struct uart_port
*port
, unsigned int cflag
)
365 unsigned int fcr_val
= 0;
368 if (port
->mapbase
== 0xffe00000) {
369 data
= ctrl_inw(PSCR
);
372 fcr_val
|= SCFCR_MCE
;
376 ctrl_outw(data
, PSCR
);
378 /* SCIF1 and SCIF2 should be setup by board code */
380 sci_out(port
, SCFCR
, fcr_val
);
382 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
383 static void sci_init_pins_scif(struct uart_port
*port
, unsigned int cflag
)
385 /* Nothing to do here.. */
386 sci_out(port
, SCFCR
, 0);
390 static void sci_init_pins_scif(struct uart_port
*port
, unsigned int cflag
)
392 unsigned int fcr_val
= 0;
394 if (cflag
& CRTSCTS
) {
395 fcr_val
|= SCFCR_MCE
;
397 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
399 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
400 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
401 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
402 defined(CONFIG_CPU_SUBTYPE_SHX3)
403 ctrl_outw(0x0080, SCSPTR0
); /* Set RTS = 1 */
405 ctrl_outw(0x0080, SCSPTR2
); /* Set RTS = 1 */
408 sci_out(port
, SCFCR
, fcr_val
);
412 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
414 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7785)
416 static inline int scif_txroom(struct uart_port
*port
)
418 return SCIF_TXROOM_MAX
- (sci_in(port
, SCTFDR
) & 0xff);
421 static inline int scif_rxroom(struct uart_port
*port
)
423 return sci_in(port
, SCRFDR
) & 0xff;
426 static inline int scif_txroom(struct uart_port
*port
)
428 return SCIF_TXROOM_MAX
- (sci_in(port
, SCFDR
) >> 8);
431 static inline int scif_rxroom(struct uart_port
*port
)
433 return sci_in(port
, SCFDR
) & SCIF_RFDC_MASK
;
436 #endif /* SCIF_ONLY || SCI_AND_SCIF */
438 static inline int sci_txroom(struct uart_port
*port
)
440 return ((sci_in(port
, SCxSR
) & SCI_TDRE
) != 0);
443 static inline int sci_rxroom(struct uart_port
*port
)
445 return ((sci_in(port
, SCxSR
) & SCxSR_RDxF(port
)) != 0);
448 /* ********************************************************************** *
449 * the interrupt related routines *
450 * ********************************************************************** */
452 static void sci_transmit_chars(struct uart_port
*port
)
454 struct circ_buf
*xmit
= &port
->info
->xmit
;
455 unsigned int stopped
= uart_tx_stopped(port
);
456 unsigned short status
;
460 status
= sci_in(port
, SCxSR
);
461 if (!(status
& SCxSR_TDxE(port
))) {
462 ctrl
= sci_in(port
, SCSCR
);
463 if (uart_circ_empty(xmit
)) {
464 ctrl
&= ~SCI_CTRL_FLAGS_TIE
;
466 ctrl
|= SCI_CTRL_FLAGS_TIE
;
468 sci_out(port
, SCSCR
, ctrl
);
473 if (port
->type
== PORT_SCIF
)
474 count
= scif_txroom(port
);
477 count
= sci_txroom(port
);
485 } else if (!uart_circ_empty(xmit
) && !stopped
) {
486 c
= xmit
->buf
[xmit
->tail
];
487 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
492 sci_out(port
, SCxTDR
, c
);
495 } while (--count
> 0);
497 sci_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
499 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
500 uart_write_wakeup(port
);
501 if (uart_circ_empty(xmit
)) {
504 ctrl
= sci_in(port
, SCSCR
);
506 #if !defined(SCI_ONLY)
507 if (port
->type
== PORT_SCIF
) {
508 sci_in(port
, SCxSR
); /* Dummy read */
509 sci_out(port
, SCxSR
, SCxSR_TDxE_CLEAR(port
));
513 ctrl
|= SCI_CTRL_FLAGS_TIE
;
514 sci_out(port
, SCSCR
, ctrl
);
518 /* On SH3, SCIF may read end-of-break as a space->mark char */
519 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
521 static inline void sci_receive_chars(struct uart_port
*port
)
523 struct sci_port
*sci_port
= (struct sci_port
*)port
;
524 struct tty_struct
*tty
= port
->info
->port
.tty
;
525 int i
, count
, copied
= 0;
526 unsigned short status
;
529 status
= sci_in(port
, SCxSR
);
530 if (!(status
& SCxSR_RDxF(port
)))
534 #if !defined(SCI_ONLY)
535 if (port
->type
== PORT_SCIF
)
536 count
= scif_rxroom(port
);
539 count
= sci_rxroom(port
);
541 /* Don't copy more bytes than there is room for in the buffer */
542 count
= tty_buffer_request_room(tty
, count
);
544 /* If for any reason we can't copy more data, we're done! */
548 if (port
->type
== PORT_SCI
) {
549 char c
= sci_in(port
, SCxRDR
);
550 if (uart_handle_sysrq_char(port
, c
) || sci_port
->break_flag
)
553 tty_insert_flip_char(tty
, c
, TTY_NORMAL
);
556 for (i
=0; i
<count
; i
++) {
557 char c
= sci_in(port
, SCxRDR
);
558 status
= sci_in(port
, SCxSR
);
559 #if defined(CONFIG_CPU_SH3)
560 /* Skip "chars" during break */
561 if (sci_port
->break_flag
) {
563 (status
& SCxSR_FER(port
))) {
568 /* Nonzero => end-of-break */
569 pr_debug("scif: debounce<%02x>\n", c
);
570 sci_port
->break_flag
= 0;
577 #endif /* CONFIG_CPU_SH3 */
578 if (uart_handle_sysrq_char(port
, c
)) {
583 /* Store data and status */
584 if (status
&SCxSR_FER(port
)) {
586 pr_debug("sci: frame error\n");
587 } else if (status
&SCxSR_PER(port
)) {
589 pr_debug("sci: parity error\n");
592 tty_insert_flip_char(tty
, c
, flag
);
596 sci_in(port
, SCxSR
); /* dummy read */
597 sci_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
600 port
->icount
.rx
+= count
;
604 /* Tell the rest of the system the news. New characters! */
605 tty_flip_buffer_push(tty
);
607 sci_in(port
, SCxSR
); /* dummy read */
608 sci_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
612 #define SCI_BREAK_JIFFIES (HZ/20)
613 /* The sci generates interrupts during the break,
614 * 1 per millisecond or so during the break period, for 9600 baud.
615 * So dont bother disabling interrupts.
616 * But dont want more than 1 break event.
617 * Use a kernel timer to periodically poll the rx line until
618 * the break is finished.
620 static void sci_schedule_break_timer(struct sci_port
*port
)
622 port
->break_timer
.expires
= jiffies
+ SCI_BREAK_JIFFIES
;
623 add_timer(&port
->break_timer
);
625 /* Ensure that two consecutive samples find the break over. */
626 static void sci_break_timer(unsigned long data
)
628 struct sci_port
*port
= (struct sci_port
*)data
;
630 if (sci_rxd_in(&port
->port
) == 0) {
631 port
->break_flag
= 1;
632 sci_schedule_break_timer(port
);
633 } else if (port
->break_flag
== 1) {
635 port
->break_flag
= 2;
636 sci_schedule_break_timer(port
);
638 port
->break_flag
= 0;
641 static inline int sci_handle_errors(struct uart_port
*port
)
644 unsigned short status
= sci_in(port
, SCxSR
);
645 struct tty_struct
*tty
= port
->info
->port
.tty
;
647 if (status
& SCxSR_ORER(port
)) {
649 if (tty_insert_flip_char(tty
, 0, TTY_OVERRUN
))
651 pr_debug("sci: overrun error\n");
654 if (status
& SCxSR_FER(port
)) {
655 if (sci_rxd_in(port
) == 0) {
656 /* Notify of BREAK */
657 struct sci_port
*sci_port
= (struct sci_port
*)port
;
659 if (!sci_port
->break_flag
) {
660 sci_port
->break_flag
= 1;
661 sci_schedule_break_timer(sci_port
);
663 /* Do sysrq handling. */
664 if (uart_handle_break(port
))
666 pr_debug("sci: BREAK detected\n");
667 if (tty_insert_flip_char(tty
, 0, TTY_BREAK
))
672 if (tty_insert_flip_char(tty
, 0, TTY_FRAME
))
674 pr_debug("sci: frame error\n");
678 if (status
& SCxSR_PER(port
)) {
680 if (tty_insert_flip_char(tty
, 0, TTY_PARITY
))
682 pr_debug("sci: parity error\n");
686 tty_flip_buffer_push(tty
);
691 static inline int sci_handle_breaks(struct uart_port
*port
)
694 unsigned short status
= sci_in(port
, SCxSR
);
695 struct tty_struct
*tty
= port
->info
->port
.tty
;
696 struct sci_port
*s
= &sci_ports
[port
->line
];
698 if (uart_handle_break(port
))
701 if (!s
->break_flag
&& status
& SCxSR_BRK(port
)) {
702 #if defined(CONFIG_CPU_SH3)
706 /* Notify of BREAK */
707 if (tty_insert_flip_char(tty
, 0, TTY_BREAK
))
709 pr_debug("sci: BREAK detected\n");
712 #if defined(SCIF_ORER)
713 /* XXX: Handle SCIF overrun error */
714 if (port
->type
== PORT_SCIF
&& (sci_in(port
, SCLSR
) & SCIF_ORER
) != 0) {
715 sci_out(port
, SCLSR
, 0);
716 if (tty_insert_flip_char(tty
, 0, TTY_OVERRUN
)) {
718 pr_debug("sci: overrun error\n");
724 tty_flip_buffer_push(tty
);
729 static irqreturn_t
sci_rx_interrupt(int irq
, void *port
)
731 /* I think sci_receive_chars has to be called irrespective
732 * of whether the I_IXOFF is set, otherwise, how is the interrupt
735 sci_receive_chars(port
);
740 static irqreturn_t
sci_tx_interrupt(int irq
, void *ptr
)
742 struct uart_port
*port
= ptr
;
744 spin_lock_irq(&port
->lock
);
745 sci_transmit_chars(port
);
746 spin_unlock_irq(&port
->lock
);
751 static irqreturn_t
sci_er_interrupt(int irq
, void *ptr
)
753 struct uart_port
*port
= ptr
;
756 if (port
->type
== PORT_SCI
) {
757 if (sci_handle_errors(port
)) {
758 /* discard character in rx buffer */
760 sci_out(port
, SCxSR
, SCxSR_RDxF_CLEAR(port
));
763 #if defined(SCIF_ORER)
764 if((sci_in(port
, SCLSR
) & SCIF_ORER
) != 0) {
765 struct tty_struct
*tty
= port
->info
->port
.tty
;
767 sci_out(port
, SCLSR
, 0);
768 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
769 tty_flip_buffer_push(tty
);
770 pr_debug("scif: overrun error\n");
773 sci_rx_interrupt(irq
, ptr
);
776 sci_out(port
, SCxSR
, SCxSR_ERROR_CLEAR(port
));
778 /* Kick the transmission */
779 sci_tx_interrupt(irq
, ptr
);
784 static irqreturn_t
sci_br_interrupt(int irq
, void *ptr
)
786 struct uart_port
*port
= ptr
;
789 sci_handle_breaks(port
);
790 sci_out(port
, SCxSR
, SCxSR_BREAK_CLEAR(port
));
795 static irqreturn_t
sci_mpxed_interrupt(int irq
, void *ptr
)
797 unsigned short ssr_status
, scr_status
;
798 struct uart_port
*port
= ptr
;
800 ssr_status
= sci_in(port
,SCxSR
);
801 scr_status
= sci_in(port
,SCSCR
);
804 if ((ssr_status
& 0x0020) && (scr_status
& 0x0080))
805 sci_tx_interrupt(irq
, ptr
);
807 if ((ssr_status
& 0x0002) && (scr_status
& 0x0040))
808 sci_rx_interrupt(irq
, ptr
);
809 /* Error Interrupt */
810 if ((ssr_status
& 0x0080) && (scr_status
& 0x0400))
811 sci_er_interrupt(irq
, ptr
);
812 /* Break Interrupt */
813 if ((ssr_status
& 0x0010) && (scr_status
& 0x0200))
814 sci_br_interrupt(irq
, ptr
);
819 #ifdef CONFIG_CPU_FREQ
821 * Here we define a transistion notifier so that we can update all of our
822 * ports' baud rate when the peripheral clock changes.
824 static int sci_notifier(struct notifier_block
*self
,
825 unsigned long phase
, void *p
)
827 struct cpufreq_freqs
*freqs
= p
;
830 if ((phase
== CPUFREQ_POSTCHANGE
) ||
831 (phase
== CPUFREQ_RESUMECHANGE
)){
832 for (i
= 0; i
< SCI_NPORTS
; i
++) {
833 struct uart_port
*port
= &sci_ports
[i
].port
;
837 * Update the uartclk per-port if frequency has
838 * changed, since it will no longer necessarily be
839 * consistent with the old frequency.
841 * Really we want to be able to do something like
842 * uart_change_speed() or something along those lines
843 * here to implicitly reset the per-port baud rate..
845 * Clean this up later..
847 clk
= clk_get(NULL
, "module_clk");
848 port
->uartclk
= clk_get_rate(clk
) * 16;
852 printk(KERN_INFO
"%s: got a postchange notification "
853 "for cpu %d (old %d, new %d)\n",
854 __func__
, freqs
->cpu
, freqs
->old
, freqs
->new);
860 static struct notifier_block sci_nb
= { &sci_notifier
, NULL
, 0 };
861 #endif /* CONFIG_CPU_FREQ */
863 static int sci_request_irq(struct sci_port
*port
)
866 irqreturn_t (*handlers
[4])(int irq
, void *ptr
) = {
867 sci_er_interrupt
, sci_rx_interrupt
, sci_tx_interrupt
,
870 const char *desc
[] = { "SCI Receive Error", "SCI Receive Data Full",
871 "SCI Transmit Data Empty", "SCI Break" };
873 if (port
->irqs
[0] == port
->irqs
[1]) {
874 if (!port
->irqs
[0]) {
875 printk(KERN_ERR
"sci: Cannot allocate irq.(IRQ=0)\n");
879 if (request_irq(port
->irqs
[0], sci_mpxed_interrupt
,
880 IRQF_DISABLED
, "sci", port
)) {
881 printk(KERN_ERR
"sci: Cannot allocate irq.\n");
885 for (i
= 0; i
< ARRAY_SIZE(handlers
); i
++) {
888 if (request_irq(port
->irqs
[i
], handlers
[i
],
889 IRQF_DISABLED
, desc
[i
], port
)) {
890 printk(KERN_ERR
"sci: Cannot allocate irq.\n");
899 static void sci_free_irq(struct sci_port
*port
)
903 if (port
->irqs
[0] == port
->irqs
[1]) {
905 printk("sci: sci_free_irq error\n");
907 free_irq(port
->irqs
[0], port
);
909 for (i
= 0; i
< ARRAY_SIZE(port
->irqs
); i
++) {
913 free_irq(port
->irqs
[i
], port
);
918 static unsigned int sci_tx_empty(struct uart_port
*port
)
924 static void sci_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
926 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
927 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
928 /* If you have signals for DTR and DCD, please implement here. */
931 static unsigned int sci_get_mctrl(struct uart_port
*port
)
933 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
936 return TIOCM_DTR
| TIOCM_RTS
| TIOCM_DSR
;
939 static void sci_start_tx(struct uart_port
*port
)
943 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
944 ctrl
= sci_in(port
, SCSCR
);
945 ctrl
|= SCI_CTRL_FLAGS_TIE
;
946 sci_out(port
, SCSCR
, ctrl
);
949 static void sci_stop_tx(struct uart_port
*port
)
953 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
954 ctrl
= sci_in(port
, SCSCR
);
955 ctrl
&= ~SCI_CTRL_FLAGS_TIE
;
956 sci_out(port
, SCSCR
, ctrl
);
959 static void sci_start_rx(struct uart_port
*port
, unsigned int tty_start
)
963 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
964 ctrl
= sci_in(port
, SCSCR
);
965 ctrl
|= SCI_CTRL_FLAGS_RIE
| SCI_CTRL_FLAGS_REIE
;
966 sci_out(port
, SCSCR
, ctrl
);
969 static void sci_stop_rx(struct uart_port
*port
)
973 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
974 ctrl
= sci_in(port
, SCSCR
);
975 ctrl
&= ~(SCI_CTRL_FLAGS_RIE
| SCI_CTRL_FLAGS_REIE
);
976 sci_out(port
, SCSCR
, ctrl
);
979 static void sci_enable_ms(struct uart_port
*port
)
981 /* Nothing here yet .. */
984 static void sci_break_ctl(struct uart_port
*port
, int break_state
)
986 /* Nothing here yet .. */
989 static int sci_startup(struct uart_port
*port
)
991 struct sci_port
*s
= &sci_ports
[port
->line
];
996 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
997 s
->clk
= clk_get(NULL
, "module_clk");
1002 sci_start_rx(port
, 1);
1007 static void sci_shutdown(struct uart_port
*port
)
1009 struct sci_port
*s
= &sci_ports
[port
->line
];
1018 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1024 static void sci_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1025 struct ktermios
*old
)
1027 struct sci_port
*s
= &sci_ports
[port
->line
];
1028 unsigned int status
, baud
, smr_val
;
1031 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/16);
1039 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1040 t
= SCBRR_VALUE(baud
, clk_get_rate(s
->clk
));
1042 t
= SCBRR_VALUE(baud
);
1049 status
= sci_in(port
, SCxSR
);
1050 } while (!(status
& SCxSR_TEND(port
)));
1052 sci_out(port
, SCSCR
, 0x00); /* TE=0, RE=0, CKE1=0 */
1054 #if !defined(SCI_ONLY)
1055 if (port
->type
== PORT_SCIF
)
1056 sci_out(port
, SCFCR
, SCFCR_RFRST
| SCFCR_TFRST
);
1059 smr_val
= sci_in(port
, SCSMR
) & 3;
1060 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1062 if (termios
->c_cflag
& PARENB
)
1064 if (termios
->c_cflag
& PARODD
)
1066 if (termios
->c_cflag
& CSTOPB
)
1069 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1071 sci_out(port
, SCSMR
, smr_val
);
1075 sci_out(port
, SCSMR
, (sci_in(port
, SCSMR
) & ~3) | 1);
1078 sci_out(port
, SCSMR
, sci_in(port
, SCSMR
) & ~3);
1080 sci_out(port
, SCBRR
, t
);
1081 udelay((1000000+(baud
-1)) / baud
); /* Wait one bit interval */
1084 if (likely(s
->init_pins
))
1085 s
->init_pins(port
, termios
->c_cflag
);
1087 sci_out(port
, SCSCR
, SCSCR_INIT(port
));
1089 if ((termios
->c_cflag
& CREAD
) != 0)
1090 sci_start_rx(port
,0);
1093 static const char *sci_type(struct uart_port
*port
)
1095 switch (port
->type
) {
1096 case PORT_SCI
: return "sci";
1097 case PORT_SCIF
: return "scif";
1098 case PORT_IRDA
: return "irda";
1104 static void sci_release_port(struct uart_port
*port
)
1106 /* Nothing here yet .. */
1109 static int sci_request_port(struct uart_port
*port
)
1111 /* Nothing here yet .. */
1115 static void sci_config_port(struct uart_port
*port
, int flags
)
1117 struct sci_port
*s
= &sci_ports
[port
->line
];
1119 port
->type
= s
->type
;
1121 switch (port
->type
) {
1123 s
->init_pins
= sci_init_pins_sci
;
1126 s
->init_pins
= sci_init_pins_scif
;
1129 s
->init_pins
= sci_init_pins_irda
;
1133 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1134 if (port
->mapbase
== 0)
1135 port
->mapbase
= onchip_remap(SCIF_ADDR_SH5
, 1024, "SCIF");
1137 port
->membase
= (void __iomem
*)port
->mapbase
;
1141 static int sci_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1143 struct sci_port
*s
= &sci_ports
[port
->line
];
1145 if (ser
->irq
!= s
->irqs
[SCIx_TXI_IRQ
] || ser
->irq
> NR_IRQS
)
1147 if (ser
->baud_base
< 2400)
1148 /* No paper tape reader for Mitch.. */
1154 static struct uart_ops sci_uart_ops
= {
1155 .tx_empty
= sci_tx_empty
,
1156 .set_mctrl
= sci_set_mctrl
,
1157 .get_mctrl
= sci_get_mctrl
,
1158 .start_tx
= sci_start_tx
,
1159 .stop_tx
= sci_stop_tx
,
1160 .stop_rx
= sci_stop_rx
,
1161 .enable_ms
= sci_enable_ms
,
1162 .break_ctl
= sci_break_ctl
,
1163 .startup
= sci_startup
,
1164 .shutdown
= sci_shutdown
,
1165 .set_termios
= sci_set_termios
,
1167 .release_port
= sci_release_port
,
1168 .request_port
= sci_request_port
,
1169 .config_port
= sci_config_port
,
1170 .verify_port
= sci_verify_port
,
1173 static void __init
sci_init_ports(void)
1175 static int first
= 1;
1183 for (i
= 0; i
< SCI_NPORTS
; i
++) {
1184 sci_ports
[i
].port
.ops
= &sci_uart_ops
;
1185 sci_ports
[i
].port
.iotype
= UPIO_MEM
;
1186 sci_ports
[i
].port
.line
= i
;
1187 sci_ports
[i
].port
.fifosize
= 1;
1189 #if defined(__H8300H__) || defined(__H8300S__)
1191 sci_ports
[i
].enable
= h8300_sci_enable
;
1192 sci_ports
[i
].disable
= h8300_sci_disable
;
1194 sci_ports
[i
].port
.uartclk
= CONFIG_CPU_CLOCK
;
1195 #elif defined(CONFIG_SUPERH64)
1196 sci_ports
[i
].port
.uartclk
= current_cpu_data
.module_clock
* 16;
1199 * XXX: We should use a proper SCI/SCIF clock
1202 struct clk
*clk
= clk_get(NULL
, "module_clk");
1203 sci_ports
[i
].port
.uartclk
= clk_get_rate(clk
) * 16;
1208 sci_ports
[i
].break_timer
.data
= (unsigned long)&sci_ports
[i
];
1209 sci_ports
[i
].break_timer
.function
= sci_break_timer
;
1211 init_timer(&sci_ports
[i
].break_timer
);
1215 int __init
early_sci_setup(struct uart_port
*port
)
1217 if (unlikely(port
->line
> SCI_NPORTS
))
1222 sci_ports
[port
->line
].port
.membase
= port
->membase
;
1223 sci_ports
[port
->line
].port
.mapbase
= port
->mapbase
;
1224 sci_ports
[port
->line
].port
.type
= port
->type
;
1229 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1231 * Print a string to the serial port trying not to disturb
1232 * any possible real use of the port...
1234 static void serial_console_write(struct console
*co
, const char *s
,
1237 put_string(serial_console_port
, s
, count
);
1240 static int __init
serial_console_setup(struct console
*co
, char *options
)
1242 struct uart_port
*port
;
1250 * Check whether an invalid uart number has been specified, and
1251 * if so, search for the first available port that does have
1254 if (co
->index
>= SCI_NPORTS
)
1257 serial_console_port
= &sci_ports
[co
->index
];
1258 port
= &serial_console_port
->port
;
1261 * Also need to check port->type, we don't actually have any
1262 * UPIO_PORT ports, but uart_report_port() handily misreports
1263 * it anyways if we don't have a port available by the time this is
1268 if (!port
->membase
|| !port
->mapbase
)
1271 port
->type
= serial_console_port
->type
;
1273 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1274 if (!serial_console_port
->clk
)
1275 serial_console_port
->clk
= clk_get(NULL
, "module_clk");
1278 if (port
->flags
& UPF_IOREMAP
)
1279 sci_config_port(port
, 0);
1281 if (serial_console_port
->enable
)
1282 serial_console_port
->enable(port
);
1285 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1287 ret
= uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1288 #if defined(__H8300H__) || defined(__H8300S__)
1289 /* disable rx interrupt */
1296 static struct console serial_console
= {
1298 .device
= uart_console_device
,
1299 .write
= serial_console_write
,
1300 .setup
= serial_console_setup
,
1301 .flags
= CON_PRINTBUFFER
,
1303 .data
= &sci_uart_driver
,
1306 static int __init
sci_console_init(void)
1309 register_console(&serial_console
);
1312 console_initcall(sci_console_init
);
1313 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1315 #ifdef CONFIG_SH_KGDB_CONSOLE
1317 * FIXME: Most of this can go away.. at the moment, we rely on
1318 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1319 * most of that can easily be done here instead.
1321 * For the time being, just accept the values that were parsed earlier..
1323 static void __init
kgdb_console_get_options(struct uart_port
*port
, int *baud
,
1324 int *parity
, int *bits
)
1327 *parity
= tolower(kgdb_parity
);
1328 *bits
= kgdb_bits
- '0';
1332 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1333 * care of the early-on initialization for kgdb, regardless of whether we
1334 * actually use kgdb as a console or not.
1336 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1338 int __init
kgdb_console_setup(struct console
*co
, char *options
)
1340 struct uart_port
*port
= &sci_ports
[kgdb_portnum
].port
;
1346 if (co
->index
!= kgdb_portnum
)
1347 co
->index
= kgdb_portnum
;
1349 kgdb_sci_port
= &sci_ports
[co
->index
];
1350 port
= &kgdb_sci_port
->port
;
1353 * Also need to check port->type, we don't actually have any
1354 * UPIO_PORT ports, but uart_report_port() handily misreports
1355 * it anyways if we don't have a port available by the time this is
1360 if (!port
->membase
|| !port
->mapbase
)
1364 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1366 kgdb_console_get_options(port
, &baud
, &parity
, &bits
);
1368 kgdb_getchar
= kgdb_sci_getchar
;
1369 kgdb_putchar
= kgdb_sci_putchar
;
1371 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1374 static struct console kgdb_console
= {
1376 .device
= uart_console_device
,
1377 .write
= kgdb_console_write
,
1378 .setup
= kgdb_console_setup
,
1379 .flags
= CON_PRINTBUFFER
,
1381 .data
= &sci_uart_driver
,
1384 /* Register the KGDB console so we get messages (d'oh!) */
1385 static int __init
kgdb_console_init(void)
1388 register_console(&kgdb_console
);
1391 console_initcall(kgdb_console_init
);
1392 #endif /* CONFIG_SH_KGDB_CONSOLE */
1394 #if defined(CONFIG_SH_KGDB_CONSOLE)
1395 #define SCI_CONSOLE &kgdb_console
1396 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1397 #define SCI_CONSOLE &serial_console
1399 #define SCI_CONSOLE 0
1402 static char banner
[] __initdata
=
1403 KERN_INFO
"SuperH SCI(F) driver initialized\n";
1405 static struct uart_driver sci_uart_driver
= {
1406 .owner
= THIS_MODULE
,
1407 .driver_name
= "sci",
1408 .dev_name
= "ttySC",
1410 .minor
= SCI_MINOR_START
,
1412 .cons
= SCI_CONSOLE
,
1416 * Register a set of serial devices attached to a platform device. The
1417 * list is terminated with a zero flags entry, which means we expect
1418 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1419 * remapping (such as sh64) should also set UPF_IOREMAP.
1421 static int __devinit
sci_probe(struct platform_device
*dev
)
1423 struct plat_sci_port
*p
= dev
->dev
.platform_data
;
1426 for (i
= 0; p
&& p
->flags
!= 0; p
++, i
++) {
1427 struct sci_port
*sciport
= &sci_ports
[i
];
1430 if (unlikely(i
== SCI_NPORTS
)) {
1431 dev_notice(&dev
->dev
, "Attempting to register port "
1432 "%d when only %d are available.\n",
1434 dev_notice(&dev
->dev
, "Consider bumping "
1435 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1439 sciport
->port
.mapbase
= p
->mapbase
;
1442 * For the simple (and majority of) cases where we don't need
1443 * to do any remapping, just cast the cookie directly.
1445 if (p
->mapbase
&& !p
->membase
&& !(p
->flags
& UPF_IOREMAP
))
1446 p
->membase
= (void __iomem
*)p
->mapbase
;
1448 sciport
->port
.membase
= p
->membase
;
1450 sciport
->port
.irq
= p
->irqs
[SCIx_TXI_IRQ
];
1451 sciport
->port
.flags
= p
->flags
;
1452 sciport
->port
.dev
= &dev
->dev
;
1454 sciport
->type
= sciport
->port
.type
= p
->type
;
1456 memcpy(&sciport
->irqs
, &p
->irqs
, sizeof(p
->irqs
));
1458 uart_add_one_port(&sci_uart_driver
, &sciport
->port
);
1461 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1462 kgdb_sci_port
= &sci_ports
[kgdb_portnum
];
1463 kgdb_getchar
= kgdb_sci_getchar
;
1464 kgdb_putchar
= kgdb_sci_putchar
;
1467 #ifdef CONFIG_CPU_FREQ
1468 cpufreq_register_notifier(&sci_nb
, CPUFREQ_TRANSITION_NOTIFIER
);
1469 dev_info(&dev
->dev
, "CPU frequency notifier registered\n");
1472 #ifdef CONFIG_SH_STANDARD_BIOS
1473 sh_bios_gdb_detach();
1479 static int __devexit
sci_remove(struct platform_device
*dev
)
1483 for (i
= 0; i
< SCI_NPORTS
; i
++)
1484 uart_remove_one_port(&sci_uart_driver
, &sci_ports
[i
].port
);
1489 static int sci_suspend(struct platform_device
*dev
, pm_message_t state
)
1493 for (i
= 0; i
< SCI_NPORTS
; i
++) {
1494 struct sci_port
*p
= &sci_ports
[i
];
1496 if (p
->type
!= PORT_UNKNOWN
&& p
->port
.dev
== &dev
->dev
)
1497 uart_suspend_port(&sci_uart_driver
, &p
->port
);
1503 static int sci_resume(struct platform_device
*dev
)
1507 for (i
= 0; i
< SCI_NPORTS
; i
++) {
1508 struct sci_port
*p
= &sci_ports
[i
];
1510 if (p
->type
!= PORT_UNKNOWN
&& p
->port
.dev
== &dev
->dev
)
1511 uart_resume_port(&sci_uart_driver
, &p
->port
);
1517 static struct platform_driver sci_driver
= {
1519 .remove
= __devexit_p(sci_remove
),
1520 .suspend
= sci_suspend
,
1521 .resume
= sci_resume
,
1524 .owner
= THIS_MODULE
,
1528 static int __init
sci_init(void)
1536 ret
= uart_register_driver(&sci_uart_driver
);
1537 if (likely(ret
== 0)) {
1538 ret
= platform_driver_register(&sci_driver
);
1540 uart_unregister_driver(&sci_uart_driver
);
1546 static void __exit
sci_exit(void)
1548 platform_driver_unregister(&sci_driver
);
1549 uart_unregister_driver(&sci_uart_driver
);
1552 module_init(sci_init
);
1553 module_exit(sci_exit
);
1555 MODULE_LICENSE("GPL");
1556 MODULE_ALIAS("platform:sh-sci");