1 #include <linux/serial_core.h>
5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6 #include <asm/regs306x.h>
8 #if defined(CONFIG_H8S2678)
9 #include <asm/regs267x.h>
12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
20 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
21 # define SCIF0 0xA4400000
22 # define SCIF2 0xA4410000
23 # define SCSMR_Ir 0xA44A0000
24 # define IRDA_SCIF SCIF0
25 # define SCPCR 0xA4000116
26 # define SCPDR 0xA4000136
28 /* Set the clock source,
29 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
32 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
34 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7721)
36 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
38 #define SCIF_ORER 0x0200 /* overrun error bit */
39 #elif defined(CONFIG_SH_RTS7751R2D)
40 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41 # define SCIF_ORER 0x0001 /* overrun error bit */
42 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
44 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7751R)
50 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
51 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
52 # define SCIF_ORER 0x0001 /* overrun error bit */
53 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
57 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
58 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
59 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
60 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
61 # define SCIF_ORER 0x0001 /* overrun error bit */
62 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
64 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
65 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
66 # define SCIF_ORER 0x0001 /* overrun error bit */
67 # define PACR 0xa4050100
68 # define PBCR 0xa4050102
69 # define SCSCR_INIT(port) 0x3B
71 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
78 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79 # define PADR 0xA4050120
80 # define PSDR 0xA405013e
81 # define PWDR 0xA4050166
82 # define PSCR 0xA405011E
83 # define SCIF_ORER 0x0001 /* overrun error bit */
84 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
86 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
87 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
88 # define SCSPTR0 SCPDR0
89 # define SCIF_ORER 0x0001 /* overrun error bit */
90 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
91 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
92 # define SCSPTR0 0xa4050160
93 # define SCSPTR1 0xa405013e
94 # define SCSPTR2 0xa4050160
95 # define SCSPTR3 0xa405013e
96 # define SCSPTR4 0xa4050128
97 # define SCSPTR5 0xa4050128
98 # define SCIF_ORER 0x0001 /* overrun error bit */
99 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
102 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
103 # define SCIF_ORER 0x0001 /* overrun error bit */
104 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
106 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
107 # define SCIF_BASE_ADDR 0x01030000
108 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
109 # define SCIF_PTR2_OFFS 0x0000020
110 # define SCIF_LSR2_OFFS 0x0000024
111 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
113 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
115 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
116 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
118 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
119 #elif defined(CONFIG_H8S2678)
120 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
123 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
124 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
125 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
126 # define SCIF_ORER 0x0001 /* overrun error bit */
127 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
130 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
131 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
132 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
133 # define SCIF_ORER 0x0001 /* overrun error bit */
134 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
136 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
137 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
138 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
139 # define SCIF_ORER 0x0001 /* Overrun error bit */
140 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
143 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
144 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
145 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
146 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
147 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
148 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
149 # define SCIF_OPER 0x0001 /* Overrun error bit */
150 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
152 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7263)
155 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
156 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
157 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
158 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
159 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
161 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
162 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
163 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
164 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
165 # define SCIF_ORER 0x0001 /* overrun error bit */
166 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
168 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
169 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
170 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
171 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
172 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
173 # define SCIF_ORER 0x0001 /* Overrun error bit */
174 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
177 # error CPU subtype not defined
181 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
182 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
183 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
184 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
185 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
193 defined(CONFIG_CPU_SUBTYPE_SHX3)
194 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
196 #define SCI_CTRL_FLAGS_REIE 0
198 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
201 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
204 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
213 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
216 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
225 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
226 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
227 defined(CONFIG_CPU_SUBTYPE_SH7721)
228 #define SCIF_ORER 0x0200
229 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
230 #define SCIF_RFDC_MASK 0x007f
231 #define SCIF_TXROOM_MAX 64
233 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
234 #define SCIF_RFDC_MASK 0x001f
235 #define SCIF_TXROOM_MAX 16
238 #if defined(SCI_ONLY)
239 # define SCxSR_TEND(port) SCI_TEND
240 # define SCxSR_ERRORS(port) SCI_ERRORS
241 # define SCxSR_RDxF(port) SCI_RDRF
242 # define SCxSR_TDxE(port) SCI_TDRE
243 # define SCxSR_ORER(port) SCI_ORER
244 # define SCxSR_FER(port) SCI_FER
245 # define SCxSR_PER(port) SCI_PER
246 # define SCxSR_BRK(port) 0x00
247 # define SCxSR_RDxF_CLEAR(port) 0xbc
248 # define SCxSR_ERROR_CLEAR(port) 0xc4
249 # define SCxSR_TDxE_CLEAR(port) 0x78
250 # define SCxSR_BREAK_CLEAR(port) 0xc4
251 #elif defined(SCIF_ONLY)
252 # define SCxSR_TEND(port) SCIF_TEND
253 # define SCxSR_ERRORS(port) SCIF_ERRORS
254 # define SCxSR_RDxF(port) SCIF_RDF
255 # define SCxSR_TDxE(port) SCIF_TDFE
256 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
257 # define SCxSR_ORER(port) SCIF_ORER
259 # define SCxSR_ORER(port) 0x0000
261 # define SCxSR_FER(port) SCIF_FER
262 # define SCxSR_PER(port) SCIF_PER
263 # define SCxSR_BRK(port) SCIF_BRK
264 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7721)
267 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
268 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
269 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
270 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
272 /* SH7705 can also use this, clearing is same between 7705 and 7709 */
273 # define SCxSR_RDxF_CLEAR(port) 0x00fc
274 # define SCxSR_ERROR_CLEAR(port) 0x0073
275 # define SCxSR_TDxE_CLEAR(port) 0x00df
276 # define SCxSR_BREAK_CLEAR(port) 0x00e3
279 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
280 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
281 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
282 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
283 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
284 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
285 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
286 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
287 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
288 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
289 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
290 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
294 #define SCFCR_RFRST 0x0002
295 #define SCFCR_TFRST 0x0004
296 #define SCFCR_TCRST 0x4000
297 #define SCFCR_MCE 0x0008
299 #define SCI_MAJOR 204
300 #define SCI_MINOR_START 8
302 /* Generic serial flags */
303 #define SCI_RX_THROTTLE 0x0000001
305 #define SCI_MAGIC 0xbabeface
308 * Events are used to schedule things to happen at timer-interrupt
309 * time, instead of at rs interrupt time.
311 #define SCI_EVENT_WRITE_WAKEUP 0
313 #define SCI_IN(size, offset) \
314 unsigned int addr = port->mapbase + (offset); \
316 return ctrl_inb(addr); \
318 return ctrl_inw(addr); \
320 #define SCI_OUT(size, offset, value) \
321 unsigned int addr = port->mapbase + (offset); \
323 ctrl_outb(value, addr); \
324 } else if ((size) == 16) { \
325 ctrl_outw(value, addr); \
328 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
329 static inline unsigned int sci_##name##_in(struct uart_port *port) \
331 if (port->type == PORT_SCI) { \
332 SCI_IN(sci_size, sci_offset) \
334 SCI_IN(scif_size, scif_offset); \
337 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
339 if (port->type == PORT_SCI) { \
340 SCI_OUT(sci_size, sci_offset, value) \
342 SCI_OUT(scif_size, scif_offset, value); \
346 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
347 static inline unsigned int sci_##name##_in(struct uart_port *port) \
349 SCI_IN(scif_size, scif_offset); \
351 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
353 SCI_OUT(scif_size, scif_offset, value); \
356 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
357 static inline unsigned int sci_##name##_in(struct uart_port* port) \
359 SCI_IN(sci_size, sci_offset); \
361 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
363 SCI_OUT(sci_size, sci_offset, value); \
366 #ifdef CONFIG_CPU_SH3
367 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
368 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
369 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
372 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
373 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
374 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
375 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
376 defined(CONFIG_CPU_SUBTYPE_SH7721)
377 #define SCIF_FNS(name, scif_offset, scif_size) \
378 CPU_SCIF_FNS(name, scif_offset, scif_size)
380 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
381 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
382 h8_sci_offset, h8_sci_size) \
383 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
384 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
385 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
387 #elif defined(__H8300H__) || defined(__H8300S__)
388 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
389 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
390 h8_sci_offset, h8_sci_size) \
391 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
392 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
393 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
394 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
395 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
396 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
397 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
399 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
400 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
401 h8_sci_offset, h8_sci_size) \
402 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
403 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
404 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
407 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
409 defined(CONFIG_CPU_SUBTYPE_SH7721)
411 SCIF_FNS(SCSMR
, 0x00, 16)
412 SCIF_FNS(SCBRR
, 0x04, 8)
413 SCIF_FNS(SCSCR
, 0x08, 16)
414 SCIF_FNS(SCTDSR
, 0x0c, 8)
415 SCIF_FNS(SCFER
, 0x10, 16)
416 SCIF_FNS(SCxSR
, 0x14, 16)
417 SCIF_FNS(SCFCR
, 0x18, 16)
418 SCIF_FNS(SCFDR
, 0x1c, 16)
419 SCIF_FNS(SCxTDR
, 0x20, 8)
420 SCIF_FNS(SCxRDR
, 0x24, 8)
421 SCIF_FNS(SCLSR
, 0x24, 16)
422 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
423 SCIx_FNS(SCSMR
, 0x00, 16, 0x00, 16)
424 SCIx_FNS(SCBRR
, 0x04, 8, 0x04, 8)
425 SCIx_FNS(SCSCR
, 0x08, 16, 0x08, 16)
426 SCIx_FNS(SCxTDR
, 0x20, 8, 0x0c, 8)
427 SCIx_FNS(SCxSR
, 0x14, 16, 0x10, 16)
428 SCIx_FNS(SCxRDR
, 0x24, 8, 0x14, 8)
429 SCIF_FNS(SCTDSR
, 0x0c, 8)
430 SCIF_FNS(SCFER
, 0x10, 16)
431 SCIF_FNS(SCFCR
, 0x18, 16)
432 SCIF_FNS(SCFDR
, 0x1c, 16)
433 SCIF_FNS(SCLSR
, 0x24, 16)
435 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
436 /* name off sz off sz off sz off sz off sz*/
437 SCIx_FNS(SCSMR
, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
438 SCIx_FNS(SCBRR
, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
439 SCIx_FNS(SCSCR
, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
440 SCIx_FNS(SCxTDR
, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
441 SCIx_FNS(SCxSR
, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
442 SCIx_FNS(SCxRDR
, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
443 SCIF_FNS(SCFCR
, 0x0c, 8, 0x18, 16)
444 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
445 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7785)
448 SCIF_FNS(SCFDR
, 0x0e, 16, 0x1C, 16)
449 SCIF_FNS(SCTFDR
, 0x0e, 16, 0x1C, 16)
450 SCIF_FNS(SCRFDR
, 0x0e, 16, 0x20, 16)
451 SCIF_FNS(SCSPTR
, 0, 0, 0x24, 16)
452 SCIF_FNS(SCLSR
, 0, 0, 0x28, 16)
454 SCIF_FNS(SCFDR
, 0x0e, 16, 0x1C, 16)
455 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
456 SCIF_FNS(SCSPTR
, 0, 0, 0, 0)
458 SCIF_FNS(SCSPTR
, 0, 0, 0x20, 16)
460 SCIF_FNS(SCLSR
, 0, 0, 0x24, 16)
463 #define sci_in(port, reg) sci_##reg##_in(port)
464 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
466 /* H8/300 series SCI pins assignment */
467 #if defined(__H8300H__) || defined(__H8300S__)
468 static const struct __attribute__((packed
)) {
469 int port
; /* GPIO port no */
470 unsigned short rx
,tx
; /* GPIO bit no */
471 } h8300_sci_pins
[] = {
472 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
474 .port
= H8300_GPIO_P9
,
479 .port
= H8300_GPIO_P9
,
484 .port
= H8300_GPIO_PB
,
488 #elif defined(CONFIG_H8S2678)
490 .port
= H8300_GPIO_P3
,
495 .port
= H8300_GPIO_P3
,
500 .port
= H8300_GPIO_P5
,
508 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
509 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
510 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
511 defined(CONFIG_CPU_SUBTYPE_SH7709)
512 static inline int sci_rxd_in(struct uart_port
*port
)
514 if (port
->mapbase
== 0xfffffe80)
515 return ctrl_inb(SCPDR
)&0x01 ? 1 : 0; /* SCI */
516 if (port
->mapbase
== 0xa4000150)
517 return ctrl_inb(SCPDR
)&0x10 ? 1 : 0; /* SCIF */
518 if (port
->mapbase
== 0xa4000140)
519 return ctrl_inb(SCPDR
)&0x04 ? 1 : 0; /* IRDA */
522 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
523 static inline int sci_rxd_in(struct uart_port
*port
)
525 if (port
->mapbase
== SCIF0
)
526 return ctrl_inb(SCPDR
)&0x04 ? 1 : 0; /* IRDA */
527 if (port
->mapbase
== SCIF2
)
528 return ctrl_inb(SCPDR
)&0x10 ? 1 : 0; /* SCIF */
531 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
532 static inline int sci_rxd_in(struct uart_port
*port
)
534 return sci_in(port
,SCxSR
)&0x0010 ? 1 : 0;
536 static inline void set_sh771x_scif_pfc(struct uart_port
*port
)
538 if (port
->mapbase
== 0xA4400000){
539 ctrl_outw(ctrl_inw(PACR
)&0xffc0,PACR
);
540 ctrl_outw(ctrl_inw(PBCR
)&0x0fff,PBCR
);
543 if (port
->mapbase
== 0xA4410000){
544 ctrl_outw(ctrl_inw(PBCR
)&0xf003,PBCR
);
548 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
549 defined(CONFIG_CPU_SUBTYPE_SH7721)
550 static inline int sci_rxd_in(struct uart_port
*port
)
552 if (port
->mapbase
== 0xa4430000)
553 return sci_in(port
, SCxSR
) & 0x0003 ? 1 : 0;
554 else if (port
->mapbase
== 0xa4438000)
555 return sci_in(port
, SCxSR
) & 0x0003 ? 1 : 0;
558 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
559 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
560 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
561 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
562 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
563 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
564 defined(CONFIG_CPU_SUBTYPE_SH4_202)
565 static inline int sci_rxd_in(struct uart_port
*port
)
568 if (port
->mapbase
== 0xffe00000)
569 return ctrl_inb(SCSPTR1
)&0x01 ? 1 : 0; /* SCI */
572 if (port
->mapbase
== 0xffe80000)
573 return ctrl_inw(SCSPTR2
)&0x0001 ? 1 : 0; /* SCIF */
577 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
578 static inline int sci_rxd_in(struct uart_port
*port
)
580 if (port
->mapbase
== 0xfe600000)
581 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
582 if (port
->mapbase
== 0xfe610000)
583 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
584 if (port
->mapbase
== 0xfe620000)
585 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
588 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
589 static inline int sci_rxd_in(struct uart_port
*port
)
591 if (port
->mapbase
== 0xffe00000)
592 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
593 if (port
->mapbase
== 0xffe10000)
594 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
595 if (port
->mapbase
== 0xffe20000)
596 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
597 if (port
->mapbase
== 0xffe30000)
598 return ctrl_inw(SCSPTR3
) & 0x0001 ? 1 : 0; /* SCIF */
601 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
602 static inline int sci_rxd_in(struct uart_port
*port
)
604 if (port
->mapbase
== 0xffe00000)
605 return ctrl_inb(SCPDR0
) & 0x0001 ? 1 : 0; /* SCIF0 */
608 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
609 static inline int sci_rxd_in(struct uart_port
*port
)
611 if (port
->mapbase
== 0xffe00000)
612 return ctrl_inb(PSDR
) & 0x02 ? 1 : 0; /* SCIF0 */
613 if (port
->mapbase
== 0xffe10000)
614 return ctrl_inb(PADR
) & 0x40 ? 1 : 0; /* SCIF1 */
615 if (port
->mapbase
== 0xffe20000)
616 return ctrl_inb(PWDR
) & 0x04 ? 1 : 0; /* SCIF2 */
620 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
621 static inline int sci_rxd_in(struct uart_port
*port
)
623 if (port
->mapbase
== 0xffe00000)
624 return ctrl_inb(SCSPTR0
) & 0x0008 ? 1 : 0; /* SCIF0 */
625 if (port
->mapbase
== 0xffe10000)
626 return ctrl_inb(SCSPTR1
) & 0x0020 ? 1 : 0; /* SCIF1 */
627 if (port
->mapbase
== 0xffe20000)
628 return ctrl_inb(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF2 */
629 if (port
->mapbase
== 0xa4e30000)
630 return ctrl_inb(SCSPTR3
) & 0x0001 ? 1 : 0; /* SCIF3 */
631 if (port
->mapbase
== 0xa4e40000)
632 return ctrl_inb(SCSPTR4
) & 0x0001 ? 1 : 0; /* SCIF4 */
633 if (port
->mapbase
== 0xa4e50000)
634 return ctrl_inb(SCSPTR5
) & 0x0008 ? 1 : 0; /* SCIF5 */
637 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
638 static inline int sci_rxd_in(struct uart_port
*port
)
640 return sci_in(port
, SCSPTR
)&0x0001 ? 1 : 0; /* SCIF */
642 #elif defined(__H8300H__) || defined(__H8300S__)
643 static inline int sci_rxd_in(struct uart_port
*port
)
645 int ch
= (port
->mapbase
- SMR0
) >> 3;
646 return (H8300_SCI_DR(ch
) & h8300_sci_pins
[ch
].rx
) ? 1 : 0;
648 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
649 static inline int sci_rxd_in(struct uart_port
*port
)
651 if (port
->mapbase
== 0xffe00000)
652 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port
->mapbase
== 0xffe08000)
654 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
657 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
658 static inline int sci_rxd_in(struct uart_port
*port
)
660 if (port
->mapbase
== 0xff923000)
661 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
662 if (port
->mapbase
== 0xff924000)
663 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
664 if (port
->mapbase
== 0xff925000)
665 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
668 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
669 static inline int sci_rxd_in(struct uart_port
*port
)
671 if (port
->mapbase
== 0xffe00000)
672 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
673 if (port
->mapbase
== 0xffe10000)
674 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
677 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
678 static inline int sci_rxd_in(struct uart_port
*port
)
680 if (port
->mapbase
== 0xffea0000)
681 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
682 if (port
->mapbase
== 0xffeb0000)
683 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
684 if (port
->mapbase
== 0xffec0000)
685 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
686 if (port
->mapbase
== 0xffed0000)
687 return ctrl_inw(SCSPTR3
) & 0x0001 ? 1 : 0; /* SCIF */
688 if (port
->mapbase
== 0xffee0000)
689 return ctrl_inw(SCSPTR4
) & 0x0001 ? 1 : 0; /* SCIF */
690 if (port
->mapbase
== 0xffef0000)
691 return ctrl_inw(SCSPTR5
) & 0x0001 ? 1 : 0; /* SCIF */
694 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
695 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
696 defined(CONFIG_CPU_SUBTYPE_SH7263)
697 static inline int sci_rxd_in(struct uart_port
*port
)
699 if (port
->mapbase
== 0xfffe8000)
700 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
701 if (port
->mapbase
== 0xfffe8800)
702 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
703 if (port
->mapbase
== 0xfffe9000)
704 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
705 if (port
->mapbase
== 0xfffe9800)
706 return ctrl_inw(SCSPTR3
) & 0x0001 ? 1 : 0; /* SCIF */
709 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
710 static inline int sci_rxd_in(struct uart_port
*port
)
712 if (port
->mapbase
== 0xf8400000)
713 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
714 if (port
->mapbase
== 0xf8410000)
715 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
716 if (port
->mapbase
== 0xf8420000)
717 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
720 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
721 static inline int sci_rxd_in(struct uart_port
*port
)
723 if (port
->mapbase
== 0xffc30000)
724 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
725 if (port
->mapbase
== 0xffc40000)
726 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
727 if (port
->mapbase
== 0xffc50000)
728 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
729 if (port
->mapbase
== 0xffc60000)
730 return ctrl_inw(SCSPTR3
) & 0x0001 ? 1 : 0; /* SCIF */
736 * Values for the BitRate Register (SCBRR)
738 * The values are actually divisors for a frequency which can
739 * be internal to the SH3 (14.7456MHz) or derived from an external
740 * clock source. This driver assumes the internal clock is used;
741 * to support using an external clock source, config options or
742 * possibly command-line options would need to be added.
744 * Also, to support speeds below 2400 (why?) the lower 2 bits of
745 * the SCSMR register would also need to be set to non-zero values.
747 * -- Greg Banks 27Feb2000
749 * Answer: The SCBRR register is only eight bits, and the value in
750 * it gets larger with lower baud rates. At around 2400 (depending on
751 * the peripherial module clock) you run out of bits. However the
752 * lower two bits of SCSMR allow the module clock to be divided down,
753 * scaling the value which is needed in SCBRR.
755 * -- Stuart Menefy - 23 May 2000
757 * I meant, why would anyone bother with bitrates below 2400.
759 * -- Greg Banks - 7Jul2000
761 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
762 * tape reader as a console!
764 * -- Mitch Davis - 15 Jul 2000
767 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
768 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
769 defined(CONFIG_CPU_SUBTYPE_SH7785)
770 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
771 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
772 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
773 defined(CONFIG_CPU_SUBTYPE_SH7721)
774 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
775 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
776 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
777 #elif defined(__H8300H__) || defined(__H8300S__)
778 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
779 #elif defined(CONFIG_SUPERH64)
780 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
781 #else /* Generic SH */
782 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
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