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Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq
[deliverable/linux.git] / drivers / serial / sunzilog.c
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/major.h>
23 #include <linux/string.h>
24 #include <linux/ptrace.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #ifdef CONFIG_SERIO
33 #include <linux/serio.h>
34 #endif
35 #include <linux/init.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/of_device.h>
41
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47
48 #include "suncore.h"
49 #include "sunzilog.h"
50
51 /* On 32-bit sparcs we need to delay after register accesses
52 * to accommodate sun4 systems, but we do not need to flush writes.
53 * On 64-bit sparc we only need to flush single writes to ensure
54 * completion.
55 */
56 #ifndef CONFIG_SPARC64
57 #define ZSDELAY() udelay(5)
58 #define ZSDELAY_LONG() udelay(20)
59 #define ZS_WSYNC(channel) do { } while (0)
60 #else
61 #define ZSDELAY()
62 #define ZSDELAY_LONG()
63 #define ZS_WSYNC(__channel) \
64 readb(&((__channel)->control))
65 #endif
66
67 static int num_sunzilog;
68 #define NUM_SUNZILOG num_sunzilog
69 #define NUM_CHANNELS (NUM_SUNZILOG * 2)
70
71 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
72 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
73
74 /*
75 * We wrap our port structure around the generic uart_port.
76 */
77 struct uart_sunzilog_port {
78 struct uart_port port;
79
80 /* IRQ servicing chain. */
81 struct uart_sunzilog_port *next;
82
83 /* Current values of Zilog write registers. */
84 unsigned char curregs[NUM_ZSREGS];
85
86 unsigned int flags;
87 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
88 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
89 #define SUNZILOG_FLAG_IS_CONS 0x00000004
90 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
91 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
92 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
93 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
94 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
95 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
96
97 unsigned int cflag;
98
99 unsigned char parity_mask;
100 unsigned char prev_status;
101
102 #ifdef CONFIG_SERIO
103 struct serio serio;
104 int serio_open;
105 #endif
106 };
107
108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
109 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
110
111 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
113 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
114 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
115 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
116 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
117 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
118 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
119 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
120
121 /* Reading and writing Zilog8530 registers. The delays are to make this
122 * driver work on the Sun4 which needs a settling delay after each chip
123 * register access, other machines handle this in hardware via auxiliary
124 * flip-flops which implement the settle time we do in software.
125 *
126 * The port lock must be held and local IRQs must be disabled
127 * when {read,write}_zsreg is invoked.
128 */
129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
130 unsigned char reg)
131 {
132 unsigned char retval;
133
134 writeb(reg, &channel->control);
135 ZSDELAY();
136 retval = readb(&channel->control);
137 ZSDELAY();
138
139 return retval;
140 }
141
142 static void write_zsreg(struct zilog_channel __iomem *channel,
143 unsigned char reg, unsigned char value)
144 {
145 writeb(reg, &channel->control);
146 ZSDELAY();
147 writeb(value, &channel->control);
148 ZSDELAY();
149 }
150
151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
152 {
153 int i;
154
155 for (i = 0; i < 32; i++) {
156 unsigned char regval;
157
158 regval = readb(&channel->control);
159 ZSDELAY();
160 if (regval & Rx_CH_AV)
161 break;
162
163 regval = read_zsreg(channel, R1);
164 readb(&channel->data);
165 ZSDELAY();
166
167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
168 writeb(ERR_RES, &channel->control);
169 ZSDELAY();
170 ZS_WSYNC(channel);
171 }
172 }
173 }
174
175 /* This function must only be called when the TX is not busy. The UART
176 * port lock must be held and local interrupts disabled.
177 */
178 static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
179 {
180 int i;
181
182 /* Let pending transmits finish. */
183 for (i = 0; i < 1000; i++) {
184 unsigned char stat = read_zsreg(channel, R1);
185 if (stat & ALL_SNT)
186 break;
187 udelay(100);
188 }
189
190 writeb(ERR_RES, &channel->control);
191 ZSDELAY();
192 ZS_WSYNC(channel);
193
194 sunzilog_clear_fifo(channel);
195
196 /* Disable all interrupts. */
197 write_zsreg(channel, R1,
198 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
199
200 /* Set parity, sync config, stop bits, and clock divisor. */
201 write_zsreg(channel, R4, regs[R4]);
202
203 /* Set misc. TX/RX control bits. */
204 write_zsreg(channel, R10, regs[R10]);
205
206 /* Set TX/RX controls sans the enable bits. */
207 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
208 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
209
210 /* Synchronous mode config. */
211 write_zsreg(channel, R6, regs[R6]);
212 write_zsreg(channel, R7, regs[R7]);
213
214 /* Don't mess with the interrupt vector (R2, unused by us) and
215 * master interrupt control (R9). We make sure this is setup
216 * properly at probe time then never touch it again.
217 */
218
219 /* Disable baud generator. */
220 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
221
222 /* Clock mode control. */
223 write_zsreg(channel, R11, regs[R11]);
224
225 /* Lower and upper byte of baud rate generator divisor. */
226 write_zsreg(channel, R12, regs[R12]);
227 write_zsreg(channel, R13, regs[R13]);
228
229 /* Now rewrite R14, with BRENAB (if set). */
230 write_zsreg(channel, R14, regs[R14]);
231
232 /* External status interrupt control. */
233 write_zsreg(channel, R15, regs[R15]);
234
235 /* Reset external status interrupts. */
236 write_zsreg(channel, R0, RES_EXT_INT);
237 write_zsreg(channel, R0, RES_EXT_INT);
238
239 /* Rewrite R3/R5, this time without enables masked. */
240 write_zsreg(channel, R3, regs[R3]);
241 write_zsreg(channel, R5, regs[R5]);
242
243 /* Rewrite R1, this time without IRQ enabled masked. */
244 write_zsreg(channel, R1, regs[R1]);
245 }
246
247 /* Reprogram the Zilog channel HW registers with the copies found in the
248 * software state struct. If the transmitter is busy, we defer this update
249 * until the next TX complete interrupt. Else, we do it right now.
250 *
251 * The UART port lock must be held and local interrupts disabled.
252 */
253 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
254 struct zilog_channel __iomem *channel)
255 {
256 if (!ZS_REGS_HELD(up)) {
257 if (ZS_TX_ACTIVE(up)) {
258 up->flags |= SUNZILOG_FLAG_REGS_HELD;
259 } else {
260 __load_zsregs(channel, up->curregs);
261 }
262 }
263 }
264
265 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
266 {
267 unsigned int cur_cflag = up->cflag;
268 int brg, new_baud;
269
270 up->cflag &= ~CBAUD;
271 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
272
273 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
274 up->curregs[R12] = (brg & 0xff);
275 up->curregs[R13] = (brg >> 8) & 0xff;
276 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
277 }
278
279 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
280 unsigned char ch, int is_break,
281 struct pt_regs *regs)
282 {
283 if (ZS_IS_KEYB(up)) {
284 /* Stop-A is handled by drivers/char/keyboard.c now. */
285 #ifdef CONFIG_SERIO
286 if (up->serio_open)
287 serio_interrupt(&up->serio, ch, 0, regs);
288 #endif
289 } else if (ZS_IS_MOUSE(up)) {
290 int ret = suncore_mouse_baud_detection(ch, is_break);
291
292 switch (ret) {
293 case 2:
294 sunzilog_change_mouse_baud(up);
295 /* fallthru */
296 case 1:
297 break;
298
299 case 0:
300 #ifdef CONFIG_SERIO
301 if (up->serio_open)
302 serio_interrupt(&up->serio, ch, 0, regs);
303 #endif
304 break;
305 };
306 }
307 }
308
309 static struct tty_struct *
310 sunzilog_receive_chars(struct uart_sunzilog_port *up,
311 struct zilog_channel __iomem *channel,
312 struct pt_regs *regs)
313 {
314 struct tty_struct *tty;
315 unsigned char ch, r1, flag;
316
317 tty = NULL;
318 if (up->port.info != NULL && /* Unopened serial console */
319 up->port.info->tty != NULL) /* Keyboard || mouse */
320 tty = up->port.info->tty;
321
322 for (;;) {
323
324 r1 = read_zsreg(channel, R1);
325 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
326 writeb(ERR_RES, &channel->control);
327 ZSDELAY();
328 ZS_WSYNC(channel);
329 }
330
331 ch = readb(&channel->control);
332 ZSDELAY();
333
334 /* This funny hack depends upon BRK_ABRT not interfering
335 * with the other bits we care about in R1.
336 */
337 if (ch & BRK_ABRT)
338 r1 |= BRK_ABRT;
339
340 if (!(ch & Rx_CH_AV))
341 break;
342
343 ch = readb(&channel->data);
344 ZSDELAY();
345
346 ch &= up->parity_mask;
347
348 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
349 sunzilog_kbdms_receive_chars(up, ch, 0, regs);
350 continue;
351 }
352
353 if (tty == NULL) {
354 uart_handle_sysrq_char(&up->port, ch, regs);
355 continue;
356 }
357
358 /* A real serial line, record the character and status. */
359 flag = TTY_NORMAL;
360 up->port.icount.rx++;
361 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
362 if (r1 & BRK_ABRT) {
363 r1 &= ~(PAR_ERR | CRC_ERR);
364 up->port.icount.brk++;
365 if (uart_handle_break(&up->port))
366 continue;
367 }
368 else if (r1 & PAR_ERR)
369 up->port.icount.parity++;
370 else if (r1 & CRC_ERR)
371 up->port.icount.frame++;
372 if (r1 & Rx_OVR)
373 up->port.icount.overrun++;
374 r1 &= up->port.read_status_mask;
375 if (r1 & BRK_ABRT)
376 flag = TTY_BREAK;
377 else if (r1 & PAR_ERR)
378 flag = TTY_PARITY;
379 else if (r1 & CRC_ERR)
380 flag = TTY_FRAME;
381 }
382 if (uart_handle_sysrq_char(&up->port, ch, regs))
383 continue;
384
385 if (up->port.ignore_status_mask == 0xff ||
386 (r1 & up->port.ignore_status_mask) == 0) {
387 tty_insert_flip_char(tty, ch, flag);
388 }
389 if (r1 & Rx_OVR)
390 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
391 }
392
393 return tty;
394 }
395
396 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
397 struct zilog_channel __iomem *channel,
398 struct pt_regs *regs)
399 {
400 unsigned char status;
401
402 status = readb(&channel->control);
403 ZSDELAY();
404
405 writeb(RES_EXT_INT, &channel->control);
406 ZSDELAY();
407 ZS_WSYNC(channel);
408
409 if (status & BRK_ABRT) {
410 if (ZS_IS_MOUSE(up))
411 sunzilog_kbdms_receive_chars(up, 0, 1, regs);
412 if (ZS_IS_CONS(up)) {
413 /* Wait for BREAK to deassert to avoid potentially
414 * confusing the PROM.
415 */
416 while (1) {
417 status = readb(&channel->control);
418 ZSDELAY();
419 if (!(status & BRK_ABRT))
420 break;
421 }
422 sun_do_break();
423 return;
424 }
425 }
426
427 if (ZS_WANTS_MODEM_STATUS(up)) {
428 if (status & SYNC)
429 up->port.icount.dsr++;
430
431 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
432 * But it does not tell us which bit has changed, we have to keep
433 * track of this ourselves.
434 */
435 if ((status ^ up->prev_status) ^ DCD)
436 uart_handle_dcd_change(&up->port,
437 (status & DCD));
438 if ((status ^ up->prev_status) ^ CTS)
439 uart_handle_cts_change(&up->port,
440 (status & CTS));
441
442 wake_up_interruptible(&up->port.info->delta_msr_wait);
443 }
444
445 up->prev_status = status;
446 }
447
448 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
449 struct zilog_channel __iomem *channel)
450 {
451 struct circ_buf *xmit;
452
453 if (ZS_IS_CONS(up)) {
454 unsigned char status = readb(&channel->control);
455 ZSDELAY();
456
457 /* TX still busy? Just wait for the next TX done interrupt.
458 *
459 * It can occur because of how we do serial console writes. It would
460 * be nice to transmit console writes just like we normally would for
461 * a TTY line. (ie. buffered and TX interrupt driven). That is not
462 * easy because console writes cannot sleep. One solution might be
463 * to poll on enough port->xmit space becomming free. -DaveM
464 */
465 if (!(status & Tx_BUF_EMP))
466 return;
467 }
468
469 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
470
471 if (ZS_REGS_HELD(up)) {
472 __load_zsregs(channel, up->curregs);
473 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
474 }
475
476 if (ZS_TX_STOPPED(up)) {
477 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
478 goto ack_tx_int;
479 }
480
481 if (up->port.x_char) {
482 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
483 writeb(up->port.x_char, &channel->data);
484 ZSDELAY();
485 ZS_WSYNC(channel);
486
487 up->port.icount.tx++;
488 up->port.x_char = 0;
489 return;
490 }
491
492 if (up->port.info == NULL)
493 goto ack_tx_int;
494 xmit = &up->port.info->xmit;
495 if (uart_circ_empty(xmit))
496 goto ack_tx_int;
497
498 if (uart_tx_stopped(&up->port))
499 goto ack_tx_int;
500
501 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
502 writeb(xmit->buf[xmit->tail], &channel->data);
503 ZSDELAY();
504 ZS_WSYNC(channel);
505
506 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
507 up->port.icount.tx++;
508
509 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
510 uart_write_wakeup(&up->port);
511
512 return;
513
514 ack_tx_int:
515 writeb(RES_Tx_P, &channel->control);
516 ZSDELAY();
517 ZS_WSYNC(channel);
518 }
519
520 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
521 {
522 struct uart_sunzilog_port *up = dev_id;
523
524 while (up) {
525 struct zilog_channel __iomem *channel
526 = ZILOG_CHANNEL_FROM_PORT(&up->port);
527 struct tty_struct *tty;
528 unsigned char r3;
529
530 spin_lock(&up->port.lock);
531 r3 = read_zsreg(channel, R3);
532
533 /* Channel A */
534 tty = NULL;
535 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
536 writeb(RES_H_IUS, &channel->control);
537 ZSDELAY();
538 ZS_WSYNC(channel);
539
540 if (r3 & CHARxIP)
541 tty = sunzilog_receive_chars(up, channel, regs);
542 if (r3 & CHAEXT)
543 sunzilog_status_handle(up, channel, regs);
544 if (r3 & CHATxIP)
545 sunzilog_transmit_chars(up, channel);
546 }
547 spin_unlock(&up->port.lock);
548
549 if (tty)
550 tty_flip_buffer_push(tty);
551
552 /* Channel B */
553 up = up->next;
554 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
555
556 spin_lock(&up->port.lock);
557 tty = NULL;
558 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
559 writeb(RES_H_IUS, &channel->control);
560 ZSDELAY();
561 ZS_WSYNC(channel);
562
563 if (r3 & CHBRxIP)
564 tty = sunzilog_receive_chars(up, channel, regs);
565 if (r3 & CHBEXT)
566 sunzilog_status_handle(up, channel, regs);
567 if (r3 & CHBTxIP)
568 sunzilog_transmit_chars(up, channel);
569 }
570 spin_unlock(&up->port.lock);
571
572 if (tty)
573 tty_flip_buffer_push(tty);
574
575 up = up->next;
576 }
577
578 return IRQ_HANDLED;
579 }
580
581 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
582 * port lock, it is acquired here.
583 */
584 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
585 {
586 struct zilog_channel __iomem *channel;
587 unsigned char status;
588
589 channel = ZILOG_CHANNEL_FROM_PORT(port);
590 status = readb(&channel->control);
591 ZSDELAY();
592
593 return status;
594 }
595
596 /* The port lock is not held. */
597 static unsigned int sunzilog_tx_empty(struct uart_port *port)
598 {
599 unsigned long flags;
600 unsigned char status;
601 unsigned int ret;
602
603 spin_lock_irqsave(&port->lock, flags);
604
605 status = sunzilog_read_channel_status(port);
606
607 spin_unlock_irqrestore(&port->lock, flags);
608
609 if (status & Tx_BUF_EMP)
610 ret = TIOCSER_TEMT;
611 else
612 ret = 0;
613
614 return ret;
615 }
616
617 /* The port lock is held and interrupts are disabled. */
618 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
619 {
620 unsigned char status;
621 unsigned int ret;
622
623 status = sunzilog_read_channel_status(port);
624
625 ret = 0;
626 if (status & DCD)
627 ret |= TIOCM_CAR;
628 if (status & SYNC)
629 ret |= TIOCM_DSR;
630 if (status & CTS)
631 ret |= TIOCM_CTS;
632
633 return ret;
634 }
635
636 /* The port lock is held and interrupts are disabled. */
637 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
638 {
639 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
640 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
641 unsigned char set_bits, clear_bits;
642
643 set_bits = clear_bits = 0;
644
645 if (mctrl & TIOCM_RTS)
646 set_bits |= RTS;
647 else
648 clear_bits |= RTS;
649 if (mctrl & TIOCM_DTR)
650 set_bits |= DTR;
651 else
652 clear_bits |= DTR;
653
654 /* NOTE: Not subject to 'transmitter active' rule. */
655 up->curregs[R5] |= set_bits;
656 up->curregs[R5] &= ~clear_bits;
657 write_zsreg(channel, R5, up->curregs[R5]);
658 }
659
660 /* The port lock is held and interrupts are disabled. */
661 static void sunzilog_stop_tx(struct uart_port *port)
662 {
663 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
664
665 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
666 }
667
668 /* The port lock is held and interrupts are disabled. */
669 static void sunzilog_start_tx(struct uart_port *port)
670 {
671 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
672 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
673 unsigned char status;
674
675 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
676 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
677
678 status = readb(&channel->control);
679 ZSDELAY();
680
681 /* TX busy? Just wait for the TX done interrupt. */
682 if (!(status & Tx_BUF_EMP))
683 return;
684
685 /* Send the first character to jump-start the TX done
686 * IRQ sending engine.
687 */
688 if (port->x_char) {
689 writeb(port->x_char, &channel->data);
690 ZSDELAY();
691 ZS_WSYNC(channel);
692
693 port->icount.tx++;
694 port->x_char = 0;
695 } else {
696 struct circ_buf *xmit = &port->info->xmit;
697
698 writeb(xmit->buf[xmit->tail], &channel->data);
699 ZSDELAY();
700 ZS_WSYNC(channel);
701
702 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
703 port->icount.tx++;
704
705 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
706 uart_write_wakeup(&up->port);
707 }
708 }
709
710 /* The port lock is held. */
711 static void sunzilog_stop_rx(struct uart_port *port)
712 {
713 struct uart_sunzilog_port *up = UART_ZILOG(port);
714 struct zilog_channel __iomem *channel;
715
716 if (ZS_IS_CONS(up))
717 return;
718
719 channel = ZILOG_CHANNEL_FROM_PORT(port);
720
721 /* Disable all RX interrupts. */
722 up->curregs[R1] &= ~RxINT_MASK;
723 sunzilog_maybe_update_regs(up, channel);
724 }
725
726 /* The port lock is held. */
727 static void sunzilog_enable_ms(struct uart_port *port)
728 {
729 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
730 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
731 unsigned char new_reg;
732
733 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
734 if (new_reg != up->curregs[R15]) {
735 up->curregs[R15] = new_reg;
736
737 /* NOTE: Not subject to 'transmitter active' rule. */
738 write_zsreg(channel, R15, up->curregs[R15]);
739 }
740 }
741
742 /* The port lock is not held. */
743 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
744 {
745 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
746 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
747 unsigned char set_bits, clear_bits, new_reg;
748 unsigned long flags;
749
750 set_bits = clear_bits = 0;
751
752 if (break_state)
753 set_bits |= SND_BRK;
754 else
755 clear_bits |= SND_BRK;
756
757 spin_lock_irqsave(&port->lock, flags);
758
759 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
760 if (new_reg != up->curregs[R5]) {
761 up->curregs[R5] = new_reg;
762
763 /* NOTE: Not subject to 'transmitter active' rule. */
764 write_zsreg(channel, R5, up->curregs[R5]);
765 }
766
767 spin_unlock_irqrestore(&port->lock, flags);
768 }
769
770 static void __sunzilog_startup(struct uart_sunzilog_port *up)
771 {
772 struct zilog_channel __iomem *channel;
773
774 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
775 up->prev_status = readb(&channel->control);
776
777 /* Enable receiver and transmitter. */
778 up->curregs[R3] |= RxENAB;
779 up->curregs[R5] |= TxENAB;
780
781 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
782 sunzilog_maybe_update_regs(up, channel);
783 }
784
785 static int sunzilog_startup(struct uart_port *port)
786 {
787 struct uart_sunzilog_port *up = UART_ZILOG(port);
788 unsigned long flags;
789
790 if (ZS_IS_CONS(up))
791 return 0;
792
793 spin_lock_irqsave(&port->lock, flags);
794 __sunzilog_startup(up);
795 spin_unlock_irqrestore(&port->lock, flags);
796 return 0;
797 }
798
799 /*
800 * The test for ZS_IS_CONS is explained by the following e-mail:
801 *****
802 * From: Russell King <rmk@arm.linux.org.uk>
803 * Date: Sun, 8 Dec 2002 10:18:38 +0000
804 *
805 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
806 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
807 * > and I noticed that something is not right with reference
808 * > counting in this case. It seems that when the console
809 * > is open by kernel initially, this is not accounted
810 * > as an open, and uart_startup is not called.
811 *
812 * That is correct. We are unable to call uart_startup when the serial
813 * console is initialised because it may need to allocate memory (as
814 * request_irq does) and the memory allocators may not have been
815 * initialised.
816 *
817 * 1. initialise the port into a state where it can send characters in the
818 * console write method.
819 *
820 * 2. don't do the actual hardware shutdown in your shutdown() method (but
821 * do the normal software shutdown - ie, free irqs etc)
822 *****
823 */
824 static void sunzilog_shutdown(struct uart_port *port)
825 {
826 struct uart_sunzilog_port *up = UART_ZILOG(port);
827 struct zilog_channel __iomem *channel;
828 unsigned long flags;
829
830 if (ZS_IS_CONS(up))
831 return;
832
833 spin_lock_irqsave(&port->lock, flags);
834
835 channel = ZILOG_CHANNEL_FROM_PORT(port);
836
837 /* Disable receiver and transmitter. */
838 up->curregs[R3] &= ~RxENAB;
839 up->curregs[R5] &= ~TxENAB;
840
841 /* Disable all interrupts and BRK assertion. */
842 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
843 up->curregs[R5] &= ~SND_BRK;
844 sunzilog_maybe_update_regs(up, channel);
845
846 spin_unlock_irqrestore(&port->lock, flags);
847 }
848
849 /* Shared by TTY driver and serial console setup. The port lock is held
850 * and local interrupts are disabled.
851 */
852 static void
853 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
854 unsigned int iflag, int brg)
855 {
856
857 up->curregs[R10] = NRZ;
858 up->curregs[R11] = TCBR | RCBR;
859
860 /* Program BAUD and clock source. */
861 up->curregs[R4] &= ~XCLK_MASK;
862 up->curregs[R4] |= X16CLK;
863 up->curregs[R12] = brg & 0xff;
864 up->curregs[R13] = (brg >> 8) & 0xff;
865 up->curregs[R14] = BRSRC | BRENAB;
866
867 /* Character size, stop bits, and parity. */
868 up->curregs[3] &= ~RxN_MASK;
869 up->curregs[5] &= ~TxN_MASK;
870 switch (cflag & CSIZE) {
871 case CS5:
872 up->curregs[3] |= Rx5;
873 up->curregs[5] |= Tx5;
874 up->parity_mask = 0x1f;
875 break;
876 case CS6:
877 up->curregs[3] |= Rx6;
878 up->curregs[5] |= Tx6;
879 up->parity_mask = 0x3f;
880 break;
881 case CS7:
882 up->curregs[3] |= Rx7;
883 up->curregs[5] |= Tx7;
884 up->parity_mask = 0x7f;
885 break;
886 case CS8:
887 default:
888 up->curregs[3] |= Rx8;
889 up->curregs[5] |= Tx8;
890 up->parity_mask = 0xff;
891 break;
892 };
893 up->curregs[4] &= ~0x0c;
894 if (cflag & CSTOPB)
895 up->curregs[4] |= SB2;
896 else
897 up->curregs[4] |= SB1;
898 if (cflag & PARENB)
899 up->curregs[4] |= PAR_ENAB;
900 else
901 up->curregs[4] &= ~PAR_ENAB;
902 if (!(cflag & PARODD))
903 up->curregs[4] |= PAR_EVEN;
904 else
905 up->curregs[4] &= ~PAR_EVEN;
906
907 up->port.read_status_mask = Rx_OVR;
908 if (iflag & INPCK)
909 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
910 if (iflag & (BRKINT | PARMRK))
911 up->port.read_status_mask |= BRK_ABRT;
912
913 up->port.ignore_status_mask = 0;
914 if (iflag & IGNPAR)
915 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
916 if (iflag & IGNBRK) {
917 up->port.ignore_status_mask |= BRK_ABRT;
918 if (iflag & IGNPAR)
919 up->port.ignore_status_mask |= Rx_OVR;
920 }
921
922 if ((cflag & CREAD) == 0)
923 up->port.ignore_status_mask = 0xff;
924 }
925
926 /* The port lock is not held. */
927 static void
928 sunzilog_set_termios(struct uart_port *port, struct termios *termios,
929 struct termios *old)
930 {
931 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
932 unsigned long flags;
933 int baud, brg;
934
935 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
936
937 spin_lock_irqsave(&up->port.lock, flags);
938
939 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
940
941 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
942
943 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
944 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
945 else
946 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
947
948 up->cflag = termios->c_cflag;
949
950 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
951
952 uart_update_timeout(port, termios->c_cflag, baud);
953
954 spin_unlock_irqrestore(&up->port.lock, flags);
955 }
956
957 static const char *sunzilog_type(struct uart_port *port)
958 {
959 return "zs";
960 }
961
962 /* We do not request/release mappings of the registers here, this
963 * happens at early serial probe time.
964 */
965 static void sunzilog_release_port(struct uart_port *port)
966 {
967 }
968
969 static int sunzilog_request_port(struct uart_port *port)
970 {
971 return 0;
972 }
973
974 /* These do not need to do anything interesting either. */
975 static void sunzilog_config_port(struct uart_port *port, int flags)
976 {
977 }
978
979 /* We do not support letting the user mess with the divisor, IRQ, etc. */
980 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
981 {
982 return -EINVAL;
983 }
984
985 static struct uart_ops sunzilog_pops = {
986 .tx_empty = sunzilog_tx_empty,
987 .set_mctrl = sunzilog_set_mctrl,
988 .get_mctrl = sunzilog_get_mctrl,
989 .stop_tx = sunzilog_stop_tx,
990 .start_tx = sunzilog_start_tx,
991 .stop_rx = sunzilog_stop_rx,
992 .enable_ms = sunzilog_enable_ms,
993 .break_ctl = sunzilog_break_ctl,
994 .startup = sunzilog_startup,
995 .shutdown = sunzilog_shutdown,
996 .set_termios = sunzilog_set_termios,
997 .type = sunzilog_type,
998 .release_port = sunzilog_release_port,
999 .request_port = sunzilog_request_port,
1000 .config_port = sunzilog_config_port,
1001 .verify_port = sunzilog_verify_port,
1002 };
1003
1004 static struct uart_sunzilog_port *sunzilog_port_table;
1005 static struct zilog_layout __iomem **sunzilog_chip_regs;
1006
1007 static struct uart_sunzilog_port *sunzilog_irq_chain;
1008
1009 static struct uart_driver sunzilog_reg = {
1010 .owner = THIS_MODULE,
1011 .driver_name = "ttyS",
1012 .dev_name = "ttyS",
1013 .major = TTY_MAJOR,
1014 };
1015
1016 static int __init sunzilog_alloc_tables(void)
1017 {
1018 struct uart_sunzilog_port *up;
1019 unsigned long size;
1020 int i;
1021
1022 size = NUM_CHANNELS * sizeof(struct uart_sunzilog_port);
1023 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1024 if (!sunzilog_port_table)
1025 return -ENOMEM;
1026
1027 for (i = 0; i < NUM_CHANNELS; i++) {
1028 up = &sunzilog_port_table[i];
1029
1030 spin_lock_init(&up->port.lock);
1031
1032 if (i == 0)
1033 sunzilog_irq_chain = up;
1034
1035 if (i < NUM_CHANNELS - 1)
1036 up->next = up + 1;
1037 else
1038 up->next = NULL;
1039 }
1040
1041 size = NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *);
1042 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1043 if (!sunzilog_chip_regs) {
1044 kfree(sunzilog_port_table);
1045 sunzilog_irq_chain = NULL;
1046 return -ENOMEM;
1047 }
1048
1049 return 0;
1050 }
1051
1052 static void sunzilog_free_tables(void)
1053 {
1054 kfree(sunzilog_port_table);
1055 sunzilog_irq_chain = NULL;
1056 kfree(sunzilog_chip_regs);
1057 }
1058
1059 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1060
1061 static void sunzilog_putchar(struct uart_port *port, int ch)
1062 {
1063 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1064 int loops = ZS_PUT_CHAR_MAX_DELAY;
1065
1066 /* This is a timed polling loop so do not switch the explicit
1067 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1068 */
1069 do {
1070 unsigned char val = readb(&channel->control);
1071 if (val & Tx_BUF_EMP) {
1072 ZSDELAY();
1073 break;
1074 }
1075 udelay(5);
1076 } while (--loops);
1077
1078 writeb(ch, &channel->data);
1079 ZSDELAY();
1080 ZS_WSYNC(channel);
1081 }
1082
1083 #ifdef CONFIG_SERIO
1084
1085 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1086
1087 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1088 {
1089 struct uart_sunzilog_port *up = serio->port_data;
1090 unsigned long flags;
1091
1092 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1093
1094 sunzilog_putchar(&up->port, ch);
1095
1096 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1097
1098 return 0;
1099 }
1100
1101 static int sunzilog_serio_open(struct serio *serio)
1102 {
1103 struct uart_sunzilog_port *up = serio->port_data;
1104 unsigned long flags;
1105 int ret;
1106
1107 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1108 if (!up->serio_open) {
1109 up->serio_open = 1;
1110 ret = 0;
1111 } else
1112 ret = -EBUSY;
1113 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1114
1115 return ret;
1116 }
1117
1118 static void sunzilog_serio_close(struct serio *serio)
1119 {
1120 struct uart_sunzilog_port *up = serio->port_data;
1121 unsigned long flags;
1122
1123 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1124 up->serio_open = 0;
1125 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1126 }
1127
1128 #endif /* CONFIG_SERIO */
1129
1130 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1131 static void
1132 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1133 {
1134 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1135 unsigned long flags;
1136
1137 spin_lock_irqsave(&up->port.lock, flags);
1138 uart_console_write(&up->port, s, count, sunzilog_putchar);
1139 udelay(2);
1140 spin_unlock_irqrestore(&up->port.lock, flags);
1141 }
1142
1143 static int __init sunzilog_console_setup(struct console *con, char *options)
1144 {
1145 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1146 unsigned long flags;
1147 int baud, brg;
1148
1149 if (up->port.type != PORT_SUNZILOG)
1150 return -1;
1151
1152 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1153 (sunzilog_reg.minor - 64) + con->index, con->index);
1154
1155 /* Get firmware console settings. */
1156 sunserial_console_termios(con);
1157
1158 /* Firmware console speed is limited to 150-->38400 baud so
1159 * this hackish cflag thing is OK.
1160 */
1161 switch (con->cflag & CBAUD) {
1162 case B150: baud = 150; break;
1163 case B300: baud = 300; break;
1164 case B600: baud = 600; break;
1165 case B1200: baud = 1200; break;
1166 case B2400: baud = 2400; break;
1167 case B4800: baud = 4800; break;
1168 default: case B9600: baud = 9600; break;
1169 case B19200: baud = 19200; break;
1170 case B38400: baud = 38400; break;
1171 };
1172
1173 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1174
1175 spin_lock_irqsave(&up->port.lock, flags);
1176
1177 up->curregs[R15] = BRKIE;
1178 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1179
1180 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1181 __sunzilog_startup(up);
1182
1183 spin_unlock_irqrestore(&up->port.lock, flags);
1184
1185 return 0;
1186 }
1187
1188 static struct console sunzilog_console = {
1189 .name = "ttyS",
1190 .write = sunzilog_console_write,
1191 .device = uart_console_device,
1192 .setup = sunzilog_console_setup,
1193 .flags = CON_PRINTBUFFER,
1194 .index = -1,
1195 .data = &sunzilog_reg,
1196 };
1197
1198 static inline struct console *SUNZILOG_CONSOLE(void)
1199 {
1200 int i;
1201
1202 if (con_is_present())
1203 return NULL;
1204
1205 for (i = 0; i < NUM_CHANNELS; i++) {
1206 int this_minor = sunzilog_reg.minor + i;
1207
1208 if ((this_minor - 64) == (serial_console - 1))
1209 break;
1210 }
1211 if (i == NUM_CHANNELS)
1212 return NULL;
1213
1214 sunzilog_console.index = i;
1215 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1216
1217 return &sunzilog_console;
1218 }
1219
1220 #else
1221 #define SUNZILOG_CONSOLE() (NULL)
1222 #endif
1223
1224 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1225 {
1226 int baud, brg;
1227
1228 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1229 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1230 baud = 1200;
1231 } else {
1232 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1233 baud = 4800;
1234 }
1235
1236 up->curregs[R15] = BRKIE;
1237 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1238 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1239 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1240 __sunzilog_startup(up);
1241 }
1242
1243 #ifdef CONFIG_SERIO
1244 static void __init sunzilog_register_serio(struct uart_sunzilog_port *up)
1245 {
1246 struct serio *serio = &up->serio;
1247
1248 serio->port_data = up;
1249
1250 serio->id.type = SERIO_RS232;
1251 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1252 serio->id.proto = SERIO_SUNKBD;
1253 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1254 } else {
1255 serio->id.proto = SERIO_SUN;
1256 serio->id.extra = 1;
1257 strlcpy(serio->name, "zsms", sizeof(serio->name));
1258 }
1259 strlcpy(serio->phys,
1260 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1261 "zs/serio0" : "zs/serio1"),
1262 sizeof(serio->phys));
1263
1264 serio->write = sunzilog_serio_write;
1265 serio->open = sunzilog_serio_open;
1266 serio->close = sunzilog_serio_close;
1267 serio->dev.parent = up->port.dev;
1268
1269 serio_register_port(serio);
1270 }
1271 #endif
1272
1273 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1274 {
1275 struct zilog_channel __iomem *channel;
1276 unsigned long flags;
1277 int baud, brg;
1278
1279 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1280
1281 spin_lock_irqsave(&up->port.lock, flags);
1282 if (ZS_IS_CHANNEL_A(up)) {
1283 write_zsreg(channel, R9, FHWRES);
1284 ZSDELAY_LONG();
1285 (void) read_zsreg(channel, R0);
1286 }
1287
1288 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1289 SUNZILOG_FLAG_CONS_MOUSE)) {
1290 sunzilog_init_kbdms(up, up->port.line);
1291 up->curregs[R9] |= (NV | MIE);
1292 write_zsreg(channel, R9, up->curregs[R9]);
1293 } else {
1294 /* Normal serial TTY. */
1295 up->parity_mask = 0xff;
1296 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1297 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1298 up->curregs[R3] = RxENAB | Rx8;
1299 up->curregs[R5] = TxENAB | Tx8;
1300 up->curregs[R9] = NV | MIE;
1301 up->curregs[R10] = NRZ;
1302 up->curregs[R11] = TCBR | RCBR;
1303 baud = 9600;
1304 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1305 up->curregs[R12] = (brg & 0xff);
1306 up->curregs[R13] = (brg >> 8) & 0xff;
1307 up->curregs[R14] = BRSRC | BRENAB;
1308 __load_zsregs(channel, up->curregs);
1309 write_zsreg(channel, R9, up->curregs[R9]);
1310 }
1311
1312 spin_unlock_irqrestore(&up->port.lock, flags);
1313
1314 #ifdef CONFIG_SERIO
1315 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1316 SUNZILOG_FLAG_CONS_MOUSE))
1317 sunzilog_register_serio(up);
1318 #endif
1319 }
1320
1321 static int zilog_irq = -1;
1322
1323 static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
1324 {
1325 static int inst;
1326 struct uart_sunzilog_port *up;
1327 struct zilog_layout __iomem *rp;
1328 int keyboard_mouse;
1329 int err;
1330
1331 keyboard_mouse = 0;
1332 if (of_find_property(op->node, "keyboard", NULL))
1333 keyboard_mouse = 1;
1334
1335 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1336 sizeof(struct zilog_layout),
1337 "zs");
1338 if (!sunzilog_chip_regs[inst])
1339 return -ENOMEM;
1340
1341 rp = sunzilog_chip_regs[inst];
1342
1343 if (zilog_irq == -1)
1344 zilog_irq = op->irqs[0];
1345
1346 up = &sunzilog_port_table[inst * 2];
1347
1348 /* Channel A */
1349 up[0].port.mapbase = op->resource[0].start + 0x00;
1350 up[0].port.membase = (void __iomem *) &rp->channelA;
1351 up[0].port.iotype = UPIO_MEM;
1352 up[0].port.irq = op->irqs[0];
1353 up[0].port.uartclk = ZS_CLOCK;
1354 up[0].port.fifosize = 1;
1355 up[0].port.ops = &sunzilog_pops;
1356 up[0].port.type = PORT_SUNZILOG;
1357 up[0].port.flags = 0;
1358 up[0].port.line = (inst * 2) + 0;
1359 up[0].port.dev = &op->dev;
1360 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1361 if (keyboard_mouse)
1362 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1363 sunzilog_init_hw(&up[0]);
1364
1365 /* Channel B */
1366 up[1].port.mapbase = op->resource[0].start + 0x04;
1367 up[1].port.membase = (void __iomem *) &rp->channelB;
1368 up[1].port.iotype = UPIO_MEM;
1369 up[1].port.irq = op->irqs[0];
1370 up[1].port.uartclk = ZS_CLOCK;
1371 up[1].port.fifosize = 1;
1372 up[1].port.ops = &sunzilog_pops;
1373 up[1].port.type = PORT_SUNZILOG;
1374 up[1].port.flags = 0;
1375 up[1].port.line = (inst * 2) + 1;
1376 up[1].port.dev = &op->dev;
1377 up[1].flags |= 0;
1378 if (keyboard_mouse)
1379 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1380 sunzilog_init_hw(&up[1]);
1381
1382 if (!keyboard_mouse) {
1383 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1384 if (err) {
1385 of_iounmap(rp, sizeof(struct zilog_layout));
1386 return err;
1387 }
1388 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1389 if (err) {
1390 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1391 of_iounmap(rp, sizeof(struct zilog_layout));
1392 return err;
1393 }
1394 } else {
1395 printk(KERN_INFO "%s: Keyboard at MMIO %lx (irq = %d) "
1396 "is a zs\n",
1397 op->dev.bus_id, up[0].port.mapbase, op->irqs[0]);
1398 printk(KERN_INFO "%s: Mouse at MMIO %lx (irq = %d) "
1399 "is a zs\n",
1400 op->dev.bus_id, up[1].port.mapbase, op->irqs[0]);
1401 }
1402
1403 dev_set_drvdata(&op->dev, &up[0]);
1404
1405 inst++;
1406
1407 return 0;
1408 }
1409
1410 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1411 {
1412 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1413 #ifdef CONFIG_SERIO
1414 serio_unregister_port(&up->serio);
1415 #endif
1416 } else
1417 uart_remove_one_port(&sunzilog_reg, &up->port);
1418 }
1419
1420 static int __devexit zs_remove(struct of_device *dev)
1421 {
1422 struct uart_sunzilog_port *up = dev_get_drvdata(&dev->dev);
1423 struct zilog_layout __iomem *regs;
1424
1425 zs_remove_one(&up[0]);
1426 zs_remove_one(&up[1]);
1427
1428 regs = sunzilog_chip_regs[up[0].port.line / 2];
1429 of_iounmap(regs, sizeof(struct zilog_layout));
1430
1431 dev_set_drvdata(&dev->dev, NULL);
1432
1433 return 0;
1434 }
1435
1436 static struct of_device_id zs_match[] = {
1437 {
1438 .name = "zs",
1439 },
1440 {},
1441 };
1442 MODULE_DEVICE_TABLE(of, zs_match);
1443
1444 static struct of_platform_driver zs_driver = {
1445 .name = "zs",
1446 .match_table = zs_match,
1447 .probe = zs_probe,
1448 .remove = __devexit_p(zs_remove),
1449 };
1450
1451 static int __init sunzilog_init(void)
1452 {
1453 struct device_node *dp;
1454 int err, uart_count;
1455 int num_keybms;
1456
1457 NUM_SUNZILOG = 0;
1458 num_keybms = 0;
1459 for_each_node_by_name(dp, "zs") {
1460 NUM_SUNZILOG++;
1461 if (of_find_property(dp, "keyboard", NULL))
1462 num_keybms++;
1463 }
1464
1465 uart_count = 0;
1466 if (NUM_SUNZILOG) {
1467 int uart_count;
1468
1469 err = sunzilog_alloc_tables();
1470 if (err)
1471 goto out;
1472
1473 uart_count = (NUM_SUNZILOG * 2) - (2 * num_keybms);
1474
1475 sunzilog_reg.nr = uart_count;
1476 sunzilog_reg.minor = sunserial_current_minor;
1477 err = uart_register_driver(&sunzilog_reg);
1478 if (err)
1479 goto out_free_tables;
1480
1481 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1482 sunzilog_reg.cons = SUNZILOG_CONSOLE();
1483
1484 sunserial_current_minor += uart_count;
1485 }
1486
1487 err = of_register_driver(&zs_driver, &of_bus_type);
1488 if (err)
1489 goto out_unregister_uart;
1490
1491 if (zilog_irq != -1) {
1492 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1493 "zs", sunzilog_irq_chain);
1494 if (err)
1495 goto out_unregister_driver;
1496 }
1497
1498 out:
1499 return err;
1500
1501 out_unregister_driver:
1502 of_unregister_driver(&zs_driver);
1503
1504 out_unregister_uart:
1505 if (NUM_SUNZILOG) {
1506 uart_unregister_driver(&sunzilog_reg);
1507 sunzilog_reg.cons = NULL;
1508 }
1509
1510 out_free_tables:
1511 sunzilog_free_tables();
1512 goto out;
1513 }
1514
1515 static void __exit sunzilog_exit(void)
1516 {
1517 of_unregister_driver(&zs_driver);
1518
1519 if (zilog_irq != -1) {
1520 free_irq(zilog_irq, sunzilog_irq_chain);
1521 zilog_irq = -1;
1522 }
1523
1524 if (NUM_SUNZILOG) {
1525 uart_unregister_driver(&sunzilog_reg);
1526 sunzilog_free_tables();
1527 }
1528 }
1529
1530 module_init(sunzilog_init);
1531 module_exit(sunzilog_exit);
1532
1533 MODULE_AUTHOR("David S. Miller");
1534 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1535 MODULE_VERSION("2.0");
1536 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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