2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/sh_intc.h>
26 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
27 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
28 ((addr_e) << 16) | ((addr_d << 24)))
30 #define _INTC_SHIFT(h) (h & 0x1f)
31 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
32 #define _INTC_FN(h) ((h >> 9) & 0xf)
33 #define _INTC_MODE(h) ((h >> 13) & 0x7)
34 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
35 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
37 struct intc_handle_int
{
42 struct intc_desc_int
{
48 struct intc_handle_int
*prio
;
50 struct intc_handle_int
*sense
;
51 unsigned int nr_sense
;
56 #define IS_SMP(x) x.smp
57 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
58 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
61 #define INTC_REG(d, x, c) (d->reg[(x)])
62 #define SMP_NR(d, x) 1
65 static unsigned int intc_prio_level
[NR_IRQS
]; /* for now */
66 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
67 static unsigned long ack_handle
[NR_IRQS
];
70 static inline struct intc_desc_int
*get_intc_desc(unsigned int irq
)
72 struct irq_chip
*chip
= get_irq_chip(irq
);
73 return (void *)((char *)chip
- offsetof(struct intc_desc_int
, chip
));
76 static inline unsigned int set_field(unsigned int value
,
77 unsigned int field_value
,
80 unsigned int width
= _INTC_WIDTH(handle
);
81 unsigned int shift
= _INTC_SHIFT(handle
);
83 value
&= ~(((1 << width
) - 1) << shift
);
84 value
|= field_value
<< shift
;
88 static void write_8(unsigned long addr
, unsigned long h
, unsigned long data
)
90 __raw_writeb(set_field(0, data
, h
), addr
);
93 static void write_16(unsigned long addr
, unsigned long h
, unsigned long data
)
95 __raw_writew(set_field(0, data
, h
), addr
);
98 static void write_32(unsigned long addr
, unsigned long h
, unsigned long data
)
100 __raw_writel(set_field(0, data
, h
), addr
);
103 static void modify_8(unsigned long addr
, unsigned long h
, unsigned long data
)
106 local_irq_save(flags
);
107 __raw_writeb(set_field(__raw_readb(addr
), data
, h
), addr
);
108 local_irq_restore(flags
);
111 static void modify_16(unsigned long addr
, unsigned long h
, unsigned long data
)
114 local_irq_save(flags
);
115 __raw_writew(set_field(__raw_readw(addr
), data
, h
), addr
);
116 local_irq_restore(flags
);
119 static void modify_32(unsigned long addr
, unsigned long h
, unsigned long data
)
122 local_irq_save(flags
);
123 __raw_writel(set_field(__raw_readl(addr
), data
, h
), addr
);
124 local_irq_restore(flags
);
127 enum { REG_FN_ERR
= 0, REG_FN_WRITE_BASE
= 1, REG_FN_MODIFY_BASE
= 5 };
129 static void (*intc_reg_fns
[])(unsigned long addr
,
131 unsigned long data
) = {
132 [REG_FN_WRITE_BASE
+ 0] = write_8
,
133 [REG_FN_WRITE_BASE
+ 1] = write_16
,
134 [REG_FN_WRITE_BASE
+ 3] = write_32
,
135 [REG_FN_MODIFY_BASE
+ 0] = modify_8
,
136 [REG_FN_MODIFY_BASE
+ 1] = modify_16
,
137 [REG_FN_MODIFY_BASE
+ 3] = modify_32
,
140 enum { MODE_ENABLE_REG
= 0, /* Bit(s) set -> interrupt enabled */
141 MODE_MASK_REG
, /* Bit(s) set -> interrupt disabled */
142 MODE_DUAL_REG
, /* Two registers, set bit to enable / disable */
143 MODE_PRIO_REG
, /* Priority value written to enable interrupt */
144 MODE_PCLR_REG
, /* Above plus all bits set to disable interrupt */
147 static void intc_mode_field(unsigned long addr
,
148 unsigned long handle
,
149 void (*fn
)(unsigned long,
154 fn(addr
, handle
, ((1 << _INTC_WIDTH(handle
)) - 1));
157 static void intc_mode_zero(unsigned long addr
,
158 unsigned long handle
,
159 void (*fn
)(unsigned long,
167 static void intc_mode_prio(unsigned long addr
,
168 unsigned long handle
,
169 void (*fn
)(unsigned long,
174 fn(addr
, handle
, intc_prio_level
[irq
]);
177 static void (*intc_enable_fns
[])(unsigned long addr
,
178 unsigned long handle
,
179 void (*fn
)(unsigned long,
182 unsigned int irq
) = {
183 [MODE_ENABLE_REG
] = intc_mode_field
,
184 [MODE_MASK_REG
] = intc_mode_zero
,
185 [MODE_DUAL_REG
] = intc_mode_field
,
186 [MODE_PRIO_REG
] = intc_mode_prio
,
187 [MODE_PCLR_REG
] = intc_mode_prio
,
190 static void (*intc_disable_fns
[])(unsigned long addr
,
191 unsigned long handle
,
192 void (*fn
)(unsigned long,
195 unsigned int irq
) = {
196 [MODE_ENABLE_REG
] = intc_mode_zero
,
197 [MODE_MASK_REG
] = intc_mode_field
,
198 [MODE_DUAL_REG
] = intc_mode_field
,
199 [MODE_PRIO_REG
] = intc_mode_zero
,
200 [MODE_PCLR_REG
] = intc_mode_field
,
203 static inline void _intc_enable(unsigned int irq
, unsigned long handle
)
205 struct intc_desc_int
*d
= get_intc_desc(irq
);
209 for (cpu
= 0; cpu
< SMP_NR(d
, _INTC_ADDR_E(handle
)); cpu
++) {
210 addr
= INTC_REG(d
, _INTC_ADDR_E(handle
), cpu
);
211 intc_enable_fns
[_INTC_MODE(handle
)](addr
, handle
, intc_reg_fns\
212 [_INTC_FN(handle
)], irq
);
216 static void intc_enable(unsigned int irq
)
218 _intc_enable(irq
, (unsigned long)get_irq_chip_data(irq
));
221 static void intc_disable(unsigned int irq
)
223 struct intc_desc_int
*d
= get_intc_desc(irq
);
224 unsigned long handle
= (unsigned long) get_irq_chip_data(irq
);
228 for (cpu
= 0; cpu
< SMP_NR(d
, _INTC_ADDR_D(handle
)); cpu
++) {
229 addr
= INTC_REG(d
, _INTC_ADDR_D(handle
), cpu
);
230 intc_disable_fns
[_INTC_MODE(handle
)](addr
, handle
,intc_reg_fns\
231 [_INTC_FN(handle
)], irq
);
235 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
236 static void intc_mask_ack(unsigned int irq
)
238 struct intc_desc_int
*d
= get_intc_desc(irq
);
239 unsigned long handle
= ack_handle
[irq
];
244 /* read register and write zero only to the assocaited bit */
247 addr
= INTC_REG(d
, _INTC_ADDR_D(handle
), 0);
248 switch (_INTC_FN(handle
)) {
249 case REG_FN_MODIFY_BASE
+ 0: /* 8bit */
251 __raw_writeb(0xff ^ set_field(0, 1, handle
), addr
);
253 case REG_FN_MODIFY_BASE
+ 1: /* 16bit */
255 __raw_writew(0xffff ^ set_field(0, 1, handle
), addr
);
257 case REG_FN_MODIFY_BASE
+ 3: /* 32bit */
259 __raw_writel(0xffffffff ^ set_field(0, 1, handle
), addr
);
269 static struct intc_handle_int
*intc_find_irq(struct intc_handle_int
*hp
,
275 /* this doesn't scale well, but...
277 * this function should only be used for cerain uncommon
278 * operations such as intc_set_priority() and intc_set_sense()
279 * and in those rare cases performance doesn't matter that much.
280 * keeping the memory footprint low is more important.
282 * one rather simple way to speed this up and still keep the
283 * memory footprint down is to make sure the array is sorted
284 * and then perform a bisect to lookup the irq.
287 for (i
= 0; i
< nr_hp
; i
++) {
288 if ((hp
+ i
)->irq
!= irq
)
297 int intc_set_priority(unsigned int irq
, unsigned int prio
)
299 struct intc_desc_int
*d
= get_intc_desc(irq
);
300 struct intc_handle_int
*ihp
;
302 if (!intc_prio_level
[irq
] || prio
<= 1)
305 ihp
= intc_find_irq(d
->prio
, d
->nr_prio
, irq
);
307 if (prio
>= (1 << _INTC_WIDTH(ihp
->handle
)))
310 intc_prio_level
[irq
] = prio
;
313 * only set secondary masking method directly
314 * primary masking method is using intc_prio_level[irq]
315 * priority level will be set during next enable()
318 if (_INTC_FN(ihp
->handle
) != REG_FN_ERR
)
319 _intc_enable(irq
, ihp
->handle
);
324 #define VALID(x) (x | 0x80)
326 static unsigned char intc_irq_sense_table
[IRQ_TYPE_SENSE_MASK
+ 1] = {
327 [IRQ_TYPE_EDGE_FALLING
] = VALID(0),
328 [IRQ_TYPE_EDGE_RISING
] = VALID(1),
329 [IRQ_TYPE_LEVEL_LOW
] = VALID(2),
330 /* SH7706, SH7707 and SH7709 do not support high level triggered */
331 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
332 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
333 !defined(CONFIG_CPU_SUBTYPE_SH7709)
334 [IRQ_TYPE_LEVEL_HIGH
] = VALID(3),
338 static int intc_set_sense(unsigned int irq
, unsigned int type
)
340 struct intc_desc_int
*d
= get_intc_desc(irq
);
341 unsigned char value
= intc_irq_sense_table
[type
& IRQ_TYPE_SENSE_MASK
];
342 struct intc_handle_int
*ihp
;
348 ihp
= intc_find_irq(d
->sense
, d
->nr_sense
, irq
);
350 addr
= INTC_REG(d
, _INTC_ADDR_E(ihp
->handle
), 0);
351 intc_reg_fns
[_INTC_FN(ihp
->handle
)](addr
, ihp
->handle
, value
);
356 static unsigned int __init
intc_get_reg(struct intc_desc_int
*d
,
357 unsigned long address
)
361 for (k
= 0; k
< d
->nr_reg
; k
++) {
362 if (d
->reg
[k
] == address
)
370 static intc_enum __init
intc_grp_id(struct intc_desc
*desc
,
373 struct intc_group
*g
= desc
->groups
;
376 for (i
= 0; g
&& enum_id
&& i
< desc
->nr_groups
; i
++) {
377 g
= desc
->groups
+ i
;
379 for (j
= 0; g
->enum_ids
[j
]; j
++) {
380 if (g
->enum_ids
[j
] != enum_id
)
390 static unsigned int __init
intc_mask_data(struct intc_desc
*desc
,
391 struct intc_desc_int
*d
,
392 intc_enum enum_id
, int do_grps
)
394 struct intc_mask_reg
*mr
= desc
->mask_regs
;
395 unsigned int i
, j
, fn
, mode
;
396 unsigned long reg_e
, reg_d
;
398 for (i
= 0; mr
&& enum_id
&& i
< desc
->nr_mask_regs
; i
++) {
399 mr
= desc
->mask_regs
+ i
;
401 for (j
= 0; j
< ARRAY_SIZE(mr
->enum_ids
); j
++) {
402 if (mr
->enum_ids
[j
] != enum_id
)
405 if (mr
->set_reg
&& mr
->clr_reg
) {
406 fn
= REG_FN_WRITE_BASE
;
407 mode
= MODE_DUAL_REG
;
411 fn
= REG_FN_MODIFY_BASE
;
413 mode
= MODE_ENABLE_REG
;
417 mode
= MODE_MASK_REG
;
423 fn
+= (mr
->reg_width
>> 3) - 1;
424 return _INTC_MK(fn
, mode
,
425 intc_get_reg(d
, reg_e
),
426 intc_get_reg(d
, reg_d
),
428 (mr
->reg_width
- 1) - j
);
433 return intc_mask_data(desc
, d
, intc_grp_id(desc
, enum_id
), 0);
438 static unsigned int __init
intc_prio_data(struct intc_desc
*desc
,
439 struct intc_desc_int
*d
,
440 intc_enum enum_id
, int do_grps
)
442 struct intc_prio_reg
*pr
= desc
->prio_regs
;
443 unsigned int i
, j
, fn
, mode
, bit
;
444 unsigned long reg_e
, reg_d
;
446 for (i
= 0; pr
&& enum_id
&& i
< desc
->nr_prio_regs
; i
++) {
447 pr
= desc
->prio_regs
+ i
;
449 for (j
= 0; j
< ARRAY_SIZE(pr
->enum_ids
); j
++) {
450 if (pr
->enum_ids
[j
] != enum_id
)
453 if (pr
->set_reg
&& pr
->clr_reg
) {
454 fn
= REG_FN_WRITE_BASE
;
455 mode
= MODE_PCLR_REG
;
459 fn
= REG_FN_MODIFY_BASE
;
460 mode
= MODE_PRIO_REG
;
467 fn
+= (pr
->reg_width
>> 3) - 1;
469 BUG_ON((j
+ 1) * pr
->field_width
> pr
->reg_width
);
471 bit
= pr
->reg_width
- ((j
+ 1) * pr
->field_width
);
473 return _INTC_MK(fn
, mode
,
474 intc_get_reg(d
, reg_e
),
475 intc_get_reg(d
, reg_d
),
476 pr
->field_width
, bit
);
481 return intc_prio_data(desc
, d
, intc_grp_id(desc
, enum_id
), 0);
486 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
487 static unsigned int __init
intc_ack_data(struct intc_desc
*desc
,
488 struct intc_desc_int
*d
,
491 struct intc_mask_reg
*mr
= desc
->ack_regs
;
492 unsigned int i
, j
, fn
, mode
;
493 unsigned long reg_e
, reg_d
;
495 for (i
= 0; mr
&& enum_id
&& i
< desc
->nr_ack_regs
; i
++) {
496 mr
= desc
->ack_regs
+ i
;
498 for (j
= 0; j
< ARRAY_SIZE(mr
->enum_ids
); j
++) {
499 if (mr
->enum_ids
[j
] != enum_id
)
502 fn
= REG_FN_MODIFY_BASE
;
503 mode
= MODE_ENABLE_REG
;
507 fn
+= (mr
->reg_width
>> 3) - 1;
508 return _INTC_MK(fn
, mode
,
509 intc_get_reg(d
, reg_e
),
510 intc_get_reg(d
, reg_d
),
512 (mr
->reg_width
- 1) - j
);
520 static unsigned int __init
intc_sense_data(struct intc_desc
*desc
,
521 struct intc_desc_int
*d
,
524 struct intc_sense_reg
*sr
= desc
->sense_regs
;
525 unsigned int i
, j
, fn
, bit
;
527 for (i
= 0; sr
&& enum_id
&& i
< desc
->nr_sense_regs
; i
++) {
528 sr
= desc
->sense_regs
+ i
;
530 for (j
= 0; j
< ARRAY_SIZE(sr
->enum_ids
); j
++) {
531 if (sr
->enum_ids
[j
] != enum_id
)
534 fn
= REG_FN_MODIFY_BASE
;
535 fn
+= (sr
->reg_width
>> 3) - 1;
537 BUG_ON((j
+ 1) * sr
->field_width
> sr
->reg_width
);
539 bit
= sr
->reg_width
- ((j
+ 1) * sr
->field_width
);
541 return _INTC_MK(fn
, 0, intc_get_reg(d
, sr
->reg
),
542 0, sr
->field_width
, bit
);
549 static void __init
intc_register_irq(struct intc_desc
*desc
,
550 struct intc_desc_int
*d
,
554 struct intc_handle_int
*hp
;
555 unsigned int data
[2], primary
;
557 /* Prefer single interrupt source bitmap over other combinations:
558 * 1. bitmap, single interrupt source
559 * 2. priority, single interrupt source
560 * 3. bitmap, multiple interrupt sources (groups)
561 * 4. priority, multiple interrupt sources (groups)
564 data
[0] = intc_mask_data(desc
, d
, enum_id
, 0);
565 data
[1] = intc_prio_data(desc
, d
, enum_id
, 0);
568 if (!data
[0] && data
[1])
571 if (!data
[0] && !data
[1])
572 pr_warning("intc: missing unique irq mask for "
573 "irq %d (vect 0x%04x)\n", irq
, irq2evt(irq
));
575 data
[0] = data
[0] ? data
[0] : intc_mask_data(desc
, d
, enum_id
, 1);
576 data
[1] = data
[1] ? data
[1] : intc_prio_data(desc
, d
, enum_id
, 1);
581 BUG_ON(!data
[primary
]); /* must have primary masking method */
583 disable_irq_nosync(irq
);
584 set_irq_chip_and_handler_name(irq
, &d
->chip
,
585 handle_level_irq
, "level");
586 set_irq_chip_data(irq
, (void *)data
[primary
]);
588 /* set priority level
589 * - this needs to be at least 2 for 5-bit priorities on 7780
591 intc_prio_level
[irq
] = 2;
593 /* enable secondary masking method if present */
595 _intc_enable(irq
, data
[!primary
]);
597 /* add irq to d->prio list if priority is available */
599 hp
= d
->prio
+ d
->nr_prio
;
601 hp
->handle
= data
[1];
605 * only secondary priority should access registers, so
606 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
609 hp
->handle
&= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
610 hp
->handle
|= _INTC_MK(REG_FN_ERR
, 0, 0, 0, 0, 0);
615 /* add irq to d->sense list if sense is available */
616 data
[0] = intc_sense_data(desc
, d
, enum_id
);
618 (d
->sense
+ d
->nr_sense
)->irq
= irq
;
619 (d
->sense
+ d
->nr_sense
)->handle
= data
[0];
623 /* irq should be disabled by default */
626 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
628 ack_handle
[irq
] = intc_ack_data(desc
, d
, enum_id
);
632 static unsigned int __init
save_reg(struct intc_desc_int
*d
,
648 static unsigned char *intc_evt2irq_table
;
650 unsigned int intc_evt2irq(unsigned int vector
)
652 unsigned int irq
= evt2irq(vector
);
654 if (intc_evt2irq_table
&& intc_evt2irq_table
[irq
])
655 irq
= intc_evt2irq_table
[irq
];
660 void __init
register_intc_controller(struct intc_desc
*desc
)
662 unsigned int i
, k
, smp
;
663 struct intc_desc_int
*d
;
665 d
= alloc_bootmem(sizeof(*d
));
667 d
->nr_reg
= desc
->mask_regs
? desc
->nr_mask_regs
* 2 : 0;
668 d
->nr_reg
+= desc
->prio_regs
? desc
->nr_prio_regs
* 2 : 0;
669 d
->nr_reg
+= desc
->sense_regs
? desc
->nr_sense_regs
: 0;
671 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
672 d
->nr_reg
+= desc
->ack_regs
? desc
->nr_ack_regs
: 0;
674 d
->reg
= alloc_bootmem(d
->nr_reg
* sizeof(*d
->reg
));
676 d
->smp
= alloc_bootmem(d
->nr_reg
* sizeof(*d
->smp
));
680 if (desc
->mask_regs
) {
681 for (i
= 0; i
< desc
->nr_mask_regs
; i
++) {
682 smp
= IS_SMP(desc
->mask_regs
[i
]);
683 k
+= save_reg(d
, k
, desc
->mask_regs
[i
].set_reg
, smp
);
684 k
+= save_reg(d
, k
, desc
->mask_regs
[i
].clr_reg
, smp
);
688 if (desc
->prio_regs
) {
689 d
->prio
= alloc_bootmem(desc
->nr_vectors
* sizeof(*d
->prio
));
691 for (i
= 0; i
< desc
->nr_prio_regs
; i
++) {
692 smp
= IS_SMP(desc
->prio_regs
[i
]);
693 k
+= save_reg(d
, k
, desc
->prio_regs
[i
].set_reg
, smp
);
694 k
+= save_reg(d
, k
, desc
->prio_regs
[i
].clr_reg
, smp
);
698 if (desc
->sense_regs
) {
699 d
->sense
= alloc_bootmem(desc
->nr_vectors
* sizeof(*d
->sense
));
701 for (i
= 0; i
< desc
->nr_sense_regs
; i
++) {
702 k
+= save_reg(d
, k
, desc
->sense_regs
[i
].reg
, 0);
706 d
->chip
.name
= desc
->name
;
707 d
->chip
.mask
= intc_disable
;
708 d
->chip
.unmask
= intc_enable
;
709 d
->chip
.mask_ack
= intc_disable
;
710 d
->chip
.set_type
= intc_set_sense
;
712 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
713 if (desc
->ack_regs
) {
714 for (i
= 0; i
< desc
->nr_ack_regs
; i
++)
715 k
+= save_reg(d
, k
, desc
->ack_regs
[i
].set_reg
, 0);
717 d
->chip
.mask_ack
= intc_mask_ack
;
721 BUG_ON(k
> 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
723 /* keep the first vector only if same enum is used multiple times */
724 for (i
= 0; i
< desc
->nr_vectors
; i
++) {
725 struct intc_vect
*vect
= desc
->vectors
+ i
;
726 int first_irq
= evt2irq(vect
->vect
);
731 for (k
= i
+ 1; k
< desc
->nr_vectors
; k
++) {
732 struct intc_vect
*vect2
= desc
->vectors
+ k
;
734 if (vect
->enum_id
!= vect2
->enum_id
)
739 if (!intc_evt2irq_table
)
740 intc_evt2irq_table
= alloc_bootmem(NR_IRQS
);
742 if (!intc_evt2irq_table
) {
743 pr_warning("intc: cannot allocate evt2irq!\n");
747 intc_evt2irq_table
[evt2irq(vect2
->vect
)] = first_irq
;
751 /* register the vectors one by one */
752 for (i
= 0; i
< desc
->nr_vectors
; i
++) {
753 struct intc_vect
*vect
= desc
->vectors
+ i
;
758 intc_register_irq(desc
, d
, vect
->enum_id
, evt2irq(vect
->vect
));
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