drivers/sh/pfc.c

   1 /*
   2  * Pinmuxed GPIO support for SuperH.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/module.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/bitops.h>
  21 #include <linux/gpio.h>
  22 #include <linux/slab.h>
  23 #include <linux/ioport.h>
  24
  25 static void pfc_iounmap(struct pinmux_info *pip)
  26 {
  27         int k;
  28
  29         for (k = 0; k < pip->num_resources; k++)
  30                 if (pip->window[k].virt)
  31                         iounmap(pip->window[k].virt);
  32
  33         kfree(pip->window);
  34         pip->window = NULL;
  35 }
  36
  37 static int pfc_ioremap(struct pinmux_info *pip)
  38 {
  39         struct resource *res;
  40         int k;
  41
  42         if (!pip->num_resources)
  43                 return 0;
  44
  45         pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
  46                               GFP_NOWAIT);
  47         if (!pip->window)
  48                 goto err1;
  49
  50         for (k = 0; k < pip->num_resources; k++) {
  51                 res = pip->resource + k;
  52                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  53                 pip->window[k].phys = res->start;
  54                 pip->window[k].size = resource_size(res);
  55                 pip->window[k].virt = ioremap_nocache(res->start,
  56                                                          resource_size(res));
  57                 if (!pip->window[k].virt)
  58                         goto err2;
  59         }
  60
  61         return 0;
  62
  63 err2:
  64         pfc_iounmap(pip);
  65 err1:
  66         return -1;
  67 }
  68
  69 static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
  70                                       unsigned long address)
  71 {
  72         struct pfc_window *window;
  73         int k;
  74
  75         /* scan through physical windows and convert address */
  76         for (k = 0; k < pip->num_resources; k++) {
  77                 window = pip->window + k;
  78
  79                 if (address < window->phys)
  80                         continue;
  81
  82                 if (address >= (window->phys + window->size))
  83                         continue;
  84
  85                 return window->virt + (address - window->phys);
  86         }
  87
  88         /* no windows defined, register must be 1:1 mapped virt:phys */
  89         return (void __iomem *)address;
  90 }
  91
  92 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  93 {
  94         if (enum_id < r->begin)
  95                 return 0;
  96
  97         if (enum_id > r->end)
  98                 return 0;
  99
 100         return 1;
 101 }
 102
 103 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
 104                                        unsigned long reg_width)
 105 {
 106         switch (reg_width) {
 107         case 8:
 108                 return ioread8(mapped_reg);
 109         case 16:
 110                 return ioread16(mapped_reg);
 111         case 32:
 112                 return ioread32(mapped_reg);
 113         }
 114
 115         BUG();
 116         return 0;
 117 }
 118
 119 static void gpio_write_raw_reg(void __iomem *mapped_reg,
 120                                unsigned long reg_width,
 121                                unsigned long data)
 122 {
 123         switch (reg_width) {
 124         case 8:
 125                 iowrite8(data, mapped_reg);
 126                 return;
 127         case 16:
 128                 iowrite16(data, mapped_reg);
 129                 return;
 130         case 32:
 131                 iowrite32(data, mapped_reg);
 132                 return;
 133         }
 134
 135         BUG();
 136 }
 137
 138 static void gpio_write_bit(struct pinmux_data_reg *dr,
 139                            unsigned long in_pos, unsigned long value)
 140 {
 141         unsigned long pos;
 142
 143         pos = dr->reg_width - (in_pos + 1);
 144
 145         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 146                  "r_width = %ld\n",
 147                  dr->reg, !!value, pos, dr->reg_width);
 148
 149         if (value)
 150                 set_bit(pos, &dr->reg_shadow);
 151         else
 152                 clear_bit(pos, &dr->reg_shadow);
 153
 154         gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 155 }
 156
 157 static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width,
 158                          unsigned long field_width, unsigned long in_pos,
 159                          unsigned long reg)
 160 {
 161         unsigned long data, mask, pos;
 162
 163         data = 0;
 164         mask = (1 << field_width) - 1;
 165         pos = reg_width - ((in_pos + 1) * field_width);
 166
 167         pr_debug("read_reg: addr = %lx, pos = %ld, "
 168                  "r_width = %ld, f_width = %ld\n",
 169                  reg, pos, reg_width, field_width);
 170
 171         data = gpio_read_raw_reg(mapped_reg, reg_width);
 172         return (data >> pos) & mask;
 173 }
 174
 175 static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width,
 176                            unsigned long field_width, unsigned long in_pos,
 177                            unsigned long value, unsigned long reg)
 178 {
 179         unsigned long mask, pos;
 180
 181         mask = (1 << field_width) - 1;
 182         pos = reg_width - ((in_pos + 1) * field_width);
 183
 184         pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
 185                  "r_width = %ld, f_width = %ld\n",
 186                  reg, value, pos, reg_width, field_width);
 187
 188         mask = ~(mask << pos);
 189         value = value << pos;
 190
 191         switch (reg_width) {
 192         case 8:
 193                 iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg);
 194                 break;
 195         case 16:
 196                 iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg);
 197                 break;
 198         case 32:
 199                 iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg);
 200                 break;
 201         }
 202 }
 203
 204 static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
 205 {
 206         struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
 207         struct pinmux_data_reg *data_reg;
 208         int k, n;
 209
 210         if (!enum_in_range(gpiop->enum_id, &gpioc->data))
 211                 return -1;
 212
 213         k = 0;
 214         while (1) {
 215                 data_reg = gpioc->data_regs + k;
 216
 217                 if (!data_reg->reg_width)
 218                         break;
 219
 220                 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
 221
 222                 for (n = 0; n < data_reg->reg_width; n++) {
 223                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 224                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 225                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 226                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 227                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 228                                 return 0;
 229                         }
 230                 }
 231                 k++;
 232         }
 233
 234         BUG();
 235
 236         return -1;
 237 }
 238
 239 static void setup_data_regs(struct pinmux_info *gpioc)
 240 {
 241         struct pinmux_data_reg *drp;
 242         int k;
 243
 244         for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
 245                 setup_data_reg(gpioc, k);
 246
 247         k = 0;
 248         while (1) {
 249                 drp = gpioc->data_regs + k;
 250
 251                 if (!drp->reg_width)
 252                         break;
 253
 254                 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
 255                                                     drp->reg_width);
 256                 k++;
 257         }
 258 }
 259
 260 static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
 261                         struct pinmux_data_reg **drp, int *bitp)
 262 {
 263         struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
 264         int k, n;
 265
 266         if (!enum_in_range(gpiop->enum_id, &gpioc->data))
 267                 return -1;
 268
 269         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 270         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 271         *drp = gpioc->data_regs + k;
 272         *bitp = n;
 273         return 0;
 274 }
 275
 276 static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
 277                           struct pinmux_cfg_reg **crp, int *indexp,
 278                           unsigned long **cntp)
 279 {
 280         struct pinmux_cfg_reg *config_reg;
 281         unsigned long r_width, f_width;
 282         int k, n;
 283
 284         k = 0;
 285         while (1) {
 286                 config_reg = gpioc->cfg_regs + k;
 287
 288                 r_width = config_reg->reg_width;
 289                 f_width = config_reg->field_width;
 290
 291                 if (!r_width)
 292                         break;
 293                 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
 294                         if (config_reg->enum_ids[n] == enum_id) {
 295                                 *crp = config_reg;
 296                                 *indexp = n;
 297                                 *cntp = &config_reg->cnt[n / (1 << f_width)];
 298                                 return 0;
 299                         }
 300                 }
 301                 k++;
 302         }
 303
 304         return -1;
 305 }
 306
 307 static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
 308                             int pos, pinmux_enum_t *enum_idp)
 309 {
 310         pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
 311         pinmux_enum_t *data = gpioc->gpio_data;
 312         int k;
 313
 314         if (!enum_in_range(enum_id, &gpioc->data)) {
 315                 if (!enum_in_range(enum_id, &gpioc->mark)) {
 316                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 317                         return -1;
 318                 }
 319         }
 320
 321         if (pos) {
 322                 *enum_idp = data[pos + 1];
 323                 return pos + 1;
 324         }
 325
 326         for (k = 0; k < gpioc->gpio_data_size; k++) {
 327                 if (data[k] == enum_id) {
 328                         *enum_idp = data[k + 1];
 329                         return k + 1;
 330                 }
 331         }
 332
 333         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 334         return -1;
 335 }
 336
 337 static void write_config_reg(struct pinmux_info *gpioc,
 338                              struct pinmux_cfg_reg *crp,
 339                              int index)
 340 {
 341         unsigned long ncomb, pos, value;
 342         void __iomem *mapped_reg;
 343
 344         ncomb = 1 << crp->field_width;
 345         pos = index / ncomb;
 346         value = index % ncomb;
 347
 348         mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
 349
 350         gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
 351                        pos, value, crp->reg);
 352 }
 353
 354 static int check_config_reg(struct pinmux_info *gpioc,
 355                             struct pinmux_cfg_reg *crp,
 356                             int index)
 357 {
 358         unsigned long ncomb, pos, value;
 359         void __iomem *mapped_reg;
 360
 361         ncomb = 1 << crp->field_width;
 362         pos = index / ncomb;
 363         value = index % ncomb;
 364
 365         mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
 366
 367         if (gpio_read_reg(mapped_reg, crp->reg_width,
 368                           crp->field_width, pos, crp->reg) == value)
 369                 return 0;
 370
 371         return -1;
 372 }
 373
 374 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
 375
 376 static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
 377                               int pinmux_type, int cfg_mode)
 378 {
 379         struct pinmux_cfg_reg *cr = NULL;
 380         pinmux_enum_t enum_id;
 381         struct pinmux_range *range;
 382         int in_range, pos, index;
 383         unsigned long *cntp;
 384
 385         switch (pinmux_type) {
 386
 387         case PINMUX_TYPE_FUNCTION:
 388                 range = NULL;
 389                 break;
 390
 391         case PINMUX_TYPE_OUTPUT:
 392                 range = &gpioc->output;
 393                 break;
 394
 395         case PINMUX_TYPE_INPUT:
 396                 range = &gpioc->input;
 397                 break;
 398
 399         case PINMUX_TYPE_INPUT_PULLUP:
 400                 range = &gpioc->input_pu;
 401                 break;
 402
 403         case PINMUX_TYPE_INPUT_PULLDOWN:
 404                 range = &gpioc->input_pd;
 405                 break;
 406
 407         default:
 408                 goto out_err;
 409         }
 410
 411         pos = 0;
 412         enum_id = 0;
 413         index = 0;
 414         while (1) {
 415                 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
 416                 if (pos <= 0)
 417                         goto out_err;
 418
 419                 if (!enum_id)
 420                         break;
 421
 422                 /* first check if this is a function enum */
 423                 in_range = enum_in_range(enum_id, &gpioc->function);
 424                 if (!in_range) {
 425                         /* not a function enum */
 426                         if (range) {
 427                                 /*
 428                                  * other range exists, so this pin is
 429                                  * a regular GPIO pin that now is being
 430                                  * bound to a specific direction.
 431                                  *
 432                                  * for this case we only allow function enums
 433                                  * and the enums that match the other range.
 434                                  */
 435                                 in_range = enum_in_range(enum_id, range);
 436
 437                                 /*
 438                                  * special case pass through for fixed
 439                                  * input-only or output-only pins without
 440                                  * function enum register association.
 441                                  */
 442                                 if (in_range && enum_id == range->force)
 443                                         continue;
 444                         } else {
 445                                 /*
 446                                  * no other range exists, so this pin
 447                                  * must then be of the function type.
 448                                  *
 449                                  * allow function type pins to select
 450                                  * any combination of function/in/out
 451                                  * in their MARK lists.
 452                                  */
 453                                 in_range = 1;
 454                         }
 455                 }
 456
 457                 if (!in_range)
 458                         continue;
 459
 460                 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
 461                         goto out_err;
 462
 463                 switch (cfg_mode) {
 464                 case GPIO_CFG_DRYRUN:
 465                         if (!*cntp || !check_config_reg(gpioc, cr, index))
 466                                 continue;
 467                         break;
 468
 469                 case GPIO_CFG_REQ:
 470                         write_config_reg(gpioc, cr, index);
 471                         *cntp = *cntp + 1;
 472                         break;
 473
 474                 case GPIO_CFG_FREE:
 475                         *cntp = *cntp - 1;
 476                         break;
 477                 }
 478         }
 479
 480         return 0;
 481  out_err:
 482         return -1;
 483 }
 484
 485 static DEFINE_SPINLOCK(gpio_lock);
 486
 487 static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
 488 {
 489         return container_of(chip, struct pinmux_info, chip);
 490 }
 491
 492 static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
 493 {
 494         struct pinmux_info *gpioc = chip_to_pinmux(chip);
 495         struct pinmux_data_reg *dummy;
 496         unsigned long flags;
 497         int i, ret, pinmux_type;
 498
 499         ret = -EINVAL;
 500
 501         if (!gpioc)
 502                 goto err_out;
 503
 504         spin_lock_irqsave(&gpio_lock, flags);
 505
 506         if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
 507                 goto err_unlock;
 508
 509         /* setup pin function here if no data is associated with pin */
 510
 511         if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
 512                 pinmux_type = PINMUX_TYPE_FUNCTION;
 513         else
 514                 pinmux_type = PINMUX_TYPE_GPIO;
 515
 516         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 517                 if (pinmux_config_gpio(gpioc, offset,
 518                                        pinmux_type,
 519                                        GPIO_CFG_DRYRUN) != 0)
 520                         goto err_unlock;
 521
 522                 if (pinmux_config_gpio(gpioc, offset,
 523                                        pinmux_type,
 524                                        GPIO_CFG_REQ) != 0)
 525                         BUG();
 526         }
 527
 528         gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
 529         gpioc->gpios[offset].flags |= pinmux_type;
 530
 531         ret = 0;
 532  err_unlock:
 533         spin_unlock_irqrestore(&gpio_lock, flags);
 534  err_out:
 535         return ret;
 536 }
 537
 538 static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
 539 {
 540         struct pinmux_info *gpioc = chip_to_pinmux(chip);
 541         unsigned long flags;
 542         int pinmux_type;
 543
 544         if (!gpioc)
 545                 return;
 546
 547         spin_lock_irqsave(&gpio_lock, flags);
 548
 549         pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
 550         pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
 551         gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
 552         gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
 553
 554         spin_unlock_irqrestore(&gpio_lock, flags);
 555 }
 556
 557 static int pinmux_direction(struct pinmux_info *gpioc,
 558                             unsigned gpio, int new_pinmux_type)
 559 {
 560         int pinmux_type;
 561         int ret = -EINVAL;
 562
 563         if (!gpioc)
 564                 goto err_out;
 565
 566         pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
 567
 568         switch (pinmux_type) {
 569         case PINMUX_TYPE_GPIO:
 570                 break;
 571         case PINMUX_TYPE_OUTPUT:
 572         case PINMUX_TYPE_INPUT:
 573         case PINMUX_TYPE_INPUT_PULLUP:
 574         case PINMUX_TYPE_INPUT_PULLDOWN:
 575                 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
 576                 break;
 577         default:
 578                 goto err_out;
 579         }
 580
 581         if (pinmux_config_gpio(gpioc, gpio,
 582                                new_pinmux_type,
 583                                GPIO_CFG_DRYRUN) != 0)
 584                 goto err_out;
 585
 586         if (pinmux_config_gpio(gpioc, gpio,
 587                                new_pinmux_type,
 588                                GPIO_CFG_REQ) != 0)
 589                 BUG();
 590
 591         gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
 592         gpioc->gpios[gpio].flags |= new_pinmux_type;
 593
 594         ret = 0;
 595  err_out:
 596         return ret;
 597 }
 598
 599 static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 600 {
 601         struct pinmux_info *gpioc = chip_to_pinmux(chip);
 602         unsigned long flags;
 603         int ret;
 604
 605         spin_lock_irqsave(&gpio_lock, flags);
 606         ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
 607         spin_unlock_irqrestore(&gpio_lock, flags);
 608
 609         return ret;
 610 }
 611
 612 static void sh_gpio_set_value(struct pinmux_info *gpioc,
 613                              unsigned gpio, int value)
 614 {
 615         struct pinmux_data_reg *dr = NULL;
 616         int bit = 0;
 617
 618         if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
 619                 BUG();
 620         else
 621                 gpio_write_bit(dr, bit, value);
 622 }
 623
 624 static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 625                                     int value)
 626 {
 627         struct pinmux_info *gpioc = chip_to_pinmux(chip);
 628         unsigned long flags;
 629         int ret;
 630
 631         sh_gpio_set_value(gpioc, offset, value);
 632         spin_lock_irqsave(&gpio_lock, flags);
 633         ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
 634         spin_unlock_irqrestore(&gpio_lock, flags);
 635
 636         return ret;
 637 }
 638
 639 static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
 640 {
 641         struct pinmux_data_reg *dr = NULL;
 642         int bit = 0;
 643
 644         if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
 645                 return -EINVAL;
 646
 647         return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg);
 648 }
 649
 650 static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
 651 {
 652         return sh_gpio_get_value(chip_to_pinmux(chip), offset);
 653 }
 654
 655 static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 656 {
 657         sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
 658 }
 659
 660 static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 661 {
 662         struct pinmux_info *gpioc = chip_to_pinmux(chip);
 663         pinmux_enum_t enum_id;
 664         pinmux_enum_t *enum_ids;
 665         int i, k, pos;
 666
 667         pos = 0;
 668         enum_id = 0;
 669         while (1) {
 670                 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
 671                 if (pos <= 0 || !enum_id)
 672                         break;
 673
 674                 for (i = 0; i < gpioc->gpio_irq_size; i++) {
 675                         enum_ids = gpioc->gpio_irq[i].enum_ids;
 676                         for (k = 0; enum_ids[k]; k++) {
 677                                 if (enum_ids[k] == enum_id)
 678                                         return gpioc->gpio_irq[i].irq;
 679                         }
 680                 }
 681         }
 682
 683         return -ENOSYS;
 684 }
 685
 686 int register_pinmux(struct pinmux_info *pip)
 687 {
 688         struct gpio_chip *chip = &pip->chip;
 689         int ret;
 690
 691         pr_info("%s handling gpio %d -> %d\n",
 692                 pip->name, pip->first_gpio, pip->last_gpio);
 693
 694         ret = pfc_ioremap(pip);
 695         if (ret < 0)
 696                 return ret;
 697
 698         setup_data_regs(pip);
 699
 700         chip->request = sh_gpio_request;
 701         chip->free = sh_gpio_free;
 702         chip->direction_input = sh_gpio_direction_input;
 703         chip->get = sh_gpio_get;
 704         chip->direction_output = sh_gpio_direction_output;
 705         chip->set = sh_gpio_set;
 706         chip->to_irq = sh_gpio_to_irq;
 707
 708         WARN_ON(pip->first_gpio != 0); /* needs testing */
 709
 710         chip->label = pip->name;
 711         chip->owner = THIS_MODULE;
 712         chip->base = pip->first_gpio;
 713         chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
 714
 715         ret = gpiochip_add(chip);
 716         if (ret < 0)
 717                 pfc_iounmap(pip);
 718
 719         return ret;
 720 }
 721
 722 int unregister_pinmux(struct pinmux_info *pip)
 723 {
 724         pr_info("%s deregistering\n", pip->name);
 725         pfc_iounmap(pip);
 726         return gpiochip_remove(&pip->chip);
 727 }