2 * drivers/soc/tegra/pmc.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
31 #include <linux/iopoll.h>
33 #include <linux/of_address.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
48 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
49 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
50 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
51 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
52 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
53 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
54 #define PMC_CNTRL_MAIN_RST (1 << 4)
56 #define DPD_SAMPLE 0x020
57 #define DPD_SAMPLE_ENABLE (1 << 0)
58 #define DPD_SAMPLE_DISABLE (0 << 0)
60 #define PWRGATE_TOGGLE 0x30
61 #define PWRGATE_TOGGLE_START (1 << 8)
63 #define REMOVE_CLAMPING 0x34
65 #define PWRGATE_STATUS 0x38
67 #define PMC_SCRATCH0 0x50
68 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
69 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
70 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
71 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
72 PMC_SCRATCH0_MODE_BOOTLOADER | \
73 PMC_SCRATCH0_MODE_RCM)
75 #define PMC_CPUPWRGOOD_TIMER 0xc8
76 #define PMC_CPUPWROFF_TIMER 0xcc
78 #define PMC_SCRATCH41 0x140
80 #define PMC_SENSOR_CTRL 0x1b0
81 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
82 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
84 #define PMC_RST_STATUS 0x1b4
85 #define PMC_RST_STATUS_POR 0
86 #define PMC_RST_STATUS_WATCHDOG 1
87 #define PMC_RST_STATUS_SENSOR 2
88 #define PMC_RST_STATUS_SW_MAIN 3
89 #define PMC_RST_STATUS_LP0 4
90 #define PMC_RST_STATUS_AOTAG 5
92 #define IO_DPD_REQ 0x1b8
93 #define IO_DPD_REQ_CODE_IDLE (0 << 30)
94 #define IO_DPD_REQ_CODE_OFF (1 << 30)
95 #define IO_DPD_REQ_CODE_ON (2 << 30)
96 #define IO_DPD_REQ_CODE_MASK (3 << 30)
98 #define IO_DPD_STATUS 0x1bc
99 #define IO_DPD2_REQ 0x1c0
100 #define IO_DPD2_STATUS 0x1c4
101 #define SEL_DPD_TIM 0x1c8
103 #define PMC_SCRATCH54 0x258
104 #define PMC_SCRATCH54_DATA_SHIFT 8
105 #define PMC_SCRATCH54_ADDR_SHIFT 0
107 #define PMC_SCRATCH55 0x25c
108 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
109 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
110 #define PMC_SCRATCH55_PINMUX_SHIFT 24
111 #define PMC_SCRATCH55_16BITOP (1 << 15)
112 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
113 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
115 #define GPU_RG_CNTRL 0x2d4
117 struct tegra_powergate
{
118 struct generic_pm_domain genpd
;
119 struct tegra_pmc
*pmc
;
122 unsigned int num_clks
;
123 struct reset_control
**resets
;
124 unsigned int num_resets
;
127 struct tegra_pmc_soc
{
128 unsigned int num_powergates
;
129 const char *const *powergates
;
130 unsigned int num_cpu_powergates
;
131 const u8
*cpu_powergates
;
133 bool has_tsense_reset
;
138 * struct tegra_pmc - NVIDIA Tegra PMC
139 * @dev: pointer to PMC device structure
140 * @base: pointer to I/O remapped register region
141 * @clk: pointer to pclk clock
142 * @soc: pointer to SoC data structure
143 * @debugfs: pointer to debugfs entry
144 * @rate: currently configured rate of pclk
145 * @suspend_mode: lowest suspend mode available
146 * @cpu_good_time: CPU power good time (in microseconds)
147 * @cpu_off_time: CPU power off time (in microsecends)
148 * @core_osc_time: core power good OSC time (in microseconds)
149 * @core_pmu_time: core power good PMU time (in microseconds)
150 * @core_off_time: core power off time (in microseconds)
151 * @corereq_high: core power request is active-high
152 * @sysclkreq_high: system clock request is active-high
153 * @combined_req: combined power request for CPU & core
154 * @cpu_pwr_good_en: CPU power good signal is enabled
155 * @lp0_vec_phys: physical base address of the LP0 warm boot code
156 * @lp0_vec_size: size of the LP0 warm boot code
157 * @powergates_available: Bitmap of available power gates
158 * @powergates_lock: mutex for power gate register access
164 struct dentry
*debugfs
;
166 const struct tegra_pmc_soc
*soc
;
170 enum tegra_suspend_mode suspend_mode
;
179 bool cpu_pwr_good_en
;
182 DECLARE_BITMAP(powergates_available
, TEGRA_POWERGATE_MAX
);
184 struct mutex powergates_lock
;
187 static struct tegra_pmc
*pmc
= &(struct tegra_pmc
) {
189 .suspend_mode
= TEGRA_SUSPEND_NONE
,
192 static inline struct tegra_powergate
*
193 to_powergate(struct generic_pm_domain
*domain
)
195 return container_of(domain
, struct tegra_powergate
, genpd
);
198 static u32
tegra_pmc_readl(unsigned long offset
)
200 return readl(pmc
->base
+ offset
);
203 static void tegra_pmc_writel(u32 value
, unsigned long offset
)
205 writel(value
, pmc
->base
+ offset
);
208 static inline bool tegra_powergate_state(int id
)
210 if (id
== TEGRA_POWERGATE_3D
&& pmc
->soc
->has_gpu_clamps
)
211 return (tegra_pmc_readl(GPU_RG_CNTRL
) & 0x1) == 0;
213 return (tegra_pmc_readl(PWRGATE_STATUS
) & BIT(id
)) != 0;
216 static inline bool tegra_powergate_is_valid(int id
)
218 return (pmc
->soc
&& pmc
->soc
->powergates
[id
]);
221 static inline bool tegra_powergate_is_available(int id
)
223 return test_bit(id
, pmc
->powergates_available
);
226 static int tegra_powergate_lookup(struct tegra_pmc
*pmc
, const char *name
)
230 if (!pmc
|| !pmc
->soc
|| !name
)
233 for (i
= 0; i
< pmc
->soc
->num_powergates
; i
++) {
234 if (!tegra_powergate_is_valid(i
))
237 if (!strcmp(name
, pmc
->soc
->powergates
[i
]))
241 dev_err(pmc
->dev
, "powergate %s not found\n", name
);
247 * tegra_powergate_set() - set the state of a partition
249 * @new_state: new state of the partition
251 static int tegra_powergate_set(unsigned int id
, bool new_state
)
256 if (id
== TEGRA_POWERGATE_3D
&& pmc
->soc
->has_gpu_clamps
)
259 mutex_lock(&pmc
->powergates_lock
);
261 if (tegra_powergate_state(id
) == new_state
) {
262 mutex_unlock(&pmc
->powergates_lock
);
266 tegra_pmc_writel(PWRGATE_TOGGLE_START
| id
, PWRGATE_TOGGLE
);
268 err
= readx_poll_timeout(tegra_powergate_state
, id
, status
,
269 status
== new_state
, 10, 100000);
271 mutex_unlock(&pmc
->powergates_lock
);
276 static int __tegra_powergate_remove_clamping(unsigned int id
)
280 mutex_lock(&pmc
->powergates_lock
);
283 * On Tegra124 and later, the clamps for the GPU are controlled by a
284 * separate register (with different semantics).
286 if (id
== TEGRA_POWERGATE_3D
) {
287 if (pmc
->soc
->has_gpu_clamps
) {
288 tegra_pmc_writel(0, GPU_RG_CNTRL
);
294 * Tegra 2 has a bug where PCIE and VDE clamping masks are
295 * swapped relatively to the partition ids
297 if (id
== TEGRA_POWERGATE_VDEC
)
298 mask
= (1 << TEGRA_POWERGATE_PCIE
);
299 else if (id
== TEGRA_POWERGATE_PCIE
)
300 mask
= (1 << TEGRA_POWERGATE_VDEC
);
304 tegra_pmc_writel(mask
, REMOVE_CLAMPING
);
307 mutex_unlock(&pmc
->powergates_lock
);
312 static void tegra_powergate_disable_clocks(struct tegra_powergate
*pg
)
316 for (i
= 0; i
< pg
->num_clks
; i
++)
317 clk_disable_unprepare(pg
->clks
[i
]);
320 static int tegra_powergate_enable_clocks(struct tegra_powergate
*pg
)
325 for (i
= 0; i
< pg
->num_clks
; i
++) {
326 err
= clk_prepare_enable(pg
->clks
[i
]);
335 clk_disable_unprepare(pg
->clks
[i
]);
340 static int tegra_powergate_reset_assert(struct tegra_powergate
*pg
)
345 for (i
= 0; i
< pg
->num_resets
; i
++) {
346 err
= reset_control_assert(pg
->resets
[i
]);
354 static int tegra_powergate_reset_deassert(struct tegra_powergate
*pg
)
359 for (i
= 0; i
< pg
->num_resets
; i
++) {
360 err
= reset_control_deassert(pg
->resets
[i
]);
368 static int tegra_powergate_power_up(struct tegra_powergate
*pg
,
373 err
= tegra_powergate_reset_assert(pg
);
377 usleep_range(10, 20);
379 err
= tegra_powergate_set(pg
->id
, true);
383 usleep_range(10, 20);
385 err
= tegra_powergate_enable_clocks(pg
);
389 usleep_range(10, 20);
391 err
= __tegra_powergate_remove_clamping(pg
->id
);
395 usleep_range(10, 20);
397 err
= tegra_powergate_reset_deassert(pg
);
401 usleep_range(10, 20);
404 tegra_powergate_disable_clocks(pg
);
409 tegra_powergate_disable_clocks(pg
);
410 usleep_range(10, 20);
413 tegra_powergate_set(pg
->id
, false);
418 static int tegra_powergate_power_down(struct tegra_powergate
*pg
)
422 err
= tegra_powergate_enable_clocks(pg
);
426 usleep_range(10, 20);
428 err
= tegra_powergate_reset_assert(pg
);
432 usleep_range(10, 20);
434 tegra_powergate_disable_clocks(pg
);
436 usleep_range(10, 20);
438 err
= tegra_powergate_set(pg
->id
, false);
445 tegra_powergate_enable_clocks(pg
);
446 usleep_range(10, 20);
447 tegra_powergate_reset_deassert(pg
);
448 usleep_range(10, 20);
451 tegra_powergate_disable_clocks(pg
);
456 static int tegra_genpd_power_on(struct generic_pm_domain
*domain
)
458 struct tegra_powergate
*pg
= to_powergate(domain
);
459 struct tegra_pmc
*pmc
= pg
->pmc
;
462 err
= tegra_powergate_power_up(pg
, true);
464 dev_err(pmc
->dev
, "failed to turn on PM domain %s: %d\n",
465 pg
->genpd
.name
, err
);
470 static int tegra_genpd_power_off(struct generic_pm_domain
*domain
)
472 struct tegra_powergate
*pg
= to_powergate(domain
);
473 struct tegra_pmc
*pmc
= pg
->pmc
;
476 err
= tegra_powergate_power_down(pg
);
478 dev_err(pmc
->dev
, "failed to turn off PM domain %s: %d\n",
479 pg
->genpd
.name
, err
);
485 * tegra_powergate_power_on() - power on partition
488 int tegra_powergate_power_on(unsigned int id
)
490 if (!tegra_powergate_is_available(id
))
493 return tegra_powergate_set(id
, true);
497 * tegra_powergate_power_off() - power off partition
500 int tegra_powergate_power_off(unsigned int id
)
502 if (!tegra_powergate_is_available(id
))
505 return tegra_powergate_set(id
, false);
507 EXPORT_SYMBOL(tegra_powergate_power_off
);
510 * tegra_powergate_is_powered() - check if partition is powered
513 int tegra_powergate_is_powered(unsigned int id
)
517 if (!tegra_powergate_is_valid(id
))
520 mutex_lock(&pmc
->powergates_lock
);
521 status
= tegra_powergate_state(id
);
522 mutex_unlock(&pmc
->powergates_lock
);
528 * tegra_powergate_remove_clamping() - remove power clamps for partition
531 int tegra_powergate_remove_clamping(unsigned int id
)
533 if (!tegra_powergate_is_available(id
))
536 return __tegra_powergate_remove_clamping(id
);
538 EXPORT_SYMBOL(tegra_powergate_remove_clamping
);
541 * tegra_powergate_sequence_power_up() - power up partition
543 * @clk: clock for partition
544 * @rst: reset for partition
546 * Must be called with clk disabled, and returns with clk enabled.
548 int tegra_powergate_sequence_power_up(unsigned int id
, struct clk
*clk
,
549 struct reset_control
*rst
)
551 struct tegra_powergate pg
;
554 if (!tegra_powergate_is_available(id
))
563 err
= tegra_powergate_power_up(&pg
, false);
565 pr_err("failed to turn on partition %d: %d\n", id
, err
);
569 EXPORT_SYMBOL(tegra_powergate_sequence_power_up
);
573 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
574 * @cpuid: CPU partition ID
576 * Returns the partition ID corresponding to the CPU partition ID or a
577 * negative error code on failure.
579 static int tegra_get_cpu_powergate_id(unsigned int cpuid
)
581 if (pmc
->soc
&& cpuid
< pmc
->soc
->num_cpu_powergates
)
582 return pmc
->soc
->cpu_powergates
[cpuid
];
588 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
589 * @cpuid: CPU partition ID
591 bool tegra_pmc_cpu_is_powered(unsigned int cpuid
)
595 id
= tegra_get_cpu_powergate_id(cpuid
);
599 return tegra_powergate_is_powered(id
);
603 * tegra_pmc_cpu_power_on() - power on CPU partition
604 * @cpuid: CPU partition ID
606 int tegra_pmc_cpu_power_on(unsigned int cpuid
)
610 id
= tegra_get_cpu_powergate_id(cpuid
);
614 return tegra_powergate_set(id
, true);
618 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
619 * @cpuid: CPU partition ID
621 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid
)
625 id
= tegra_get_cpu_powergate_id(cpuid
);
629 return tegra_powergate_remove_clamping(id
);
631 #endif /* CONFIG_SMP */
633 static int tegra_pmc_restart_notify(struct notifier_block
*this,
634 unsigned long action
, void *data
)
636 const char *cmd
= data
;
639 value
= tegra_pmc_readl(PMC_SCRATCH0
);
640 value
&= ~PMC_SCRATCH0_MODE_MASK
;
643 if (strcmp(cmd
, "recovery") == 0)
644 value
|= PMC_SCRATCH0_MODE_RECOVERY
;
646 if (strcmp(cmd
, "bootloader") == 0)
647 value
|= PMC_SCRATCH0_MODE_BOOTLOADER
;
649 if (strcmp(cmd
, "forced-recovery") == 0)
650 value
|= PMC_SCRATCH0_MODE_RCM
;
653 tegra_pmc_writel(value
, PMC_SCRATCH0
);
655 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
656 value
= tegra_pmc_readl(PMC_CNTRL
);
657 value
|= PMC_CNTRL_MAIN_RST
;
658 tegra_pmc_writel(value
, PMC_CNTRL
);
663 static struct notifier_block tegra_pmc_restart_handler
= {
664 .notifier_call
= tegra_pmc_restart_notify
,
668 static int powergate_show(struct seq_file
*s
, void *data
)
673 seq_printf(s
, " powergate powered\n");
674 seq_printf(s
, "------------------\n");
676 for (i
= 0; i
< pmc
->soc
->num_powergates
; i
++) {
677 status
= tegra_powergate_is_powered(i
);
681 seq_printf(s
, " %9s %7s\n", pmc
->soc
->powergates
[i
],
682 status
? "yes" : "no");
688 static int powergate_open(struct inode
*inode
, struct file
*file
)
690 return single_open(file
, powergate_show
, inode
->i_private
);
693 static const struct file_operations powergate_fops
= {
694 .open
= powergate_open
,
697 .release
= single_release
,
700 static int tegra_powergate_debugfs_init(void)
702 pmc
->debugfs
= debugfs_create_file("powergate", S_IRUGO
, NULL
, NULL
,
710 static int tegra_powergate_of_get_clks(struct tegra_powergate
*pg
,
711 struct device_node
*np
)
714 unsigned int i
, count
;
717 count
= of_count_phandle_with_args(np
, "clocks", "#clock-cells");
721 pg
->clks
= kcalloc(count
, sizeof(clk
), GFP_KERNEL
);
725 for (i
= 0; i
< count
; i
++) {
726 pg
->clks
[i
] = of_clk_get(np
, i
);
727 if (IS_ERR(pg
->clks
[i
])) {
728 err
= PTR_ERR(pg
->clks
[i
]);
733 pg
->num_clks
= count
;
739 clk_put(pg
->clks
[i
]);
746 static int tegra_powergate_of_get_resets(struct tegra_powergate
*pg
,
747 struct device_node
*np
, bool off
)
749 struct reset_control
*rst
;
750 unsigned int i
, count
;
753 count
= of_count_phandle_with_args(np
, "resets", "#reset-cells");
757 pg
->resets
= kcalloc(count
, sizeof(rst
), GFP_KERNEL
);
761 for (i
= 0; i
< count
; i
++) {
762 pg
->resets
[i
] = of_reset_control_get_by_index(np
, i
);
763 if (IS_ERR(pg
->resets
[i
])) {
764 err
= PTR_ERR(pg
->resets
[i
]);
769 err
= reset_control_assert(pg
->resets
[i
]);
771 err
= reset_control_deassert(pg
->resets
[i
]);
774 reset_control_put(pg
->resets
[i
]);
779 pg
->num_resets
= count
;
785 reset_control_put(pg
->resets
[i
]);
792 static void tegra_powergate_add(struct tegra_pmc
*pmc
, struct device_node
*np
)
794 struct tegra_powergate
*pg
;
798 pg
= kzalloc(sizeof(*pg
), GFP_KERNEL
);
802 id
= tegra_powergate_lookup(pmc
, np
->name
);
804 dev_err(pmc
->dev
, "powergate lookup failed for %s: %d\n",
810 * Clear the bit for this powergate so it cannot be managed
811 * directly via the legacy APIs for controlling powergates.
813 clear_bit(id
, pmc
->powergates_available
);
816 pg
->genpd
.name
= np
->name
;
817 pg
->genpd
.power_off
= tegra_genpd_power_off
;
818 pg
->genpd
.power_on
= tegra_genpd_power_on
;
821 off
= !tegra_powergate_is_powered(pg
->id
);
823 err
= tegra_powergate_of_get_clks(pg
, np
);
825 dev_err(pmc
->dev
, "failed to get clocks for %s: %d\n",
830 err
= tegra_powergate_of_get_resets(pg
, np
, off
);
832 dev_err(pmc
->dev
, "failed to get resets for %s: %d\n",
837 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS
))
838 goto power_on_cleanup
;
841 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
842 * host and super-speed partitions. Once the XHCI driver
843 * manages the partitions itself this code can be removed. Note
844 * that we don't register these partitions with the genpd core
845 * to avoid it from powering down the partitions as they appear
848 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA
) &&
849 (id
== TEGRA_POWERGATE_XUSBA
|| id
== TEGRA_POWERGATE_XUSBC
))
850 goto power_on_cleanup
;
852 pm_genpd_init(&pg
->genpd
, NULL
, off
);
854 err
= of_genpd_add_provider_simple(np
, &pg
->genpd
);
856 dev_err(pmc
->dev
, "failed to add genpd provider for %s: %d\n",
861 dev_dbg(pmc
->dev
, "added power domain %s\n", pg
->genpd
.name
);
867 WARN_ON(tegra_powergate_power_up(pg
, true));
870 while (pg
->num_resets
--)
871 reset_control_put(pg
->resets
[pg
->num_resets
]);
876 while (pg
->num_clks
--)
877 clk_put(pg
->clks
[pg
->num_clks
]);
882 set_bit(id
, pmc
->powergates_available
);
888 static void tegra_powergate_init(struct tegra_pmc
*pmc
,
889 struct device_node
*parent
)
891 struct device_node
*np
, *child
;
894 /* Create a bitmap of the available and valid partitions */
895 for (i
= 0; i
< pmc
->soc
->num_powergates
; i
++)
896 if (pmc
->soc
->powergates
[i
])
897 set_bit(i
, pmc
->powergates_available
);
899 np
= of_get_child_by_name(parent
, "powergates");
903 for_each_child_of_node(np
, child
) {
904 tegra_powergate_add(pmc
, child
);
911 static int tegra_io_rail_prepare(unsigned int id
, unsigned long *request
,
912 unsigned long *status
, unsigned int *bit
)
914 unsigned long rate
, value
;
919 * There are two sets of 30 bits to select IO rails, but bits 30 and
920 * 31 are control bits rather than IO rail selection bits.
922 if (id
> 63 || *bit
== 30 || *bit
== 31)
926 *status
= IO_DPD_STATUS
;
927 *request
= IO_DPD_REQ
;
929 *status
= IO_DPD2_STATUS
;
930 *request
= IO_DPD2_REQ
;
933 rate
= clk_get_rate(pmc
->clk
);
935 tegra_pmc_writel(DPD_SAMPLE_ENABLE
, DPD_SAMPLE
);
937 /* must be at least 200 ns, in APB (PCLK) clock cycles */
938 value
= DIV_ROUND_UP(1000000000, rate
);
939 value
= DIV_ROUND_UP(200, value
);
940 tegra_pmc_writel(value
, SEL_DPD_TIM
);
945 static int tegra_io_rail_poll(unsigned long offset
, unsigned long mask
,
946 unsigned long val
, unsigned long timeout
)
950 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
952 while (time_after(timeout
, jiffies
)) {
953 value
= tegra_pmc_readl(offset
);
954 if ((value
& mask
) == val
)
957 usleep_range(250, 1000);
963 static void tegra_io_rail_unprepare(void)
965 tegra_pmc_writel(DPD_SAMPLE_DISABLE
, DPD_SAMPLE
);
968 int tegra_io_rail_power_on(unsigned int id
)
970 unsigned long request
, status
;
974 mutex_lock(&pmc
->powergates_lock
);
976 err
= tegra_io_rail_prepare(id
, &request
, &status
, &bit
);
980 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF
| BIT(bit
), request
);
982 err
= tegra_io_rail_poll(status
, BIT(bit
), 0, 250);
984 pr_info("tegra_io_rail_poll() failed: %d\n", err
);
988 tegra_io_rail_unprepare();
991 mutex_unlock(&pmc
->powergates_lock
);
995 EXPORT_SYMBOL(tegra_io_rail_power_on
);
997 int tegra_io_rail_power_off(unsigned int id
)
999 unsigned long request
, status
;
1003 mutex_lock(&pmc
->powergates_lock
);
1005 err
= tegra_io_rail_prepare(id
, &request
, &status
, &bit
);
1007 pr_info("tegra_io_rail_prepare() failed: %d\n", err
);
1011 tegra_pmc_writel(IO_DPD_REQ_CODE_ON
| BIT(bit
), request
);
1013 err
= tegra_io_rail_poll(status
, BIT(bit
), BIT(bit
), 250);
1017 tegra_io_rail_unprepare();
1020 mutex_unlock(&pmc
->powergates_lock
);
1024 EXPORT_SYMBOL(tegra_io_rail_power_off
);
1026 #ifdef CONFIG_PM_SLEEP
1027 enum tegra_suspend_mode
tegra_pmc_get_suspend_mode(void)
1029 return pmc
->suspend_mode
;
1032 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode
)
1034 if (mode
< TEGRA_SUSPEND_NONE
|| mode
>= TEGRA_MAX_SUSPEND_MODE
)
1037 pmc
->suspend_mode
= mode
;
1040 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode
)
1042 unsigned long long rate
= 0;
1046 case TEGRA_SUSPEND_LP1
:
1050 case TEGRA_SUSPEND_LP2
:
1051 rate
= clk_get_rate(pmc
->clk
);
1058 if (WARN_ON_ONCE(rate
== 0))
1061 if (rate
!= pmc
->rate
) {
1064 ticks
= pmc
->cpu_good_time
* rate
+ USEC_PER_SEC
- 1;
1065 do_div(ticks
, USEC_PER_SEC
);
1066 tegra_pmc_writel(ticks
, PMC_CPUPWRGOOD_TIMER
);
1068 ticks
= pmc
->cpu_off_time
* rate
+ USEC_PER_SEC
- 1;
1069 do_div(ticks
, USEC_PER_SEC
);
1070 tegra_pmc_writel(ticks
, PMC_CPUPWROFF_TIMER
);
1077 value
= tegra_pmc_readl(PMC_CNTRL
);
1078 value
&= ~PMC_CNTRL_SIDE_EFFECT_LP0
;
1079 value
|= PMC_CNTRL_CPU_PWRREQ_OE
;
1080 tegra_pmc_writel(value
, PMC_CNTRL
);
1084 static int tegra_pmc_parse_dt(struct tegra_pmc
*pmc
, struct device_node
*np
)
1086 u32 value
, values
[2];
1088 if (of_property_read_u32(np
, "nvidia,suspend-mode", &value
)) {
1092 pmc
->suspend_mode
= TEGRA_SUSPEND_LP0
;
1096 pmc
->suspend_mode
= TEGRA_SUSPEND_LP1
;
1100 pmc
->suspend_mode
= TEGRA_SUSPEND_LP2
;
1104 pmc
->suspend_mode
= TEGRA_SUSPEND_NONE
;
1109 pmc
->suspend_mode
= tegra_pm_validate_suspend_mode(pmc
->suspend_mode
);
1111 if (of_property_read_u32(np
, "nvidia,cpu-pwr-good-time", &value
))
1112 pmc
->suspend_mode
= TEGRA_SUSPEND_NONE
;
1114 pmc
->cpu_good_time
= value
;
1116 if (of_property_read_u32(np
, "nvidia,cpu-pwr-off-time", &value
))
1117 pmc
->suspend_mode
= TEGRA_SUSPEND_NONE
;
1119 pmc
->cpu_off_time
= value
;
1121 if (of_property_read_u32_array(np
, "nvidia,core-pwr-good-time",
1122 values
, ARRAY_SIZE(values
)))
1123 pmc
->suspend_mode
= TEGRA_SUSPEND_NONE
;
1125 pmc
->core_osc_time
= values
[0];
1126 pmc
->core_pmu_time
= values
[1];
1128 if (of_property_read_u32(np
, "nvidia,core-pwr-off-time", &value
))
1129 pmc
->suspend_mode
= TEGRA_SUSPEND_NONE
;
1131 pmc
->core_off_time
= value
;
1133 pmc
->corereq_high
= of_property_read_bool(np
,
1134 "nvidia,core-power-req-active-high");
1136 pmc
->sysclkreq_high
= of_property_read_bool(np
,
1137 "nvidia,sys-clock-req-active-high");
1139 pmc
->combined_req
= of_property_read_bool(np
,
1140 "nvidia,combined-power-req");
1142 pmc
->cpu_pwr_good_en
= of_property_read_bool(np
,
1143 "nvidia,cpu-pwr-good-en");
1145 if (of_property_read_u32_array(np
, "nvidia,lp0-vec", values
,
1146 ARRAY_SIZE(values
)))
1147 if (pmc
->suspend_mode
== TEGRA_SUSPEND_LP0
)
1148 pmc
->suspend_mode
= TEGRA_SUSPEND_LP1
;
1150 pmc
->lp0_vec_phys
= values
[0];
1151 pmc
->lp0_vec_size
= values
[1];
1156 static void tegra_pmc_init(struct tegra_pmc
*pmc
)
1160 /* Always enable CPU power request */
1161 value
= tegra_pmc_readl(PMC_CNTRL
);
1162 value
|= PMC_CNTRL_CPU_PWRREQ_OE
;
1163 tegra_pmc_writel(value
, PMC_CNTRL
);
1165 value
= tegra_pmc_readl(PMC_CNTRL
);
1167 if (pmc
->sysclkreq_high
)
1168 value
&= ~PMC_CNTRL_SYSCLK_POLARITY
;
1170 value
|= PMC_CNTRL_SYSCLK_POLARITY
;
1172 /* configure the output polarity while the request is tristated */
1173 tegra_pmc_writel(value
, PMC_CNTRL
);
1175 /* now enable the request */
1176 value
= tegra_pmc_readl(PMC_CNTRL
);
1177 value
|= PMC_CNTRL_SYSCLK_OE
;
1178 tegra_pmc_writel(value
, PMC_CNTRL
);
1181 static void tegra_pmc_init_tsense_reset(struct tegra_pmc
*pmc
)
1183 static const char disabled
[] = "emergency thermal reset disabled";
1184 u32 pmu_addr
, ctrl_id
, reg_addr
, reg_data
, pinmux
;
1185 struct device
*dev
= pmc
->dev
;
1186 struct device_node
*np
;
1187 u32 value
, checksum
;
1189 if (!pmc
->soc
->has_tsense_reset
)
1192 np
= of_find_node_by_name(pmc
->dev
->of_node
, "i2c-thermtrip");
1194 dev_warn(dev
, "i2c-thermtrip node not found, %s.\n", disabled
);
1198 if (of_property_read_u32(np
, "nvidia,i2c-controller-id", &ctrl_id
)) {
1199 dev_err(dev
, "I2C controller ID missing, %s.\n", disabled
);
1203 if (of_property_read_u32(np
, "nvidia,bus-addr", &pmu_addr
)) {
1204 dev_err(dev
, "nvidia,bus-addr missing, %s.\n", disabled
);
1208 if (of_property_read_u32(np
, "nvidia,reg-addr", ®_addr
)) {
1209 dev_err(dev
, "nvidia,reg-addr missing, %s.\n", disabled
);
1213 if (of_property_read_u32(np
, "nvidia,reg-data", ®_data
)) {
1214 dev_err(dev
, "nvidia,reg-data missing, %s.\n", disabled
);
1218 if (of_property_read_u32(np
, "nvidia,pinmux-id", &pinmux
))
1221 value
= tegra_pmc_readl(PMC_SENSOR_CTRL
);
1222 value
|= PMC_SENSOR_CTRL_SCRATCH_WRITE
;
1223 tegra_pmc_writel(value
, PMC_SENSOR_CTRL
);
1225 value
= (reg_data
<< PMC_SCRATCH54_DATA_SHIFT
) |
1226 (reg_addr
<< PMC_SCRATCH54_ADDR_SHIFT
);
1227 tegra_pmc_writel(value
, PMC_SCRATCH54
);
1229 value
= PMC_SCRATCH55_RESET_TEGRA
;
1230 value
|= ctrl_id
<< PMC_SCRATCH55_CNTRL_ID_SHIFT
;
1231 value
|= pinmux
<< PMC_SCRATCH55_PINMUX_SHIFT
;
1232 value
|= pmu_addr
<< PMC_SCRATCH55_I2CSLV1_SHIFT
;
1235 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1236 * contain the checksum and are currently zero, so they are not added.
1238 checksum
= reg_addr
+ reg_data
+ (value
& 0xff) + ((value
>> 8) & 0xff)
1239 + ((value
>> 24) & 0xff);
1241 checksum
= 0x100 - checksum
;
1243 value
|= checksum
<< PMC_SCRATCH55_CHECKSUM_SHIFT
;
1245 tegra_pmc_writel(value
, PMC_SCRATCH55
);
1247 value
= tegra_pmc_readl(PMC_SENSOR_CTRL
);
1248 value
|= PMC_SENSOR_CTRL_ENABLE_RST
;
1249 tegra_pmc_writel(value
, PMC_SENSOR_CTRL
);
1251 dev_info(pmc
->dev
, "emergency thermal reset enabled\n");
1257 static int tegra_pmc_probe(struct platform_device
*pdev
)
1260 struct resource
*res
;
1264 * Early initialisation should have configured an initial
1265 * register mapping and setup the soc data pointer. If these
1266 * are not valid then something went badly wrong!
1268 if (WARN_ON(!pmc
->base
|| !pmc
->soc
))
1271 err
= tegra_pmc_parse_dt(pmc
, pdev
->dev
.of_node
);
1275 /* take over the memory region from the early initialization */
1276 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1277 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1279 return PTR_ERR(base
);
1281 pmc
->clk
= devm_clk_get(&pdev
->dev
, "pclk");
1282 if (IS_ERR(pmc
->clk
)) {
1283 err
= PTR_ERR(pmc
->clk
);
1284 dev_err(&pdev
->dev
, "failed to get pclk: %d\n", err
);
1288 pmc
->dev
= &pdev
->dev
;
1290 tegra_pmc_init(pmc
);
1292 tegra_pmc_init_tsense_reset(pmc
);
1294 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1295 err
= tegra_powergate_debugfs_init();
1300 err
= register_restart_handler(&tegra_pmc_restart_handler
);
1302 debugfs_remove(pmc
->debugfs
);
1303 dev_err(&pdev
->dev
, "unable to register restart handler, %d\n",
1308 mutex_lock(&pmc
->powergates_lock
);
1311 mutex_unlock(&pmc
->powergates_lock
);
1316 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1317 static int tegra_pmc_suspend(struct device
*dev
)
1319 tegra_pmc_writel(virt_to_phys(tegra_resume
), PMC_SCRATCH41
);
1324 static int tegra_pmc_resume(struct device
*dev
)
1326 tegra_pmc_writel(0x0, PMC_SCRATCH41
);
1331 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops
, tegra_pmc_suspend
, tegra_pmc_resume
);
1335 static const char * const tegra20_powergates
[] = {
1336 [TEGRA_POWERGATE_CPU
] = "cpu",
1337 [TEGRA_POWERGATE_3D
] = "3d",
1338 [TEGRA_POWERGATE_VENC
] = "venc",
1339 [TEGRA_POWERGATE_VDEC
] = "vdec",
1340 [TEGRA_POWERGATE_PCIE
] = "pcie",
1341 [TEGRA_POWERGATE_L2
] = "l2",
1342 [TEGRA_POWERGATE_MPE
] = "mpe",
1345 static const struct tegra_pmc_soc tegra20_pmc_soc
= {
1346 .num_powergates
= ARRAY_SIZE(tegra20_powergates
),
1347 .powergates
= tegra20_powergates
,
1348 .num_cpu_powergates
= 0,
1349 .cpu_powergates
= NULL
,
1350 .has_tsense_reset
= false,
1351 .has_gpu_clamps
= false,
1354 static const char * const tegra30_powergates
[] = {
1355 [TEGRA_POWERGATE_CPU
] = "cpu0",
1356 [TEGRA_POWERGATE_3D
] = "3d0",
1357 [TEGRA_POWERGATE_VENC
] = "venc",
1358 [TEGRA_POWERGATE_VDEC
] = "vdec",
1359 [TEGRA_POWERGATE_PCIE
] = "pcie",
1360 [TEGRA_POWERGATE_L2
] = "l2",
1361 [TEGRA_POWERGATE_MPE
] = "mpe",
1362 [TEGRA_POWERGATE_HEG
] = "heg",
1363 [TEGRA_POWERGATE_SATA
] = "sata",
1364 [TEGRA_POWERGATE_CPU1
] = "cpu1",
1365 [TEGRA_POWERGATE_CPU2
] = "cpu2",
1366 [TEGRA_POWERGATE_CPU3
] = "cpu3",
1367 [TEGRA_POWERGATE_CELP
] = "celp",
1368 [TEGRA_POWERGATE_3D1
] = "3d1",
1371 static const u8 tegra30_cpu_powergates
[] = {
1372 TEGRA_POWERGATE_CPU
,
1373 TEGRA_POWERGATE_CPU1
,
1374 TEGRA_POWERGATE_CPU2
,
1375 TEGRA_POWERGATE_CPU3
,
1378 static const struct tegra_pmc_soc tegra30_pmc_soc
= {
1379 .num_powergates
= ARRAY_SIZE(tegra30_powergates
),
1380 .powergates
= tegra30_powergates
,
1381 .num_cpu_powergates
= ARRAY_SIZE(tegra30_cpu_powergates
),
1382 .cpu_powergates
= tegra30_cpu_powergates
,
1383 .has_tsense_reset
= true,
1384 .has_gpu_clamps
= false,
1387 static const char * const tegra114_powergates
[] = {
1388 [TEGRA_POWERGATE_CPU
] = "crail",
1389 [TEGRA_POWERGATE_3D
] = "3d",
1390 [TEGRA_POWERGATE_VENC
] = "venc",
1391 [TEGRA_POWERGATE_VDEC
] = "vdec",
1392 [TEGRA_POWERGATE_MPE
] = "mpe",
1393 [TEGRA_POWERGATE_HEG
] = "heg",
1394 [TEGRA_POWERGATE_CPU1
] = "cpu1",
1395 [TEGRA_POWERGATE_CPU2
] = "cpu2",
1396 [TEGRA_POWERGATE_CPU3
] = "cpu3",
1397 [TEGRA_POWERGATE_CELP
] = "celp",
1398 [TEGRA_POWERGATE_CPU0
] = "cpu0",
1399 [TEGRA_POWERGATE_C0NC
] = "c0nc",
1400 [TEGRA_POWERGATE_C1NC
] = "c1nc",
1401 [TEGRA_POWERGATE_DIS
] = "dis",
1402 [TEGRA_POWERGATE_DISB
] = "disb",
1403 [TEGRA_POWERGATE_XUSBA
] = "xusba",
1404 [TEGRA_POWERGATE_XUSBB
] = "xusbb",
1405 [TEGRA_POWERGATE_XUSBC
] = "xusbc",
1408 static const u8 tegra114_cpu_powergates
[] = {
1409 TEGRA_POWERGATE_CPU0
,
1410 TEGRA_POWERGATE_CPU1
,
1411 TEGRA_POWERGATE_CPU2
,
1412 TEGRA_POWERGATE_CPU3
,
1415 static const struct tegra_pmc_soc tegra114_pmc_soc
= {
1416 .num_powergates
= ARRAY_SIZE(tegra114_powergates
),
1417 .powergates
= tegra114_powergates
,
1418 .num_cpu_powergates
= ARRAY_SIZE(tegra114_cpu_powergates
),
1419 .cpu_powergates
= tegra114_cpu_powergates
,
1420 .has_tsense_reset
= true,
1421 .has_gpu_clamps
= false,
1424 static const char * const tegra124_powergates
[] = {
1425 [TEGRA_POWERGATE_CPU
] = "crail",
1426 [TEGRA_POWERGATE_3D
] = "3d",
1427 [TEGRA_POWERGATE_VENC
] = "venc",
1428 [TEGRA_POWERGATE_PCIE
] = "pcie",
1429 [TEGRA_POWERGATE_VDEC
] = "vdec",
1430 [TEGRA_POWERGATE_MPE
] = "mpe",
1431 [TEGRA_POWERGATE_HEG
] = "heg",
1432 [TEGRA_POWERGATE_SATA
] = "sata",
1433 [TEGRA_POWERGATE_CPU1
] = "cpu1",
1434 [TEGRA_POWERGATE_CPU2
] = "cpu2",
1435 [TEGRA_POWERGATE_CPU3
] = "cpu3",
1436 [TEGRA_POWERGATE_CELP
] = "celp",
1437 [TEGRA_POWERGATE_CPU0
] = "cpu0",
1438 [TEGRA_POWERGATE_C0NC
] = "c0nc",
1439 [TEGRA_POWERGATE_C1NC
] = "c1nc",
1440 [TEGRA_POWERGATE_SOR
] = "sor",
1441 [TEGRA_POWERGATE_DIS
] = "dis",
1442 [TEGRA_POWERGATE_DISB
] = "disb",
1443 [TEGRA_POWERGATE_XUSBA
] = "xusba",
1444 [TEGRA_POWERGATE_XUSBB
] = "xusbb",
1445 [TEGRA_POWERGATE_XUSBC
] = "xusbc",
1446 [TEGRA_POWERGATE_VIC
] = "vic",
1447 [TEGRA_POWERGATE_IRAM
] = "iram",
1450 static const u8 tegra124_cpu_powergates
[] = {
1451 TEGRA_POWERGATE_CPU0
,
1452 TEGRA_POWERGATE_CPU1
,
1453 TEGRA_POWERGATE_CPU2
,
1454 TEGRA_POWERGATE_CPU3
,
1457 static const struct tegra_pmc_soc tegra124_pmc_soc
= {
1458 .num_powergates
= ARRAY_SIZE(tegra124_powergates
),
1459 .powergates
= tegra124_powergates
,
1460 .num_cpu_powergates
= ARRAY_SIZE(tegra124_cpu_powergates
),
1461 .cpu_powergates
= tegra124_cpu_powergates
,
1462 .has_tsense_reset
= true,
1463 .has_gpu_clamps
= true,
1466 static const char * const tegra210_powergates
[] = {
1467 [TEGRA_POWERGATE_CPU
] = "crail",
1468 [TEGRA_POWERGATE_3D
] = "3d",
1469 [TEGRA_POWERGATE_VENC
] = "venc",
1470 [TEGRA_POWERGATE_PCIE
] = "pcie",
1471 [TEGRA_POWERGATE_MPE
] = "mpe",
1472 [TEGRA_POWERGATE_SATA
] = "sata",
1473 [TEGRA_POWERGATE_CPU1
] = "cpu1",
1474 [TEGRA_POWERGATE_CPU2
] = "cpu2",
1475 [TEGRA_POWERGATE_CPU3
] = "cpu3",
1476 [TEGRA_POWERGATE_CPU0
] = "cpu0",
1477 [TEGRA_POWERGATE_C0NC
] = "c0nc",
1478 [TEGRA_POWERGATE_SOR
] = "sor",
1479 [TEGRA_POWERGATE_DIS
] = "dis",
1480 [TEGRA_POWERGATE_DISB
] = "disb",
1481 [TEGRA_POWERGATE_XUSBA
] = "xusba",
1482 [TEGRA_POWERGATE_XUSBB
] = "xusbb",
1483 [TEGRA_POWERGATE_XUSBC
] = "xusbc",
1484 [TEGRA_POWERGATE_VIC
] = "vic",
1485 [TEGRA_POWERGATE_IRAM
] = "iram",
1486 [TEGRA_POWERGATE_NVDEC
] = "nvdec",
1487 [TEGRA_POWERGATE_NVJPG
] = "nvjpg",
1488 [TEGRA_POWERGATE_AUD
] = "aud",
1489 [TEGRA_POWERGATE_DFD
] = "dfd",
1490 [TEGRA_POWERGATE_VE2
] = "ve2",
1493 static const u8 tegra210_cpu_powergates
[] = {
1494 TEGRA_POWERGATE_CPU0
,
1495 TEGRA_POWERGATE_CPU1
,
1496 TEGRA_POWERGATE_CPU2
,
1497 TEGRA_POWERGATE_CPU3
,
1500 static const struct tegra_pmc_soc tegra210_pmc_soc
= {
1501 .num_powergates
= ARRAY_SIZE(tegra210_powergates
),
1502 .powergates
= tegra210_powergates
,
1503 .num_cpu_powergates
= ARRAY_SIZE(tegra210_cpu_powergates
),
1504 .cpu_powergates
= tegra210_cpu_powergates
,
1505 .has_tsense_reset
= true,
1506 .has_gpu_clamps
= true,
1509 static const struct of_device_id tegra_pmc_match
[] = {
1510 { .compatible
= "nvidia,tegra210-pmc", .data
= &tegra210_pmc_soc
},
1511 { .compatible
= "nvidia,tegra132-pmc", .data
= &tegra124_pmc_soc
},
1512 { .compatible
= "nvidia,tegra124-pmc", .data
= &tegra124_pmc_soc
},
1513 { .compatible
= "nvidia,tegra114-pmc", .data
= &tegra114_pmc_soc
},
1514 { .compatible
= "nvidia,tegra30-pmc", .data
= &tegra30_pmc_soc
},
1515 { .compatible
= "nvidia,tegra20-pmc", .data
= &tegra20_pmc_soc
},
1519 static struct platform_driver tegra_pmc_driver
= {
1521 .name
= "tegra-pmc",
1522 .suppress_bind_attrs
= true,
1523 .of_match_table
= tegra_pmc_match
,
1524 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1525 .pm
= &tegra_pmc_pm_ops
,
1528 .probe
= tegra_pmc_probe
,
1530 builtin_platform_driver(tegra_pmc_driver
);
1533 * Early initialization to allow access to registers in the very early boot
1536 static int __init
tegra_pmc_early_init(void)
1538 const struct of_device_id
*match
;
1539 struct device_node
*np
;
1540 struct resource regs
;
1544 mutex_init(&pmc
->powergates_lock
);
1546 np
= of_find_matching_node_and_match(NULL
, tegra_pmc_match
, &match
);
1549 * Fall back to legacy initialization for 32-bit ARM only. All
1550 * 64-bit ARM device tree files for Tegra are required to have
1553 * This is for backwards-compatibility with old device trees
1554 * that didn't contain a PMC node. Note that in this case the
1555 * SoC data can't be matched and therefore powergating is
1558 if (IS_ENABLED(CONFIG_ARM
) && soc_is_tegra()) {
1559 pr_warn("DT node not found, powergating disabled\n");
1561 regs
.start
= 0x7000e400;
1562 regs
.end
= 0x7000e7ff;
1563 regs
.flags
= IORESOURCE_MEM
;
1565 pr_warn("Using memory region %pR\n", ®s
);
1568 * At this point we're not running on Tegra, so play
1569 * nice with multi-platform kernels.
1575 * Extract information from the device tree if we've found a
1578 if (of_address_to_resource(np
, 0, ®s
) < 0) {
1579 pr_err("failed to get PMC registers\n");
1585 pmc
->base
= ioremap_nocache(regs
.start
, resource_size(®s
));
1587 pr_err("failed to map PMC registers\n");
1593 pmc
->soc
= match
->data
;
1595 tegra_powergate_init(pmc
, np
);
1598 * Invert the interrupt polarity if a PMC device tree node
1599 * exists and contains the nvidia,invert-interrupt property.
1601 invert
= of_property_read_bool(np
, "nvidia,invert-interrupt");
1603 value
= tegra_pmc_readl(PMC_CNTRL
);
1606 value
|= PMC_CNTRL_INTR_POLARITY
;
1608 value
&= ~PMC_CNTRL_INTR_POLARITY
;
1610 tegra_pmc_writel(value
, PMC_CNTRL
);
1617 early_initcall(tegra_pmc_early_init
);