2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/spinlock.h>
20 #include <linux/workqueue.h>
21 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_bitbang.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/clk.h>
28 #include <linux/err.h>
30 #include <asm/mach-ath79/ar71xx_regs.h>
31 #include <asm/mach-ath79/ath79_spi_platform.h>
33 #define DRV_NAME "ath79-spi"
35 #define ATH79_SPI_RRW_DELAY_FACTOR 12000
36 #define MHZ (1000 * 1000)
39 struct spi_bitbang bitbang
;
47 static inline u32
ath79_spi_rr(struct ath79_spi
*sp
, unsigned reg
)
49 return ioread32(sp
->base
+ reg
);
52 static inline void ath79_spi_wr(struct ath79_spi
*sp
, unsigned reg
, u32 val
)
54 iowrite32(val
, sp
->base
+ reg
);
57 static inline struct ath79_spi
*ath79_spidev_to_sp(struct spi_device
*spi
)
59 return spi_master_get_devdata(spi
->master
);
62 static inline void ath79_spi_delay(struct ath79_spi
*sp
, unsigned nsecs
)
64 if (nsecs
> sp
->rrw_delay
)
65 ndelay(nsecs
- sp
->rrw_delay
);
68 static void ath79_spi_chipselect(struct spi_device
*spi
, int is_active
)
70 struct ath79_spi
*sp
= ath79_spidev_to_sp(spi
);
71 int cs_high
= (spi
->mode
& SPI_CS_HIGH
) ? is_active
: !is_active
;
74 /* set initial clock polarity */
75 if (spi
->mode
& SPI_CPOL
)
76 sp
->ioc_base
|= AR71XX_SPI_IOC_CLK
;
78 sp
->ioc_base
&= ~AR71XX_SPI_IOC_CLK
;
80 ath79_spi_wr(sp
, AR71XX_SPI_REG_IOC
, sp
->ioc_base
);
83 if (spi
->chip_select
) {
84 struct ath79_spi_controller_data
*cdata
= spi
->controller_data
;
86 /* SPI is normally active-low */
87 gpio_set_value(cdata
->gpio
, cs_high
);
90 sp
->ioc_base
|= AR71XX_SPI_IOC_CS0
;
92 sp
->ioc_base
&= ~AR71XX_SPI_IOC_CS0
;
94 ath79_spi_wr(sp
, AR71XX_SPI_REG_IOC
, sp
->ioc_base
);
99 static void ath79_spi_enable(struct ath79_spi
*sp
)
101 /* enable GPIO mode */
102 ath79_spi_wr(sp
, AR71XX_SPI_REG_FS
, AR71XX_SPI_FS_GPIO
);
104 /* save CTRL register */
105 sp
->reg_ctrl
= ath79_spi_rr(sp
, AR71XX_SPI_REG_CTRL
);
106 sp
->ioc_base
= ath79_spi_rr(sp
, AR71XX_SPI_REG_IOC
);
108 /* TODO: setup speed? */
109 ath79_spi_wr(sp
, AR71XX_SPI_REG_CTRL
, 0x43);
112 static void ath79_spi_disable(struct ath79_spi
*sp
)
114 /* restore CTRL register */
115 ath79_spi_wr(sp
, AR71XX_SPI_REG_CTRL
, sp
->reg_ctrl
);
116 /* disable GPIO mode */
117 ath79_spi_wr(sp
, AR71XX_SPI_REG_FS
, 0);
120 static int ath79_spi_setup_cs(struct spi_device
*spi
)
122 struct ath79_spi_controller_data
*cdata
;
125 cdata
= spi
->controller_data
;
126 if (spi
->chip_select
&& !cdata
)
130 if (spi
->chip_select
) {
133 flags
= GPIOF_DIR_OUT
;
134 if (spi
->mode
& SPI_CS_HIGH
)
135 flags
|= GPIOF_INIT_HIGH
;
137 flags
|= GPIOF_INIT_LOW
;
139 status
= gpio_request_one(cdata
->gpio
, flags
,
140 dev_name(&spi
->dev
));
146 static void ath79_spi_cleanup_cs(struct spi_device
*spi
)
148 if (spi
->chip_select
) {
149 struct ath79_spi_controller_data
*cdata
= spi
->controller_data
;
150 gpio_free(cdata
->gpio
);
154 static int ath79_spi_setup(struct spi_device
*spi
)
158 if (spi
->bits_per_word
> 32)
161 if (!spi
->controller_state
) {
162 status
= ath79_spi_setup_cs(spi
);
167 status
= spi_bitbang_setup(spi
);
168 if (status
&& !spi
->controller_state
)
169 ath79_spi_cleanup_cs(spi
);
174 static void ath79_spi_cleanup(struct spi_device
*spi
)
176 ath79_spi_cleanup_cs(spi
);
177 spi_bitbang_cleanup(spi
);
180 static u32
ath79_spi_txrx_mode0(struct spi_device
*spi
, unsigned nsecs
,
183 struct ath79_spi
*sp
= ath79_spidev_to_sp(spi
);
184 u32 ioc
= sp
->ioc_base
;
186 /* clock starts at inactive polarity */
187 for (word
<<= (32 - bits
); likely(bits
); bits
--) {
190 if (word
& (1 << 31))
191 out
= ioc
| AR71XX_SPI_IOC_DO
;
193 out
= ioc
& ~AR71XX_SPI_IOC_DO
;
195 /* setup MSB (to slave) on trailing edge */
196 ath79_spi_wr(sp
, AR71XX_SPI_REG_IOC
, out
);
197 ath79_spi_delay(sp
, nsecs
);
198 ath79_spi_wr(sp
, AR71XX_SPI_REG_IOC
, out
| AR71XX_SPI_IOC_CLK
);
199 ath79_spi_delay(sp
, nsecs
);
201 ath79_spi_wr(sp
, AR71XX_SPI_REG_IOC
, out
);
206 return ath79_spi_rr(sp
, AR71XX_SPI_REG_RDS
);
209 static int ath79_spi_probe(struct platform_device
*pdev
)
211 struct spi_master
*master
;
212 struct ath79_spi
*sp
;
213 struct ath79_spi_platform_data
*pdata
;
218 master
= spi_alloc_master(&pdev
->dev
, sizeof(*sp
));
219 if (master
== NULL
) {
220 dev_err(&pdev
->dev
, "failed to allocate spi master\n");
224 sp
= spi_master_get_devdata(master
);
225 platform_set_drvdata(pdev
, sp
);
227 pdata
= pdev
->dev
.platform_data
;
229 master
->setup
= ath79_spi_setup
;
230 master
->cleanup
= ath79_spi_cleanup
;
232 master
->bus_num
= pdata
->bus_num
;
233 master
->num_chipselect
= pdata
->num_chipselect
;
236 sp
->bitbang
.master
= spi_master_get(master
);
237 sp
->bitbang
.chipselect
= ath79_spi_chipselect
;
238 sp
->bitbang
.txrx_word
[SPI_MODE_0
] = ath79_spi_txrx_mode0
;
239 sp
->bitbang
.setup_transfer
= spi_bitbang_setup_transfer
;
240 sp
->bitbang
.flags
= SPI_CS_HIGH
;
242 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
248 sp
->base
= ioremap(r
->start
, resource_size(r
));
254 sp
->clk
= clk_get(&pdev
->dev
, "ahb");
255 if (IS_ERR(sp
->clk
)) {
256 ret
= PTR_ERR(sp
->clk
);
260 ret
= clk_enable(sp
->clk
);
264 rate
= DIV_ROUND_UP(clk_get_rate(sp
->clk
), MHZ
);
267 goto err_clk_disable
;
270 sp
->rrw_delay
= ATH79_SPI_RRW_DELAY_FACTOR
/ rate
;
271 dev_dbg(&pdev
->dev
, "register read/write delay is %u nsecs\n",
274 ath79_spi_enable(sp
);
275 ret
= spi_bitbang_start(&sp
->bitbang
);
282 ath79_spi_disable(sp
);
284 clk_disable(sp
->clk
);
290 spi_master_put(sp
->bitbang
.master
);
295 static int ath79_spi_remove(struct platform_device
*pdev
)
297 struct ath79_spi
*sp
= platform_get_drvdata(pdev
);
299 spi_bitbang_stop(&sp
->bitbang
);
300 ath79_spi_disable(sp
);
301 clk_disable(sp
->clk
);
304 spi_master_put(sp
->bitbang
.master
);
309 static void ath79_spi_shutdown(struct platform_device
*pdev
)
311 ath79_spi_remove(pdev
);
314 static struct platform_driver ath79_spi_driver
= {
315 .probe
= ath79_spi_probe
,
316 .remove
= ath79_spi_remove
,
317 .shutdown
= ath79_spi_shutdown
,
320 .owner
= THIS_MODULE
,
323 module_platform_driver(ath79_spi_driver
);
325 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
326 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
327 MODULE_LICENSE("GPL v2");
328 MODULE_ALIAS("platform:" DRV_NAME
);