drivers/spi/spi-bcm2835.c

   1 /*
   2  * Driver for Broadcom BCM2835 SPI Controllers
   3  *
   4  * Copyright (C) 2012 Chris Boot
   5  * Copyright (C) 2013 Stephen Warren
   6  *
   7  * This driver is inspired by:
   8  * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_device.h>
  33 #include <linux/spi/spi.h>
  34
  35 /* SPI register offsets */
  36 #define BCM2835_SPI_CS                  0x00
  37 #define BCM2835_SPI_FIFO                0x04
  38 #define BCM2835_SPI_CLK                 0x08
  39 #define BCM2835_SPI_DLEN                0x0c
  40 #define BCM2835_SPI_LTOH                0x10
  41 #define BCM2835_SPI_DC                  0x14
  42
  43 /* Bitfields in CS */
  44 #define BCM2835_SPI_CS_LEN_LONG         0x02000000
  45 #define BCM2835_SPI_CS_DMA_LEN          0x01000000
  46 #define BCM2835_SPI_CS_CSPOL2           0x00800000
  47 #define BCM2835_SPI_CS_CSPOL1           0x00400000
  48 #define BCM2835_SPI_CS_CSPOL0           0x00200000
  49 #define BCM2835_SPI_CS_RXF              0x00100000
  50 #define BCM2835_SPI_CS_RXR              0x00080000
  51 #define BCM2835_SPI_CS_TXD              0x00040000
  52 #define BCM2835_SPI_CS_RXD              0x00020000
  53 #define BCM2835_SPI_CS_DONE             0x00010000
  54 #define BCM2835_SPI_CS_LEN              0x00002000
  55 #define BCM2835_SPI_CS_REN              0x00001000
  56 #define BCM2835_SPI_CS_ADCS             0x00000800
  57 #define BCM2835_SPI_CS_INTR             0x00000400
  58 #define BCM2835_SPI_CS_INTD             0x00000200
  59 #define BCM2835_SPI_CS_DMAEN            0x00000100
  60 #define BCM2835_SPI_CS_TA               0x00000080
  61 #define BCM2835_SPI_CS_CSPOL            0x00000040
  62 #define BCM2835_SPI_CS_CLEAR_RX         0x00000020
  63 #define BCM2835_SPI_CS_CLEAR_TX         0x00000010
  64 #define BCM2835_SPI_CS_CPOL             0x00000008
  65 #define BCM2835_SPI_CS_CPHA             0x00000004
  66 #define BCM2835_SPI_CS_CS_10            0x00000002
  67 #define BCM2835_SPI_CS_CS_01            0x00000001
  68
  69 #define BCM2835_SPI_TIMEOUT_MS  30000
  70 #define BCM2835_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
  71                                 | SPI_NO_CS | SPI_3WIRE)
  72
  73 #define DRV_NAME        "spi-bcm2835"
  74
  75 struct bcm2835_spi {
  76         void __iomem *regs;
  77         struct clk *clk;
  78         int irq;
  79         struct completion done;
  80         const u8 *tx_buf;
  81         u8 *rx_buf;
  82         int len;
  83 };
  84
  85 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
  86 {
  87         return readl(bs->regs + reg);
  88 }
  89
  90 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
  91 {
  92         writel(val, bs->regs + reg);
  93 }
  94
  95 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
  96 {
  97         u8 byte;
  98
  99         while (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD) {
 100                 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
 101                 if (bs->rx_buf)
 102                         *bs->rx_buf++ = byte;
 103         }
 104 }
 105
 106 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
 107 {
 108         u8 byte;
 109
 110         while ((bs->len) &&
 111                (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
 112                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 113                 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
 114                 bs->len--;
 115         }
 116 }
 117
 118 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
 119 {
 120         struct spi_master *master = dev_id;
 121         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 122         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 123
 124         /* Read as many bytes as possible from FIFO */
 125         bcm2835_rd_fifo(bs);
 126
 127         if (bs->len) { /* there is more data to transmit */
 128                 bcm2835_wr_fifo(bs);
 129         } else { /* Transfer complete */
 130                 /* Disable SPI interrupts */
 131                 cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
 132                 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 133
 134                 /*
 135                  * Wake up bcm2835_spi_transfer_one(), which will call
 136                  * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
 137                  */
 138                 complete(&bs->done);
 139         }
 140
 141         return IRQ_HANDLED;
 142 }
 143
 144 static int bcm2835_spi_start_transfer(struct spi_device *spi,
 145                                       struct spi_transfer *tfr)
 146 {
 147         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
 148         unsigned long spi_hz, clk_hz, cdiv;
 149         u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
 150
 151         spi_hz = tfr->speed_hz;
 152         clk_hz = clk_get_rate(bs->clk);
 153
 154         if (spi_hz >= clk_hz / 2) {
 155                 cdiv = 2; /* clk_hz/2 is the fastest we can go */
 156         } else if (spi_hz) {
 157                 /* CDIV must be a multiple of two */
 158                 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
 159                 cdiv += (cdiv % 2);
 160
 161                 if (cdiv >= 65536)
 162                         cdiv = 0; /* 0 is the slowest we can go */
 163         } else {
 164                 cdiv = 0; /* 0 is the slowest we can go */
 165         }
 166
 167         if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
 168                 cs |= BCM2835_SPI_CS_REN;
 169
 170         if (spi->mode & SPI_CPOL)
 171                 cs |= BCM2835_SPI_CS_CPOL;
 172         if (spi->mode & SPI_CPHA)
 173                 cs |= BCM2835_SPI_CS_CPHA;
 174
 175         if (!(spi->mode & SPI_NO_CS)) {
 176                 if (spi->mode & SPI_CS_HIGH) {
 177                         cs |= BCM2835_SPI_CS_CSPOL;
 178                         cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
 179                 }
 180
 181                 cs |= spi->chip_select;
 182         }
 183
 184         reinit_completion(&bs->done);
 185         bs->tx_buf = tfr->tx_buf;
 186         bs->rx_buf = tfr->rx_buf;
 187         bs->len = tfr->len;
 188
 189         bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
 190         /*
 191          * Enable the HW block. This will immediately trigger a DONE (TX
 192          * empty) interrupt, upon which we will fill the TX FIFO with the
 193          * first TX bytes. Pre-filling the TX FIFO here to avoid the
 194          * interrupt doesn't work:-(
 195          */
 196         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 197
 198         return 0;
 199 }
 200
 201 static int bcm2835_spi_finish_transfer(struct spi_device *spi,
 202                                        struct spi_transfer *tfr,
 203                                        bool cs_change)
 204 {
 205         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
 206         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 207
 208         if (tfr->delay_usecs)
 209                 udelay(tfr->delay_usecs);
 210
 211         if (cs_change)
 212                 /* Clear TA flag */
 213                 bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
 214
 215         return 0;
 216 }
 217
 218 static int bcm2835_spi_transfer_one(struct spi_master *master,
 219                                     struct spi_message *mesg)
 220 {
 221         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 222         struct spi_transfer *tfr;
 223         struct spi_device *spi = mesg->spi;
 224         int err = 0;
 225         unsigned int timeout;
 226         bool cs_change;
 227
 228         list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
 229                 err = bcm2835_spi_start_transfer(spi, tfr);
 230                 if (err)
 231                         goto out;
 232
 233                 timeout = wait_for_completion_timeout(
 234                         &bs->done,
 235                         msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)
 236                         );
 237                 if (!timeout) {
 238                         err = -ETIMEDOUT;
 239                         goto out;
 240                 }
 241
 242                 cs_change = tfr->cs_change ||
 243                         list_is_last(&tfr->transfer_list, &mesg->transfers);
 244
 245                 err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
 246                 if (err)
 247                         goto out;
 248
 249                 mesg->actual_length += (tfr->len - bs->len);
 250         }
 251
 252 out:
 253         /* Clear FIFOs, and disable the HW block */
 254         bcm2835_wr(bs, BCM2835_SPI_CS,
 255                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 256         mesg->status = err;
 257         spi_finalize_current_message(master);
 258
 259         return 0;
 260 }
 261
 262 static int bcm2835_spi_probe(struct platform_device *pdev)
 263 {
 264         struct spi_master *master;
 265         struct bcm2835_spi *bs;
 266         struct resource *res;
 267         int err;
 268
 269         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 270         if (!master) {
 271                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
 272                 return -ENOMEM;
 273         }
 274
 275         platform_set_drvdata(pdev, master);
 276
 277         master->mode_bits = BCM2835_SPI_MODE_BITS;
 278         master->bits_per_word_mask = SPI_BPW_MASK(8);
 279         master->num_chipselect = 3;
 280         master->transfer_one_message = bcm2835_spi_transfer_one;
 281         master->dev.of_node = pdev->dev.of_node;
 282
 283         bs = spi_master_get_devdata(master);
 284
 285         init_completion(&bs->done);
 286
 287         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 288         bs->regs = devm_ioremap_resource(&pdev->dev, res);
 289         if (IS_ERR(bs->regs)) {
 290                 err = PTR_ERR(bs->regs);
 291                 goto out_master_put;
 292         }
 293
 294         bs->clk = devm_clk_get(&pdev->dev, NULL);
 295         if (IS_ERR(bs->clk)) {
 296                 err = PTR_ERR(bs->clk);
 297                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
 298                 goto out_master_put;
 299         }
 300
 301         bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 302         if (bs->irq <= 0) {
 303                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
 304                 err = bs->irq ? bs->irq : -ENODEV;
 305                 goto out_master_put;
 306         }
 307
 308         clk_prepare_enable(bs->clk);
 309
 310         err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
 311                                dev_name(&pdev->dev), master);
 312         if (err) {
 313                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 314                 goto out_clk_disable;
 315         }
 316
 317         /* initialise the hardware */
 318         bcm2835_wr(bs, BCM2835_SPI_CS,
 319                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 320
 321         err = devm_spi_register_master(&pdev->dev, master);
 322         if (err) {
 323                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
 324                 goto out_clk_disable;
 325         }
 326
 327         return 0;
 328
 329 out_clk_disable:
 330         clk_disable_unprepare(bs->clk);
 331 out_master_put:
 332         spi_master_put(master);
 333         return err;
 334 }
 335
 336 static int bcm2835_spi_remove(struct platform_device *pdev)
 337 {
 338         struct spi_master *master = platform_get_drvdata(pdev);
 339         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 340
 341         /* Clear FIFOs, and disable the HW block */
 342         bcm2835_wr(bs, BCM2835_SPI_CS,
 343                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 344
 345         clk_disable_unprepare(bs->clk);
 346
 347         return 0;
 348 }
 349
 350 static const struct of_device_id bcm2835_spi_match[] = {
 351         { .compatible = "brcm,bcm2835-spi", },
 352         {}
 353 };
 354 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
 355
 356 static struct platform_driver bcm2835_spi_driver = {
 357         .driver         = {
 358                 .name           = DRV_NAME,
 359                 .of_match_table = bcm2835_spi_match,
 360         },
 361         .probe          = bcm2835_spi_probe,
 362         .remove         = bcm2835_spi_remove,
 363 };
 364 module_platform_driver(bcm2835_spi_driver);
 365
 366 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
 367 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
 368 MODULE_LICENSE("GPL v2");