2 * Driver for Broadcom BCM2835 SPI Controllers
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
7 * This driver is inspired by:
8 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
9 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_device.h>
33 #include <linux/spi/spi.h>
35 /* SPI register offsets */
36 #define BCM2835_SPI_CS 0x00
37 #define BCM2835_SPI_FIFO 0x04
38 #define BCM2835_SPI_CLK 0x08
39 #define BCM2835_SPI_DLEN 0x0c
40 #define BCM2835_SPI_LTOH 0x10
41 #define BCM2835_SPI_DC 0x14
44 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
45 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
46 #define BCM2835_SPI_CS_CSPOL2 0x00800000
47 #define BCM2835_SPI_CS_CSPOL1 0x00400000
48 #define BCM2835_SPI_CS_CSPOL0 0x00200000
49 #define BCM2835_SPI_CS_RXF 0x00100000
50 #define BCM2835_SPI_CS_RXR 0x00080000
51 #define BCM2835_SPI_CS_TXD 0x00040000
52 #define BCM2835_SPI_CS_RXD 0x00020000
53 #define BCM2835_SPI_CS_DONE 0x00010000
54 #define BCM2835_SPI_CS_LEN 0x00002000
55 #define BCM2835_SPI_CS_REN 0x00001000
56 #define BCM2835_SPI_CS_ADCS 0x00000800
57 #define BCM2835_SPI_CS_INTR 0x00000400
58 #define BCM2835_SPI_CS_INTD 0x00000200
59 #define BCM2835_SPI_CS_DMAEN 0x00000100
60 #define BCM2835_SPI_CS_TA 0x00000080
61 #define BCM2835_SPI_CS_CSPOL 0x00000040
62 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
63 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
64 #define BCM2835_SPI_CS_CPOL 0x00000008
65 #define BCM2835_SPI_CS_CPHA 0x00000004
66 #define BCM2835_SPI_CS_CS_10 0x00000002
67 #define BCM2835_SPI_CS_CS_01 0x00000001
69 #define BCM2835_SPI_TIMEOUT_MS 30000
70 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)
72 #define DRV_NAME "spi-bcm2835"
78 struct completion done
;
84 static inline u32
bcm2835_rd(struct bcm2835_spi
*bs
, unsigned reg
)
86 return readl(bs
->regs
+ reg
);
89 static inline void bcm2835_wr(struct bcm2835_spi
*bs
, unsigned reg
, u32 val
)
91 writel(val
, bs
->regs
+ reg
);
94 static inline void bcm2835_rd_fifo(struct bcm2835_spi
*bs
)
98 while (bcm2835_rd(bs
, BCM2835_SPI_CS
) & BCM2835_SPI_CS_RXD
) {
99 byte
= bcm2835_rd(bs
, BCM2835_SPI_FIFO
);
101 *bs
->rx_buf
++ = byte
;
105 static inline void bcm2835_wr_fifo(struct bcm2835_spi
*bs
)
110 (bcm2835_rd(bs
, BCM2835_SPI_CS
) & BCM2835_SPI_CS_TXD
)) {
111 byte
= bs
->tx_buf
? *bs
->tx_buf
++ : 0;
112 bcm2835_wr(bs
, BCM2835_SPI_FIFO
, byte
);
117 static irqreturn_t
bcm2835_spi_interrupt(int irq
, void *dev_id
)
119 struct spi_master
*master
= dev_id
;
120 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
121 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
123 /* Read as many bytes as possible from FIFO */
126 if (bs
->len
) { /* there is more data to transmit */
128 } else { /* Transfer complete */
129 /* Disable SPI interrupts */
130 cs
&= ~(BCM2835_SPI_CS_INTR
| BCM2835_SPI_CS_INTD
);
131 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
134 * Wake up bcm2835_spi_transfer_one(), which will call
135 * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
143 static int bcm2835_spi_start_transfer(struct spi_device
*spi
,
144 struct spi_transfer
*tfr
)
146 struct bcm2835_spi
*bs
= spi_master_get_devdata(spi
->master
);
147 unsigned long spi_hz
, clk_hz
, cdiv
;
148 u32 cs
= BCM2835_SPI_CS_INTR
| BCM2835_SPI_CS_INTD
| BCM2835_SPI_CS_TA
;
150 spi_hz
= tfr
->speed_hz
;
151 clk_hz
= clk_get_rate(bs
->clk
);
153 if (spi_hz
>= clk_hz
/ 2) {
154 cdiv
= 2; /* clk_hz/2 is the fastest we can go */
156 /* CDIV must be a multiple of two */
157 cdiv
= DIV_ROUND_UP(clk_hz
, spi_hz
);
161 cdiv
= 0; /* 0 is the slowest we can go */
163 cdiv
= 0; /* 0 is the slowest we can go */
166 if (spi
->mode
& SPI_CPOL
)
167 cs
|= BCM2835_SPI_CS_CPOL
;
168 if (spi
->mode
& SPI_CPHA
)
169 cs
|= BCM2835_SPI_CS_CPHA
;
171 if (!(spi
->mode
& SPI_NO_CS
)) {
172 if (spi
->mode
& SPI_CS_HIGH
) {
173 cs
|= BCM2835_SPI_CS_CSPOL
;
174 cs
|= BCM2835_SPI_CS_CSPOL0
<< spi
->chip_select
;
177 cs
|= spi
->chip_select
;
180 reinit_completion(&bs
->done
);
181 bs
->tx_buf
= tfr
->tx_buf
;
182 bs
->rx_buf
= tfr
->rx_buf
;
185 bcm2835_wr(bs
, BCM2835_SPI_CLK
, cdiv
);
187 * Enable the HW block. This will immediately trigger a DONE (TX
188 * empty) interrupt, upon which we will fill the TX FIFO with the
189 * first TX bytes. Pre-filling the TX FIFO here to avoid the
190 * interrupt doesn't work:-(
192 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
197 static int bcm2835_spi_finish_transfer(struct spi_device
*spi
,
198 struct spi_transfer
*tfr
,
201 struct bcm2835_spi
*bs
= spi_master_get_devdata(spi
->master
);
202 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
204 if (tfr
->delay_usecs
)
205 udelay(tfr
->delay_usecs
);
209 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
& ~BCM2835_SPI_CS_TA
);
214 static int bcm2835_spi_transfer_one(struct spi_master
*master
,
215 struct spi_message
*mesg
)
217 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
218 struct spi_transfer
*tfr
;
219 struct spi_device
*spi
= mesg
->spi
;
221 unsigned int timeout
;
224 list_for_each_entry(tfr
, &mesg
->transfers
, transfer_list
) {
225 err
= bcm2835_spi_start_transfer(spi
, tfr
);
229 timeout
= wait_for_completion_timeout(
231 msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS
)
238 cs_change
= tfr
->cs_change
||
239 list_is_last(&tfr
->transfer_list
, &mesg
->transfers
);
241 err
= bcm2835_spi_finish_transfer(spi
, tfr
, cs_change
);
245 mesg
->actual_length
+= (tfr
->len
- bs
->len
);
249 /* Clear FIFOs, and disable the HW block */
250 bcm2835_wr(bs
, BCM2835_SPI_CS
,
251 BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
);
253 spi_finalize_current_message(master
);
258 static int bcm2835_spi_probe(struct platform_device
*pdev
)
260 struct spi_master
*master
;
261 struct bcm2835_spi
*bs
;
262 struct resource
*res
;
265 master
= spi_alloc_master(&pdev
->dev
, sizeof(*bs
));
267 dev_err(&pdev
->dev
, "spi_alloc_master() failed\n");
271 platform_set_drvdata(pdev
, master
);
273 master
->mode_bits
= BCM2835_SPI_MODE_BITS
;
274 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
275 master
->num_chipselect
= 3;
276 master
->transfer_one_message
= bcm2835_spi_transfer_one
;
277 master
->dev
.of_node
= pdev
->dev
.of_node
;
279 bs
= spi_master_get_devdata(master
);
281 init_completion(&bs
->done
);
283 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
284 bs
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
285 if (IS_ERR(bs
->regs
)) {
286 err
= PTR_ERR(bs
->regs
);
290 bs
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
291 if (IS_ERR(bs
->clk
)) {
292 err
= PTR_ERR(bs
->clk
);
293 dev_err(&pdev
->dev
, "could not get clk: %d\n", err
);
297 bs
->irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
299 dev_err(&pdev
->dev
, "could not get IRQ: %d\n", bs
->irq
);
300 err
= bs
->irq
? bs
->irq
: -ENODEV
;
304 clk_prepare_enable(bs
->clk
);
306 err
= devm_request_irq(&pdev
->dev
, bs
->irq
, bcm2835_spi_interrupt
, 0,
307 dev_name(&pdev
->dev
), master
);
309 dev_err(&pdev
->dev
, "could not request IRQ: %d\n", err
);
310 goto out_clk_disable
;
313 /* initialise the hardware */
314 bcm2835_wr(bs
, BCM2835_SPI_CS
,
315 BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
);
317 err
= devm_spi_register_master(&pdev
->dev
, master
);
319 dev_err(&pdev
->dev
, "could not register SPI master: %d\n", err
);
320 goto out_clk_disable
;
326 clk_disable_unprepare(bs
->clk
);
328 spi_master_put(master
);
332 static int bcm2835_spi_remove(struct platform_device
*pdev
)
334 struct spi_master
*master
= platform_get_drvdata(pdev
);
335 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
337 /* Clear FIFOs, and disable the HW block */
338 bcm2835_wr(bs
, BCM2835_SPI_CS
,
339 BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
);
341 clk_disable_unprepare(bs
->clk
);
346 static const struct of_device_id bcm2835_spi_match
[] = {
347 { .compatible
= "brcm,bcm2835-spi", },
350 MODULE_DEVICE_TABLE(of
, bcm2835_spi_match
);
352 static struct platform_driver bcm2835_spi_driver
= {
355 .of_match_table
= bcm2835_spi_match
,
357 .probe
= bcm2835_spi_probe
,
358 .remove
= bcm2835_spi_remove
,
360 module_platform_driver(bcm2835_spi_driver
);
362 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
363 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
364 MODULE_LICENSE("GPL v2");