drivers/spi/spi-bcm2835.c

   1 /*
   2  * Driver for Broadcom BCM2835 SPI Controllers
   3  *
   4  * Copyright (C) 2012 Chris Boot
   5  * Copyright (C) 2013 Stephen Warren
   6  *
   7  * This driver is inspired by:
   8  * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_device.h>
  33 #include <linux/spi/spi.h>
  34
  35 /* SPI register offsets */
  36 #define BCM2835_SPI_CS                  0x00
  37 #define BCM2835_SPI_FIFO                0x04
  38 #define BCM2835_SPI_CLK                 0x08
  39 #define BCM2835_SPI_DLEN                0x0c
  40 #define BCM2835_SPI_LTOH                0x10
  41 #define BCM2835_SPI_DC                  0x14
  42
  43 /* Bitfields in CS */
  44 #define BCM2835_SPI_CS_LEN_LONG         0x02000000
  45 #define BCM2835_SPI_CS_DMA_LEN          0x01000000
  46 #define BCM2835_SPI_CS_CSPOL2           0x00800000
  47 #define BCM2835_SPI_CS_CSPOL1           0x00400000
  48 #define BCM2835_SPI_CS_CSPOL0           0x00200000
  49 #define BCM2835_SPI_CS_RXF              0x00100000
  50 #define BCM2835_SPI_CS_RXR              0x00080000
  51 #define BCM2835_SPI_CS_TXD              0x00040000
  52 #define BCM2835_SPI_CS_RXD              0x00020000
  53 #define BCM2835_SPI_CS_DONE             0x00010000
  54 #define BCM2835_SPI_CS_LEN              0x00002000
  55 #define BCM2835_SPI_CS_REN              0x00001000
  56 #define BCM2835_SPI_CS_ADCS             0x00000800
  57 #define BCM2835_SPI_CS_INTR             0x00000400
  58 #define BCM2835_SPI_CS_INTD             0x00000200
  59 #define BCM2835_SPI_CS_DMAEN            0x00000100
  60 #define BCM2835_SPI_CS_TA               0x00000080
  61 #define BCM2835_SPI_CS_CSPOL            0x00000040
  62 #define BCM2835_SPI_CS_CLEAR_RX         0x00000020
  63 #define BCM2835_SPI_CS_CLEAR_TX         0x00000010
  64 #define BCM2835_SPI_CS_CPOL             0x00000008
  65 #define BCM2835_SPI_CS_CPHA             0x00000004
  66 #define BCM2835_SPI_CS_CS_10            0x00000002
  67 #define BCM2835_SPI_CS_CS_01            0x00000001
  68
  69 #define BCM2835_SPI_TIMEOUT_MS  30000
  70 #define BCM2835_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)
  71
  72 #define DRV_NAME        "spi-bcm2835"
  73
  74 struct bcm2835_spi {
  75         void __iomem *regs;
  76         struct clk *clk;
  77         int irq;
  78         struct completion done;
  79         const u8 *tx_buf;
  80         u8 *rx_buf;
  81         int len;
  82 };
  83
  84 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
  85 {
  86         return readl(bs->regs + reg);
  87 }
  88
  89 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
  90 {
  91         writel(val, bs->regs + reg);
  92 }
  93
  94 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len)
  95 {
  96         u8 byte;
  97
  98         while (len--) {
  99                 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
 100                 if (bs->rx_buf)
 101                         *bs->rx_buf++ = byte;
 102         }
 103 }
 104
 105 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len)
 106 {
 107         u8 byte;
 108
 109         if (len > bs->len)
 110                 len = bs->len;
 111
 112         while (len--) {
 113                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 114                 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
 115                 bs->len--;
 116         }
 117 }
 118
 119 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
 120 {
 121         struct spi_master *master = dev_id;
 122         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 123         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 124
 125         /*
 126          * RXR - RX needs Reading. This means 12 (or more) bytes have been
 127          * transmitted and hence 12 (or more) bytes have been received.
 128          *
 129          * The FIFO is 16-bytes deep. We check for this interrupt to keep the
 130          * FIFO full; we have a 4-byte-time buffer for IRQ latency. We check
 131          * this before DONE (TX empty) just in case we delayed processing this
 132          * interrupt for some reason.
 133          *
 134          * We only check for this case if we have more bytes to TX; at the end
 135          * of the transfer, we ignore this pipelining optimization, and let
 136          * bcm2835_spi_finish_transfer() drain the RX FIFO.
 137          */
 138         if (bs->len && (cs & BCM2835_SPI_CS_RXR)) {
 139                 /* Read 12 bytes of data */
 140                 bcm2835_rd_fifo(bs, 12);
 141
 142                 /* Write up to 12 bytes */
 143                 bcm2835_wr_fifo(bs, 12);
 144
 145                 /*
 146                  * We must have written something to the TX FIFO due to the
 147                  * bs->len check above, so cannot be DONE. Hence, return
 148                  * early. Note that DONE could also be set if we serviced an
 149                  * RXR interrupt really late.
 150                  */
 151                 return IRQ_HANDLED;
 152         }
 153
 154         /*
 155          * DONE - TX empty. This occurs when we first enable the transfer
 156          * since we do not pre-fill the TX FIFO. At any other time, given that
 157          * we refill the TX FIFO above based on RXR, and hence ignore DONE if
 158          * RXR is set, DONE really does mean end-of-transfer.
 159          */
 160         if (cs & BCM2835_SPI_CS_DONE) {
 161                 if (bs->len) { /* First interrupt in a transfer */
 162                         bcm2835_wr_fifo(bs, 16);
 163                 } else { /* Transfer complete */
 164                         /* Disable SPI interrupts */
 165                         cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
 166                         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 167
 168                         /*
 169                          * Wake up bcm2835_spi_transfer_one(), which will call
 170                          * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
 171                          */
 172                         complete(&bs->done);
 173                 }
 174
 175                 return IRQ_HANDLED;
 176         }
 177
 178         return IRQ_NONE;
 179 }
 180
 181 static int bcm2835_spi_start_transfer(struct spi_device *spi,
 182                 struct spi_transfer *tfr)
 183 {
 184         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
 185         unsigned long spi_hz, clk_hz, cdiv;
 186         u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
 187
 188         spi_hz = tfr->speed_hz;
 189         clk_hz = clk_get_rate(bs->clk);
 190
 191         if (spi_hz >= clk_hz / 2) {
 192                 cdiv = 2; /* clk_hz/2 is the fastest we can go */
 193         } else if (spi_hz) {
 194                 /* CDIV must be a power of two */
 195                 cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz));
 196
 197                 if (cdiv >= 65536)
 198                         cdiv = 0; /* 0 is the slowest we can go */
 199         } else
 200                 cdiv = 0; /* 0 is the slowest we can go */
 201
 202         if (spi->mode & SPI_CPOL)
 203                 cs |= BCM2835_SPI_CS_CPOL;
 204         if (spi->mode & SPI_CPHA)
 205                 cs |= BCM2835_SPI_CS_CPHA;
 206
 207         if (!(spi->mode & SPI_NO_CS)) {
 208                 if (spi->mode & SPI_CS_HIGH) {
 209                         cs |= BCM2835_SPI_CS_CSPOL;
 210                         cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
 211                 }
 212
 213                 cs |= spi->chip_select;
 214         }
 215
 216         reinit_completion(&bs->done);
 217         bs->tx_buf = tfr->tx_buf;
 218         bs->rx_buf = tfr->rx_buf;
 219         bs->len = tfr->len;
 220
 221         bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
 222         /*
 223          * Enable the HW block. This will immediately trigger a DONE (TX
 224          * empty) interrupt, upon which we will fill the TX FIFO with the
 225          * first TX bytes. Pre-filling the TX FIFO here to avoid the
 226          * interrupt doesn't work:-(
 227          */
 228         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 229
 230         return 0;
 231 }
 232
 233 static int bcm2835_spi_finish_transfer(struct spi_device *spi,
 234                 struct spi_transfer *tfr, bool cs_change)
 235 {
 236         struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
 237         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 238
 239         /* Drain RX FIFO */
 240         while (cs & BCM2835_SPI_CS_RXD) {
 241                 bcm2835_rd_fifo(bs, 1);
 242                 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 243         }
 244
 245         if (tfr->delay_usecs)
 246                 udelay(tfr->delay_usecs);
 247
 248         if (cs_change)
 249                 /* Clear TA flag */
 250                 bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
 251
 252         return 0;
 253 }
 254
 255 static int bcm2835_spi_transfer_one(struct spi_master *master,
 256                 struct spi_message *mesg)
 257 {
 258         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 259         struct spi_transfer *tfr;
 260         struct spi_device *spi = mesg->spi;
 261         int err = 0;
 262         unsigned int timeout;
 263         bool cs_change;
 264
 265         list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
 266                 err = bcm2835_spi_start_transfer(spi, tfr);
 267                 if (err)
 268                         goto out;
 269
 270                 timeout = wait_for_completion_timeout(&bs->done,
 271                                 msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS));
 272                 if (!timeout) {
 273                         err = -ETIMEDOUT;
 274                         goto out;
 275                 }
 276
 277                 cs_change = tfr->cs_change ||
 278                         list_is_last(&tfr->transfer_list, &mesg->transfers);
 279
 280                 err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
 281                 if (err)
 282                         goto out;
 283
 284                 mesg->actual_length += (tfr->len - bs->len);
 285         }
 286
 287 out:
 288         /* Clear FIFOs, and disable the HW block */
 289         bcm2835_wr(bs, BCM2835_SPI_CS,
 290                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 291         mesg->status = err;
 292         spi_finalize_current_message(master);
 293
 294         return 0;
 295 }
 296
 297 static int bcm2835_spi_probe(struct platform_device *pdev)
 298 {
 299         struct spi_master *master;
 300         struct bcm2835_spi *bs;
 301         struct resource *res;
 302         int err;
 303
 304         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 305         if (!master) {
 306                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
 307                 return -ENOMEM;
 308         }
 309
 310         platform_set_drvdata(pdev, master);
 311
 312         master->mode_bits = BCM2835_SPI_MODE_BITS;
 313         master->bits_per_word_mask = SPI_BPW_MASK(8);
 314         master->num_chipselect = 3;
 315         master->transfer_one_message = bcm2835_spi_transfer_one;
 316         master->dev.of_node = pdev->dev.of_node;
 317
 318         bs = spi_master_get_devdata(master);
 319
 320         init_completion(&bs->done);
 321
 322         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 323         bs->regs = devm_ioremap_resource(&pdev->dev, res);
 324         if (IS_ERR(bs->regs)) {
 325                 err = PTR_ERR(bs->regs);
 326                 goto out_master_put;
 327         }
 328
 329         bs->clk = devm_clk_get(&pdev->dev, NULL);
 330         if (IS_ERR(bs->clk)) {
 331                 err = PTR_ERR(bs->clk);
 332                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
 333                 goto out_master_put;
 334         }
 335
 336         bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 337         if (bs->irq <= 0) {
 338                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
 339                 err = bs->irq ? bs->irq : -ENODEV;
 340                 goto out_master_put;
 341         }
 342
 343         clk_prepare_enable(bs->clk);
 344
 345         err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
 346                                 dev_name(&pdev->dev), master);
 347         if (err) {
 348                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 349                 goto out_clk_disable;
 350         }
 351
 352         /* initialise the hardware */
 353         bcm2835_wr(bs, BCM2835_SPI_CS,
 354                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 355
 356         err = devm_spi_register_master(&pdev->dev, master);
 357         if (err) {
 358                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
 359                 goto out_clk_disable;
 360         }
 361
 362         return 0;
 363
 364 out_clk_disable:
 365         clk_disable_unprepare(bs->clk);
 366 out_master_put:
 367         spi_master_put(master);
 368         return err;
 369 }
 370
 371 static int bcm2835_spi_remove(struct platform_device *pdev)
 372 {
 373         struct spi_master *master = platform_get_drvdata(pdev);
 374         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 375
 376         /* Clear FIFOs, and disable the HW block */
 377         bcm2835_wr(bs, BCM2835_SPI_CS,
 378                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 379
 380         clk_disable_unprepare(bs->clk);
 381
 382         return 0;
 383 }
 384
 385 static const struct of_device_id bcm2835_spi_match[] = {
 386         { .compatible = "brcm,bcm2835-spi", },
 387         {}
 388 };
 389 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
 390
 391 static struct platform_driver bcm2835_spi_driver = {
 392         .driver         = {
 393                 .name           = DRV_NAME,
 394                 .of_match_table = bcm2835_spi_match,
 395         },
 396         .probe          = bcm2835_spi_probe,
 397         .remove         = bcm2835_spi_remove,
 398 };
 399 module_platform_driver(bcm2835_spi_driver);
 400
 401 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
 402 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
 403 MODULE_LICENSE("GPL v2");