2 * Broadcom BCM63xx SPI controller support
4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/spi/spi.h>
30 #include <linux/completion.h>
31 #include <linux/err.h>
32 #include <linux/pm_runtime.h>
34 #include <bcm63xx_dev_spi.h>
36 #define BCM63XX_SPI_MAX_PREPEND 15
39 struct completion done
;
46 unsigned int msg_type_shift
;
47 unsigned int msg_ctl_width
;
51 const u8 __iomem
*rx_io
;
54 struct platform_device
*pdev
;
57 static inline u8
bcm_spi_readb(struct bcm63xx_spi
*bs
,
60 return bcm_readb(bs
->regs
+ bcm63xx_spireg(offset
));
63 static inline u16
bcm_spi_readw(struct bcm63xx_spi
*bs
,
66 return bcm_readw(bs
->regs
+ bcm63xx_spireg(offset
));
69 static inline void bcm_spi_writeb(struct bcm63xx_spi
*bs
,
70 u8 value
, unsigned int offset
)
72 bcm_writeb(value
, bs
->regs
+ bcm63xx_spireg(offset
));
75 static inline void bcm_spi_writew(struct bcm63xx_spi
*bs
,
76 u16 value
, unsigned int offset
)
78 bcm_writew(value
, bs
->regs
+ bcm63xx_spireg(offset
));
81 static const unsigned bcm63xx_spi_freq_table
[SPI_CLK_MASK
][2] = {
82 { 20000000, SPI_CLK_20MHZ
},
83 { 12500000, SPI_CLK_12_50MHZ
},
84 { 6250000, SPI_CLK_6_250MHZ
},
85 { 3125000, SPI_CLK_3_125MHZ
},
86 { 1563000, SPI_CLK_1_563MHZ
},
87 { 781000, SPI_CLK_0_781MHZ
},
88 { 391000, SPI_CLK_0_391MHZ
}
91 static void bcm63xx_spi_setup_transfer(struct spi_device
*spi
,
92 struct spi_transfer
*t
)
94 struct bcm63xx_spi
*bs
= spi_master_get_devdata(spi
->master
);
98 /* Find the closest clock configuration */
99 for (i
= 0; i
< SPI_CLK_MASK
; i
++) {
100 if (t
->speed_hz
>= bcm63xx_spi_freq_table
[i
][0]) {
101 clk_cfg
= bcm63xx_spi_freq_table
[i
][1];
106 /* No matching configuration found, default to lowest */
107 if (i
== SPI_CLK_MASK
)
108 clk_cfg
= SPI_CLK_0_391MHZ
;
110 /* clear existing clock configuration bits of the register */
111 reg
= bcm_spi_readb(bs
, SPI_CLK_CFG
);
112 reg
&= ~SPI_CLK_MASK
;
115 bcm_spi_writeb(bs
, reg
, SPI_CLK_CFG
);
116 dev_dbg(&spi
->dev
, "Setting clock register to %02x (hz %d)\n",
117 clk_cfg
, t
->speed_hz
);
120 /* the spi->mode bits understood by this driver: */
121 #define MODEBITS (SPI_CPOL | SPI_CPHA)
123 static int bcm63xx_txrx_bufs(struct spi_device
*spi
, struct spi_transfer
*first
,
124 unsigned int num_transfers
)
126 struct bcm63xx_spi
*bs
= spi_master_get_devdata(spi
->master
);
130 unsigned int i
, timeout
= 0, prepend_len
= 0, len
= 0;
131 struct spi_transfer
*t
= first
;
135 /* Disable the CMD_DONE interrupt */
136 bcm_spi_writeb(bs
, 0, SPI_INT_MASK
);
138 dev_dbg(&spi
->dev
, "txrx: tx %p, rx %p, len %d\n",
139 t
->tx_buf
, t
->rx_buf
, t
->len
);
141 if (num_transfers
> 1 && t
->tx_buf
&& t
->len
<= BCM63XX_SPI_MAX_PREPEND
)
142 prepend_len
= t
->len
;
144 /* prepare the buffer */
145 for (i
= 0; i
< num_transfers
; i
++) {
148 memcpy_toio(bs
->tx_io
+ len
, t
->tx_buf
, t
->len
);
150 /* don't prepend more than one tx */
157 /* prepend is half-duplex write only */
164 t
= list_entry(t
->transfer_list
.next
, struct spi_transfer
,
168 reinit_completion(&bs
->done
);
170 /* Fill in the Message control register */
171 msg_ctl
= (len
<< SPI_BYTE_CNT_SHIFT
);
173 if (do_rx
&& do_tx
&& prepend_len
== 0)
174 msg_ctl
|= (SPI_FD_RW
<< bs
->msg_type_shift
);
176 msg_ctl
|= (SPI_HD_R
<< bs
->msg_type_shift
);
178 msg_ctl
|= (SPI_HD_W
<< bs
->msg_type_shift
);
180 switch (bs
->msg_ctl_width
) {
182 bcm_spi_writeb(bs
, msg_ctl
, SPI_MSG_CTL
);
185 bcm_spi_writew(bs
, msg_ctl
, SPI_MSG_CTL
);
189 /* Issue the transfer */
190 cmd
= SPI_CMD_START_IMMEDIATE
;
191 cmd
|= (prepend_len
<< SPI_CMD_PREPEND_BYTE_CNT_SHIFT
);
192 cmd
|= (spi
->chip_select
<< SPI_CMD_DEVICE_ID_SHIFT
);
193 bcm_spi_writew(bs
, cmd
, SPI_CMD
);
195 /* Enable the CMD_DONE interrupt */
196 bcm_spi_writeb(bs
, SPI_INTR_CMD_DONE
, SPI_INT_MASK
);
198 timeout
= wait_for_completion_timeout(&bs
->done
, HZ
);
207 /* Read out all the data */
208 for (i
= 0; i
< num_transfers
; i
++) {
210 memcpy_fromio(t
->rx_buf
, bs
->rx_io
+ len
, t
->len
);
212 if (t
!= first
|| prepend_len
== 0)
215 t
= list_entry(t
->transfer_list
.next
, struct spi_transfer
,
222 static int bcm63xx_spi_transfer_one(struct spi_master
*master
,
223 struct spi_message
*m
)
225 struct bcm63xx_spi
*bs
= spi_master_get_devdata(master
);
226 struct spi_transfer
*t
, *first
= NULL
;
227 struct spi_device
*spi
= m
->spi
;
229 unsigned int n_transfers
= 0, total_len
= 0;
230 bool can_use_prepend
= false;
233 * This SPI controller does not support keeping CS active after a
235 * Work around this by merging as many transfers we can into one big
236 * full-duplex transfers.
238 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
245 if (n_transfers
== 2 && !first
->rx_buf
&& !t
->tx_buf
&&
246 first
->len
<= BCM63XX_SPI_MAX_PREPEND
)
247 can_use_prepend
= true;
248 else if (can_use_prepend
&& t
->tx_buf
)
249 can_use_prepend
= false;
251 /* we can only transfer one fifo worth of data */
252 if ((can_use_prepend
&&
253 total_len
> (bs
->fifo_size
+ BCM63XX_SPI_MAX_PREPEND
)) ||
254 (!can_use_prepend
&& total_len
> bs
->fifo_size
)) {
255 dev_err(&spi
->dev
, "unable to do transfers larger than FIFO size (%i > %i)\n",
256 total_len
, bs
->fifo_size
);
261 /* all combined transfers have to have the same speed */
262 if (t
->speed_hz
!= first
->speed_hz
) {
263 dev_err(&spi
->dev
, "unable to change speed between transfers\n");
268 /* CS will be deasserted directly after transfer */
269 if (t
->delay_usecs
) {
270 dev_err(&spi
->dev
, "unable to keep CS asserted after transfer\n");
276 list_is_last(&t
->transfer_list
, &m
->transfers
)) {
277 /* configure adapter for a new transfer */
278 bcm63xx_spi_setup_transfer(spi
, first
);
281 status
= bcm63xx_txrx_bufs(spi
, first
, n_transfers
);
285 m
->actual_length
+= total_len
;
290 can_use_prepend
= false;
295 spi_finalize_current_message(master
);
300 /* This driver supports single master mode only. Hence
301 * CMD_DONE is the only interrupt we care about
303 static irqreturn_t
bcm63xx_spi_interrupt(int irq
, void *dev_id
)
305 struct spi_master
*master
= (struct spi_master
*)dev_id
;
306 struct bcm63xx_spi
*bs
= spi_master_get_devdata(master
);
309 /* Read interupts and clear them immediately */
310 intr
= bcm_spi_readb(bs
, SPI_INT_STATUS
);
311 bcm_spi_writeb(bs
, SPI_INTR_CLEAR_ALL
, SPI_INT_STATUS
);
312 bcm_spi_writeb(bs
, 0, SPI_INT_MASK
);
314 /* A transfer completed */
315 if (intr
& SPI_INTR_CMD_DONE
)
322 static int bcm63xx_spi_probe(struct platform_device
*pdev
)
325 struct device
*dev
= &pdev
->dev
;
326 struct bcm63xx_spi_pdata
*pdata
= dev_get_platdata(&pdev
->dev
);
328 struct spi_master
*master
;
330 struct bcm63xx_spi
*bs
;
333 irq
= platform_get_irq(pdev
, 0);
335 dev_err(dev
, "no irq\n");
339 clk
= devm_clk_get(dev
, "spi");
341 dev_err(dev
, "no clock for device\n");
345 master
= spi_alloc_master(dev
, sizeof(*bs
));
347 dev_err(dev
, "out of memory\n");
351 bs
= spi_master_get_devdata(master
);
352 init_completion(&bs
->done
);
354 platform_set_drvdata(pdev
, master
);
357 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
358 bs
->regs
= devm_ioremap_resource(&pdev
->dev
, r
);
359 if (IS_ERR(bs
->regs
)) {
360 ret
= PTR_ERR(bs
->regs
);
366 bs
->fifo_size
= pdata
->fifo_size
;
368 ret
= devm_request_irq(&pdev
->dev
, irq
, bcm63xx_spi_interrupt
, 0,
371 dev_err(dev
, "unable to request irq\n");
375 master
->bus_num
= pdata
->bus_num
;
376 master
->num_chipselect
= pdata
->num_chipselect
;
377 master
->transfer_one_message
= bcm63xx_spi_transfer_one
;
378 master
->mode_bits
= MODEBITS
;
379 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
380 master
->auto_runtime_pm
= true;
381 bs
->msg_type_shift
= pdata
->msg_type_shift
;
382 bs
->msg_ctl_width
= pdata
->msg_ctl_width
;
383 bs
->tx_io
= (u8
*)(bs
->regs
+ bcm63xx_spireg(SPI_MSG_DATA
));
384 bs
->rx_io
= (const u8
*)(bs
->regs
+ bcm63xx_spireg(SPI_RX_DATA
));
386 switch (bs
->msg_ctl_width
) {
391 dev_err(dev
, "unsupported MSG_CTL width: %d\n",
396 /* Initialize hardware */
397 ret
= clk_prepare_enable(bs
->clk
);
401 bcm_spi_writeb(bs
, SPI_INTR_CLEAR_ALL
, SPI_INT_STATUS
);
403 /* register and we are done */
404 ret
= devm_spi_register_master(dev
, master
);
406 dev_err(dev
, "spi register failed\n");
407 goto out_clk_disable
;
410 dev_info(dev
, "at 0x%08x (irq %d, FIFOs size %d)\n",
411 r
->start
, irq
, bs
->fifo_size
);
416 clk_disable_unprepare(clk
);
418 spi_master_put(master
);
422 static int bcm63xx_spi_remove(struct platform_device
*pdev
)
424 struct spi_master
*master
= platform_get_drvdata(pdev
);
425 struct bcm63xx_spi
*bs
= spi_master_get_devdata(master
);
427 /* reset spi block */
428 bcm_spi_writeb(bs
, 0, SPI_INT_MASK
);
431 clk_disable_unprepare(bs
->clk
);
436 #ifdef CONFIG_PM_SLEEP
437 static int bcm63xx_spi_suspend(struct device
*dev
)
439 struct spi_master
*master
= dev_get_drvdata(dev
);
440 struct bcm63xx_spi
*bs
= spi_master_get_devdata(master
);
442 spi_master_suspend(master
);
444 clk_disable_unprepare(bs
->clk
);
449 static int bcm63xx_spi_resume(struct device
*dev
)
451 struct spi_master
*master
= dev_get_drvdata(dev
);
452 struct bcm63xx_spi
*bs
= spi_master_get_devdata(master
);
455 ret
= clk_prepare_enable(bs
->clk
);
459 spi_master_resume(master
);
465 static const struct dev_pm_ops bcm63xx_spi_pm_ops
= {
466 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend
, bcm63xx_spi_resume
)
469 static struct platform_driver bcm63xx_spi_driver
= {
471 .name
= "bcm63xx-spi",
472 .owner
= THIS_MODULE
,
473 .pm
= &bcm63xx_spi_pm_ops
,
475 .probe
= bcm63xx_spi_probe
,
476 .remove
= bcm63xx_spi_remove
,
479 module_platform_driver(bcm63xx_spi_driver
);
481 MODULE_ALIAS("platform:bcm63xx_spi");
482 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
483 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
484 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
485 MODULE_LICENSE("GPL");