2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/interrupt.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/edma.h>
32 #include <linux/of_device.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
35 #include <linux/slab.h>
37 #include <linux/platform_data/spi-davinci.h>
39 #define SPI_NO_RESOURCE ((resource_size_t)-1)
41 #define SPI_MAX_CHIPSELECT 2
43 #define CS_DEFAULT 0xFF
45 #define SPIFMT_PHASE_MASK BIT(16)
46 #define SPIFMT_POLARITY_MASK BIT(17)
47 #define SPIFMT_DISTIMER_MASK BIT(18)
48 #define SPIFMT_SHIFTDIR_MASK BIT(20)
49 #define SPIFMT_WAITENA_MASK BIT(21)
50 #define SPIFMT_PARITYENA_MASK BIT(22)
51 #define SPIFMT_ODD_PARITY_MASK BIT(23)
52 #define SPIFMT_WDELAY_MASK 0x3f000000u
53 #define SPIFMT_WDELAY_SHIFT 24
54 #define SPIFMT_PRESCALE_SHIFT 8
57 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
58 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
59 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
60 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
62 #define SPIINT_MASKALL 0x0101035F
63 #define SPIINT_MASKINT 0x0000015F
64 #define SPI_INTLVL_1 0x000001FF
65 #define SPI_INTLVL_0 0x00000000
67 /* SPIDAT1 (upper 16 bit defines) */
68 #define SPIDAT1_CSHOLD_MASK BIT(12)
71 #define SPIGCR1_CLKMOD_MASK BIT(1)
72 #define SPIGCR1_MASTER_MASK BIT(0)
73 #define SPIGCR1_POWERDOWN_MASK BIT(8)
74 #define SPIGCR1_LOOPBACK_MASK BIT(16)
75 #define SPIGCR1_SPIENA_MASK BIT(24)
78 #define SPIBUF_TXFULL_MASK BIT(29)
79 #define SPIBUF_RXEMPTY_MASK BIT(31)
82 #define SPIDELAY_C2TDELAY_SHIFT 24
83 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
84 #define SPIDELAY_T2CDELAY_SHIFT 16
85 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
86 #define SPIDELAY_T2EDELAY_SHIFT 8
87 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
88 #define SPIDELAY_C2EDELAY_SHIFT 0
89 #define SPIDELAY_C2EDELAY_MASK 0xFF
92 #define SPIFLG_DLEN_ERR_MASK BIT(0)
93 #define SPIFLG_TIMEOUT_MASK BIT(1)
94 #define SPIFLG_PARERR_MASK BIT(2)
95 #define SPIFLG_DESYNC_MASK BIT(3)
96 #define SPIFLG_BITERR_MASK BIT(4)
97 #define SPIFLG_OVRRUN_MASK BIT(6)
98 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
99 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
100 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
101 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
102 | SPIFLG_OVRRUN_MASK)
104 #define SPIINT_DMA_REQ_EN BIT(16)
106 /* SPI Controller registers */
115 #define SPIDELAY 0x48
119 /* SPI Controller driver's private data. */
121 struct spi_bitbang bitbang
;
125 resource_size_t pbase
;
128 struct completion done
;
135 struct dma_chan
*dma_rx
;
136 struct dma_chan
*dma_tx
;
140 struct davinci_spi_platform_data pdata
;
142 void (*get_rx
)(u32 rx_data
, struct davinci_spi
*);
143 u32 (*get_tx
)(struct davinci_spi
*);
145 u8 bytes_per_word
[SPI_MAX_CHIPSELECT
];
148 static struct davinci_spi_config davinci_spi_default_cfg
;
150 static void davinci_spi_rx_buf_u8(u32 data
, struct davinci_spi
*dspi
)
159 static void davinci_spi_rx_buf_u16(u32 data
, struct davinci_spi
*dspi
)
168 static u32
davinci_spi_tx_buf_u8(struct davinci_spi
*dspi
)
172 const u8
*tx
= dspi
->tx
;
179 static u32
davinci_spi_tx_buf_u16(struct davinci_spi
*dspi
)
183 const u16
*tx
= dspi
->tx
;
190 static inline void set_io_bits(void __iomem
*addr
, u32 bits
)
192 u32 v
= ioread32(addr
);
198 static inline void clear_io_bits(void __iomem
*addr
, u32 bits
)
200 u32 v
= ioread32(addr
);
207 * Interface to control the chip select signal
209 static void davinci_spi_chipselect(struct spi_device
*spi
, int value
)
211 struct davinci_spi
*dspi
;
212 struct davinci_spi_platform_data
*pdata
;
213 u8 chip_sel
= spi
->chip_select
;
214 u16 spidat1
= CS_DEFAULT
;
215 bool gpio_chipsel
= false;
217 dspi
= spi_master_get_devdata(spi
->master
);
218 pdata
= &dspi
->pdata
;
220 if (pdata
->chip_sel
&& chip_sel
< pdata
->num_chipselect
&&
221 pdata
->chip_sel
[chip_sel
] != SPI_INTERN_CS
)
225 * Board specific chip select logic decides the polarity and cs
226 * line for the controller
229 if (value
== BITBANG_CS_ACTIVE
)
230 gpio_set_value(pdata
->chip_sel
[chip_sel
], 0);
232 gpio_set_value(pdata
->chip_sel
[chip_sel
], 1);
234 if (value
== BITBANG_CS_ACTIVE
) {
235 spidat1
|= SPIDAT1_CSHOLD_MASK
;
236 spidat1
&= ~(0x1 << chip_sel
);
239 iowrite16(spidat1
, dspi
->base
+ SPIDAT1
+ 2);
244 * davinci_spi_get_prescale - Calculates the correct prescale value
245 * @maxspeed_hz: the maximum rate the SPI clock can run at
247 * This function calculates the prescale value that generates a clock rate
248 * less than or equal to the specified maximum.
250 * Returns: calculated prescale - 1 for easy programming into SPI registers
251 * or negative error number if valid prescalar cannot be updated.
253 static inline int davinci_spi_get_prescale(struct davinci_spi
*dspi
,
258 ret
= DIV_ROUND_UP(clk_get_rate(dspi
->clk
), max_speed_hz
);
260 if (ret
< 3 || ret
> 256)
267 * davinci_spi_setup_transfer - This functions will determine transfer method
268 * @spi: spi device on which data transfer to be done
269 * @t: spi transfer in which transfer info is filled
271 * This function determines data transfer method (8/16/32 bit transfer).
272 * It will also set the SPI Clock Control register according to
273 * SPI slave device freq.
275 static int davinci_spi_setup_transfer(struct spi_device
*spi
,
276 struct spi_transfer
*t
)
279 struct davinci_spi
*dspi
;
280 struct davinci_spi_config
*spicfg
;
281 u8 bits_per_word
= 0;
282 u32 hz
= 0, spifmt
= 0;
285 dspi
= spi_master_get_devdata(spi
->master
);
286 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
288 spicfg
= &davinci_spi_default_cfg
;
291 bits_per_word
= t
->bits_per_word
;
295 /* if bits_per_word is not set then set it default */
297 bits_per_word
= spi
->bits_per_word
;
300 * Assign function pointer to appropriate transfer method
301 * 8bit, 16bit or 32bit transfer
303 if (bits_per_word
<= 8) {
304 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
305 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
306 dspi
->bytes_per_word
[spi
->chip_select
] = 1;
308 dspi
->get_rx
= davinci_spi_rx_buf_u16
;
309 dspi
->get_tx
= davinci_spi_tx_buf_u16
;
310 dspi
->bytes_per_word
[spi
->chip_select
] = 2;
314 hz
= spi
->max_speed_hz
;
316 /* Set up SPIFMTn register, unique to this chipselect. */
318 prescale
= davinci_spi_get_prescale(dspi
, hz
);
322 spifmt
= (prescale
<< SPIFMT_PRESCALE_SHIFT
) | (bits_per_word
& 0x1f);
324 if (spi
->mode
& SPI_LSB_FIRST
)
325 spifmt
|= SPIFMT_SHIFTDIR_MASK
;
327 if (spi
->mode
& SPI_CPOL
)
328 spifmt
|= SPIFMT_POLARITY_MASK
;
330 if (!(spi
->mode
& SPI_CPHA
))
331 spifmt
|= SPIFMT_PHASE_MASK
;
334 * Version 1 hardware supports two basic SPI modes:
335 * - Standard SPI mode uses 4 pins, with chipselect
336 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
337 * (distinct from SPI_3WIRE, with just one data wire;
338 * or similar variants without MOSI or without MISO)
340 * Version 2 hardware supports an optional handshaking signal,
341 * so it can support two more modes:
342 * - 5 pin SPI variant is standard SPI plus SPI_READY
343 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
346 if (dspi
->version
== SPI_VERSION_2
) {
350 spifmt
|= ((spicfg
->wdelay
<< SPIFMT_WDELAY_SHIFT
)
351 & SPIFMT_WDELAY_MASK
);
353 if (spicfg
->odd_parity
)
354 spifmt
|= SPIFMT_ODD_PARITY_MASK
;
356 if (spicfg
->parity_enable
)
357 spifmt
|= SPIFMT_PARITYENA_MASK
;
359 if (spicfg
->timer_disable
) {
360 spifmt
|= SPIFMT_DISTIMER_MASK
;
362 delay
|= (spicfg
->c2tdelay
<< SPIDELAY_C2TDELAY_SHIFT
)
363 & SPIDELAY_C2TDELAY_MASK
;
364 delay
|= (spicfg
->t2cdelay
<< SPIDELAY_T2CDELAY_SHIFT
)
365 & SPIDELAY_T2CDELAY_MASK
;
368 if (spi
->mode
& SPI_READY
) {
369 spifmt
|= SPIFMT_WAITENA_MASK
;
370 delay
|= (spicfg
->t2edelay
<< SPIDELAY_T2EDELAY_SHIFT
)
371 & SPIDELAY_T2EDELAY_MASK
;
372 delay
|= (spicfg
->c2edelay
<< SPIDELAY_C2EDELAY_SHIFT
)
373 & SPIDELAY_C2EDELAY_MASK
;
376 iowrite32(delay
, dspi
->base
+ SPIDELAY
);
379 iowrite32(spifmt
, dspi
->base
+ SPIFMT0
);
385 * davinci_spi_setup - This functions will set default transfer method
386 * @spi: spi device on which data transfer to be done
388 * This functions sets the default transfer method.
390 static int davinci_spi_setup(struct spi_device
*spi
)
393 struct davinci_spi
*dspi
;
394 struct davinci_spi_platform_data
*pdata
;
396 dspi
= spi_master_get_devdata(spi
->master
);
397 pdata
= &dspi
->pdata
;
399 /* if bits per word length is zero then set it default 8 */
400 if (!spi
->bits_per_word
)
401 spi
->bits_per_word
= 8;
403 if (!(spi
->mode
& SPI_NO_CS
)) {
404 if ((pdata
->chip_sel
== NULL
) ||
405 (pdata
->chip_sel
[spi
->chip_select
] == SPI_INTERN_CS
))
406 set_io_bits(dspi
->base
+ SPIPC0
, 1 << spi
->chip_select
);
410 if (spi
->mode
& SPI_READY
)
411 set_io_bits(dspi
->base
+ SPIPC0
, SPIPC0_SPIENA_MASK
);
413 if (spi
->mode
& SPI_LOOP
)
414 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
416 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
421 static int davinci_spi_check_error(struct davinci_spi
*dspi
, int int_status
)
423 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
425 if (int_status
& SPIFLG_TIMEOUT_MASK
) {
426 dev_dbg(sdev
, "SPI Time-out Error\n");
429 if (int_status
& SPIFLG_DESYNC_MASK
) {
430 dev_dbg(sdev
, "SPI Desynchronization Error\n");
433 if (int_status
& SPIFLG_BITERR_MASK
) {
434 dev_dbg(sdev
, "SPI Bit error\n");
438 if (dspi
->version
== SPI_VERSION_2
) {
439 if (int_status
& SPIFLG_DLEN_ERR_MASK
) {
440 dev_dbg(sdev
, "SPI Data Length Error\n");
443 if (int_status
& SPIFLG_PARERR_MASK
) {
444 dev_dbg(sdev
, "SPI Parity Error\n");
447 if (int_status
& SPIFLG_OVRRUN_MASK
) {
448 dev_dbg(sdev
, "SPI Data Overrun error\n");
451 if (int_status
& SPIFLG_BUF_INIT_ACTIVE_MASK
) {
452 dev_dbg(sdev
, "SPI Buffer Init Active\n");
461 * davinci_spi_process_events - check for and handle any SPI controller events
462 * @dspi: the controller data
464 * This function will check the SPIFLG register and handle any events that are
467 static int davinci_spi_process_events(struct davinci_spi
*dspi
)
469 u32 buf
, status
, errors
= 0, spidat1
;
471 buf
= ioread32(dspi
->base
+ SPIBUF
);
473 if (dspi
->rcount
> 0 && !(buf
& SPIBUF_RXEMPTY_MASK
)) {
474 dspi
->get_rx(buf
& 0xFFFF, dspi
);
478 status
= ioread32(dspi
->base
+ SPIFLG
);
480 if (unlikely(status
& SPIFLG_ERROR_MASK
)) {
481 errors
= status
& SPIFLG_ERROR_MASK
;
485 if (dspi
->wcount
> 0 && !(buf
& SPIBUF_TXFULL_MASK
)) {
486 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
489 spidat1
|= 0xFFFF & dspi
->get_tx(dspi
);
490 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
497 static void davinci_spi_dma_rx_callback(void *data
)
499 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
503 if (!dspi
->wcount
&& !dspi
->rcount
)
504 complete(&dspi
->done
);
507 static void davinci_spi_dma_tx_callback(void *data
)
509 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
513 if (!dspi
->wcount
&& !dspi
->rcount
)
514 complete(&dspi
->done
);
518 * davinci_spi_bufs - functions which will handle transfer data
519 * @spi: spi device on which data transfer to be done
520 * @t: spi transfer in which transfer info is filled
522 * This function will put data to be transferred into data register
523 * of SPI controller and then wait until the completion will be marked
524 * by the IRQ Handler.
526 static int davinci_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
528 struct davinci_spi
*dspi
;
529 int data_type
, ret
= -ENOMEM
;
530 u32 tx_data
, spidat1
;
532 struct davinci_spi_config
*spicfg
;
533 struct davinci_spi_platform_data
*pdata
;
534 unsigned uninitialized_var(rx_buf_count
);
535 void *dummy_buf
= NULL
;
536 struct scatterlist sg_rx
, sg_tx
;
538 dspi
= spi_master_get_devdata(spi
->master
);
539 pdata
= &dspi
->pdata
;
540 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
542 spicfg
= &davinci_spi_default_cfg
;
544 /* convert len to words based on bits_per_word */
545 data_type
= dspi
->bytes_per_word
[spi
->chip_select
];
547 dspi
->tx
= t
->tx_buf
;
548 dspi
->rx
= t
->rx_buf
;
549 dspi
->wcount
= t
->len
/ data_type
;
550 dspi
->rcount
= dspi
->wcount
;
552 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
554 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
555 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
557 INIT_COMPLETION(dspi
->done
);
559 if (spicfg
->io_type
== SPI_IO_TYPE_INTR
)
560 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
562 if (spicfg
->io_type
!= SPI_IO_TYPE_DMA
) {
563 /* start the transfer */
565 tx_data
= dspi
->get_tx(dspi
);
566 spidat1
&= 0xFFFF0000;
567 spidat1
|= tx_data
& 0xFFFF;
568 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
570 struct dma_slave_config dma_rx_conf
= {
571 .direction
= DMA_DEV_TO_MEM
,
572 .src_addr
= (unsigned long)dspi
->pbase
+ SPIBUF
,
573 .src_addr_width
= data_type
,
576 struct dma_slave_config dma_tx_conf
= {
577 .direction
= DMA_MEM_TO_DEV
,
578 .dst_addr
= (unsigned long)dspi
->pbase
+ SPIDAT1
,
579 .dst_addr_width
= data_type
,
582 struct dma_async_tx_descriptor
*rxdesc
;
583 struct dma_async_tx_descriptor
*txdesc
;
586 dummy_buf
= kzalloc(t
->len
, GFP_KERNEL
);
588 goto err_alloc_dummy_buf
;
590 dmaengine_slave_config(dspi
->dma_rx
, &dma_rx_conf
);
591 dmaengine_slave_config(dspi
->dma_tx
, &dma_tx_conf
);
593 sg_init_table(&sg_rx
, 1);
598 t
->rx_dma
= dma_map_single(&spi
->dev
, buf
,
599 t
->len
, DMA_FROM_DEVICE
);
604 sg_dma_address(&sg_rx
) = t
->rx_dma
;
605 sg_dma_len(&sg_rx
) = t
->len
;
607 sg_init_table(&sg_tx
, 1);
611 buf
= (void *)t
->tx_buf
;
612 t
->tx_dma
= dma_map_single(&spi
->dev
, buf
,
613 t
->len
, DMA_TO_DEVICE
);
618 sg_dma_address(&sg_tx
) = t
->tx_dma
;
619 sg_dma_len(&sg_tx
) = t
->len
;
621 rxdesc
= dmaengine_prep_slave_sg(dspi
->dma_rx
,
622 &sg_rx
, 1, DMA_DEV_TO_MEM
,
623 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
627 txdesc
= dmaengine_prep_slave_sg(dspi
->dma_tx
,
628 &sg_tx
, 1, DMA_MEM_TO_DEV
,
629 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
633 rxdesc
->callback
= davinci_spi_dma_rx_callback
;
634 rxdesc
->callback_param
= (void *)dspi
;
635 txdesc
->callback
= davinci_spi_dma_tx_callback
;
636 txdesc
->callback_param
= (void *)dspi
;
638 if (pdata
->cshold_bug
)
639 iowrite16(spidat1
>> 16, dspi
->base
+ SPIDAT1
+ 2);
641 dmaengine_submit(rxdesc
);
642 dmaengine_submit(txdesc
);
644 dma_async_issue_pending(dspi
->dma_rx
);
645 dma_async_issue_pending(dspi
->dma_tx
);
647 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
650 /* Wait for the transfer to complete */
651 if (spicfg
->io_type
!= SPI_IO_TYPE_POLL
) {
652 wait_for_completion_interruptible(&(dspi
->done
));
654 while (dspi
->rcount
> 0 || dspi
->wcount
> 0) {
655 errors
= davinci_spi_process_events(dspi
);
662 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKALL
);
663 if (spicfg
->io_type
== SPI_IO_TYPE_DMA
) {
664 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
666 dma_unmap_single(&spi
->dev
, t
->rx_dma
,
667 t
->len
, DMA_FROM_DEVICE
);
668 dma_unmap_single(&spi
->dev
, t
->tx_dma
,
669 t
->len
, DMA_TO_DEVICE
);
673 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
674 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
677 * Check for bit error, desync error,parity error,timeout error and
678 * receive overflow errors
681 ret
= davinci_spi_check_error(dspi
, errors
);
682 WARN(!ret
, "%s: error reported but no error found!\n",
683 dev_name(&spi
->dev
));
687 if (dspi
->rcount
!= 0 || dspi
->wcount
!= 0) {
688 dev_err(&spi
->dev
, "SPI data transfer error\n");
695 dma_unmap_single(&spi
->dev
, t
->tx_dma
, t
->len
, DMA_TO_DEVICE
);
697 dma_unmap_single(&spi
->dev
, t
->rx_dma
, t
->len
, DMA_FROM_DEVICE
);
705 * dummy_thread_fn - dummy thread function
706 * @irq: IRQ number for this SPI Master
707 * @context_data: structure for SPI Master controller davinci_spi
709 * This is to satisfy the request_threaded_irq() API so that the irq
710 * handler is called in interrupt context.
712 static irqreturn_t
dummy_thread_fn(s32 irq
, void *data
)
718 * davinci_spi_irq - Interrupt handler for SPI Master Controller
719 * @irq: IRQ number for this SPI Master
720 * @context_data: structure for SPI Master controller davinci_spi
722 * ISR will determine that interrupt arrives either for READ or WRITE command.
723 * According to command it will do the appropriate action. It will check
724 * transfer length and if it is not zero then dispatch transfer command again.
725 * If transfer length is zero then it will indicate the COMPLETION so that
726 * davinci_spi_bufs function can go ahead.
728 static irqreturn_t
davinci_spi_irq(s32 irq
, void *data
)
730 struct davinci_spi
*dspi
= data
;
733 status
= davinci_spi_process_events(dspi
);
734 if (unlikely(status
!= 0))
735 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
737 if ((!dspi
->rcount
&& !dspi
->wcount
) || status
)
738 complete(&dspi
->done
);
743 static int davinci_spi_request_dma(struct davinci_spi
*dspi
)
746 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
750 dma_cap_set(DMA_SLAVE
, mask
);
752 dspi
->dma_rx
= dma_request_channel(mask
, edma_filter_fn
,
753 &dspi
->dma_rx_chnum
);
755 dev_err(sdev
, "request RX DMA channel failed\n");
760 dspi
->dma_tx
= dma_request_channel(mask
, edma_filter_fn
,
761 &dspi
->dma_tx_chnum
);
763 dev_err(sdev
, "request TX DMA channel failed\n");
771 dma_release_channel(dspi
->dma_rx
);
776 #if defined(CONFIG_OF)
777 static const struct of_device_id davinci_spi_of_match
[] = {
779 .compatible
= "ti,dm6441-spi",
782 .compatible
= "ti,da830-spi",
783 .data
= (void *)SPI_VERSION_2
,
787 MODULE_DEVICE_TABLE(of
, davinci_spi_of_match
);
790 * spi_davinci_get_pdata - Get platform data from DTS binding
791 * @pdev: ptr to platform data
792 * @dspi: ptr to driver data
794 * Parses and populates pdata in dspi from device tree bindings.
796 * NOTE: Not all platform data params are supported currently.
798 static int spi_davinci_get_pdata(struct platform_device
*pdev
,
799 struct davinci_spi
*dspi
)
801 struct device_node
*node
= pdev
->dev
.of_node
;
802 struct davinci_spi_platform_data
*pdata
;
803 unsigned int num_cs
, intr_line
= 0;
804 const struct of_device_id
*match
;
806 pdata
= &dspi
->pdata
;
808 pdata
->version
= SPI_VERSION_1
;
809 match
= of_match_device(of_match_ptr(davinci_spi_of_match
),
814 /* match data has the SPI version number for SPI_VERSION_2 */
815 if (match
->data
== (void *)SPI_VERSION_2
)
816 pdata
->version
= SPI_VERSION_2
;
819 * default num_cs is 1 and all chipsel are internal to the chip
820 * indicated by chip_sel being NULL. GPIO based CS is not
821 * supported yet in DT bindings.
824 of_property_read_u32(node
, "num-cs", &num_cs
);
825 pdata
->num_chipselect
= num_cs
;
826 of_property_read_u32(node
, "ti,davinci-spi-intr-line", &intr_line
);
827 pdata
->intr_line
= intr_line
;
831 #define davinci_spi_of_match NULL
832 static struct davinci_spi_platform_data
833 *spi_davinci_get_pdata(struct platform_device
*pdev
,
834 struct davinci_spi
*dspi
)
841 * davinci_spi_probe - probe function for SPI Master Controller
842 * @pdev: platform_device structure which contains plateform specific data
844 * According to Linux Device Model this function will be invoked by Linux
845 * with platform_device struct which contains the device specific info.
846 * This function will map the SPI controller's memory, register IRQ,
847 * Reset SPI controller and setting its registers to default value.
848 * It will invoke spi_bitbang_start to create work queue so that client driver
849 * can register transfer method to work queue.
851 static int davinci_spi_probe(struct platform_device
*pdev
)
853 struct spi_master
*master
;
854 struct davinci_spi
*dspi
;
855 struct davinci_spi_platform_data
*pdata
;
856 struct resource
*r
, *mem
;
857 resource_size_t dma_rx_chan
= SPI_NO_RESOURCE
;
858 resource_size_t dma_tx_chan
= SPI_NO_RESOURCE
;
862 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct davinci_spi
));
863 if (master
== NULL
) {
868 platform_set_drvdata(pdev
, master
);
870 dspi
= spi_master_get_devdata(master
);
876 if (dev_get_platdata(&pdev
->dev
)) {
877 pdata
= dev_get_platdata(&pdev
->dev
);
878 dspi
->pdata
= *pdata
;
880 /* update dspi pdata with that from the DT */
881 ret
= spi_davinci_get_pdata(pdev
, dspi
);
886 /* pdata in dspi is now updated and point pdata to that */
887 pdata
= &dspi
->pdata
;
889 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
895 dspi
->pbase
= r
->start
;
897 mem
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
903 dspi
->base
= ioremap(r
->start
, resource_size(r
));
904 if (dspi
->base
== NULL
) {
909 dspi
->irq
= platform_get_irq(pdev
, 0);
910 if (dspi
->irq
<= 0) {
915 ret
= request_threaded_irq(dspi
->irq
, davinci_spi_irq
, dummy_thread_fn
,
916 0, dev_name(&pdev
->dev
), dspi
);
920 dspi
->bitbang
.master
= master
;
921 if (dspi
->bitbang
.master
== NULL
) {
926 dspi
->clk
= clk_get(&pdev
->dev
, NULL
);
927 if (IS_ERR(dspi
->clk
)) {
931 clk_prepare_enable(dspi
->clk
);
933 master
->dev
.of_node
= pdev
->dev
.of_node
;
934 master
->bus_num
= pdev
->id
;
935 master
->num_chipselect
= pdata
->num_chipselect
;
936 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(2, 16);
937 master
->setup
= davinci_spi_setup
;
939 dspi
->bitbang
.chipselect
= davinci_spi_chipselect
;
940 dspi
->bitbang
.setup_transfer
= davinci_spi_setup_transfer
;
942 dspi
->version
= pdata
->version
;
944 dspi
->bitbang
.flags
= SPI_NO_CS
| SPI_LSB_FIRST
| SPI_LOOP
;
945 if (dspi
->version
== SPI_VERSION_2
)
946 dspi
->bitbang
.flags
|= SPI_READY
;
948 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
950 dma_rx_chan
= r
->start
;
951 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
953 dma_tx_chan
= r
->start
;
955 dspi
->bitbang
.txrx_bufs
= davinci_spi_bufs
;
956 if (dma_rx_chan
!= SPI_NO_RESOURCE
&&
957 dma_tx_chan
!= SPI_NO_RESOURCE
) {
958 dspi
->dma_rx_chnum
= dma_rx_chan
;
959 dspi
->dma_tx_chnum
= dma_tx_chan
;
961 ret
= davinci_spi_request_dma(dspi
);
965 dev_info(&pdev
->dev
, "DMA: supported\n");
966 dev_info(&pdev
->dev
, "DMA: RX channel: %d, TX channel: %d, "
967 "event queue: %d\n", dma_rx_chan
, dma_tx_chan
,
971 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
972 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
974 init_completion(&dspi
->done
);
976 /* Reset In/OUT SPI module */
977 iowrite32(0, dspi
->base
+ SPIGCR0
);
979 iowrite32(1, dspi
->base
+ SPIGCR0
);
981 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
982 spipc0
= SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK
;
983 iowrite32(spipc0
, dspi
->base
+ SPIPC0
);
985 /* initialize chip selects */
986 if (pdata
->chip_sel
) {
987 for (i
= 0; i
< pdata
->num_chipselect
; i
++) {
988 if (pdata
->chip_sel
[i
] != SPI_INTERN_CS
)
989 gpio_direction_output(pdata
->chip_sel
[i
], 1);
993 if (pdata
->intr_line
)
994 iowrite32(SPI_INTLVL_1
, dspi
->base
+ SPILVL
);
996 iowrite32(SPI_INTLVL_0
, dspi
->base
+ SPILVL
);
998 iowrite32(CS_DEFAULT
, dspi
->base
+ SPIDEF
);
1000 /* master mode default */
1001 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_CLKMOD_MASK
);
1002 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_MASTER_MASK
);
1003 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
1005 ret
= spi_bitbang_start(&dspi
->bitbang
);
1009 dev_info(&pdev
->dev
, "Controller at 0x%p\n", dspi
->base
);
1014 dma_release_channel(dspi
->dma_rx
);
1015 dma_release_channel(dspi
->dma_tx
);
1017 clk_disable_unprepare(dspi
->clk
);
1020 free_irq(dspi
->irq
, dspi
);
1022 iounmap(dspi
->base
);
1024 release_mem_region(dspi
->pbase
, resource_size(r
));
1026 spi_master_put(master
);
1032 * davinci_spi_remove - remove function for SPI Master Controller
1033 * @pdev: platform_device structure which contains plateform specific data
1035 * This function will do the reverse action of davinci_spi_probe function
1036 * It will free the IRQ and SPI controller's memory region.
1037 * It will also call spi_bitbang_stop to destroy the work queue which was
1038 * created by spi_bitbang_start.
1040 static int davinci_spi_remove(struct platform_device
*pdev
)
1042 struct davinci_spi
*dspi
;
1043 struct spi_master
*master
;
1046 master
= platform_get_drvdata(pdev
);
1047 dspi
= spi_master_get_devdata(master
);
1049 spi_bitbang_stop(&dspi
->bitbang
);
1051 clk_disable_unprepare(dspi
->clk
);
1053 free_irq(dspi
->irq
, dspi
);
1054 iounmap(dspi
->base
);
1055 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1056 release_mem_region(dspi
->pbase
, resource_size(r
));
1057 spi_master_put(master
);
1062 static struct platform_driver davinci_spi_driver
= {
1064 .name
= "spi_davinci",
1065 .owner
= THIS_MODULE
,
1066 .of_match_table
= davinci_spi_of_match
,
1068 .probe
= davinci_spi_probe
,
1069 .remove
= davinci_spi_remove
,
1071 module_platform_driver(davinci_spi_driver
);
1073 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1074 MODULE_LICENSE("GPL");