drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u8 cs;                  /* chip select pin */
  34         u8 tmode;               /* TR/TO/RO/EEPROM */
  35         u8 type;                /* SPI/SSP/MicroWire */
  36
  37         u8 poll_mode;           /* 1 means use poll mode */
  38
  39         u32 rx_threshold;
  40         u32 tx_threshold;
  41         u8 enable_dma;
  42         u16 clk_div;            /* baud rate divider */
  43         u32 speed_hz;           /* baud rate */
  44         void (*cs_control)(u32 command);
  45 };
  46
  47 #ifdef CONFIG_DEBUG_FS
  48 #define SPI_REGS_BUFSIZE        1024
  49 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  50                 size_t count, loff_t *ppos)
  51 {
  52         struct dw_spi *dws = file->private_data;
  53         char *buf;
  54         u32 len = 0;
  55         ssize_t ret;
  56
  57         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  58         if (!buf)
  59                 return 0;
  60
  61         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  62                         "%s registers:\n", dev_name(&dws->master->dev));
  63         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  64                         "=================================\n");
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "=================================\n");
  97
  98         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  99         kfree(buf);
 100         return ret;
 101 }
 102
 103 static const struct file_operations dw_spi_regs_ops = {
 104         .owner          = THIS_MODULE,
 105         .open           = simple_open,
 106         .read           = dw_spi_show_regs,
 107         .llseek         = default_llseek,
 108 };
 109
 110 static int dw_spi_debugfs_init(struct dw_spi *dws)
 111 {
 112         dws->debugfs = debugfs_create_dir("dw_spi", NULL);
 113         if (!dws->debugfs)
 114                 return -ENOMEM;
 115
 116         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 117                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 118         return 0;
 119 }
 120
 121 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 122 {
 123         debugfs_remove_recursive(dws->debugfs);
 124 }
 125
 126 #else
 127 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 128 {
 129         return 0;
 130 }
 131
 132 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 133 {
 134 }
 135 #endif /* CONFIG_DEBUG_FS */
 136
 137 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
 138 {
 139         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 140         struct chip_data *chip = spi_get_ctldata(spi);
 141
 142         /* Chip select logic is inverted from spi_set_cs() */
 143         if (chip && chip->cs_control)
 144                 chip->cs_control(!enable);
 145
 146         if (!enable)
 147                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 148 }
 149
 150 /* Return the max entries we can fill into tx fifo */
 151 static inline u32 tx_max(struct dw_spi *dws)
 152 {
 153         u32 tx_left, tx_room, rxtx_gap;
 154
 155         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 156         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 157
 158         /*
 159          * Another concern is about the tx/rx mismatch, we
 160          * though to use (dws->fifo_len - rxflr - txflr) as
 161          * one maximum value for tx, but it doesn't cover the
 162          * data which is out of tx/rx fifo and inside the
 163          * shift registers. So a control from sw point of
 164          * view is taken.
 165          */
 166         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 167                         / dws->n_bytes;
 168
 169         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 170 }
 171
 172 /* Return the max entries we should read out of rx fifo */
 173 static inline u32 rx_max(struct dw_spi *dws)
 174 {
 175         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 176
 177         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 178 }
 179
 180 static void dw_writer(struct dw_spi *dws)
 181 {
 182         u32 max = tx_max(dws);
 183         u16 txw = 0;
 184
 185         while (max--) {
 186                 /* Set the tx word if the transfer's original "tx" is not null */
 187                 if (dws->tx_end - dws->len) {
 188                         if (dws->n_bytes == 1)
 189                                 txw = *(u8 *)(dws->tx);
 190                         else
 191                                 txw = *(u16 *)(dws->tx);
 192                 }
 193                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 194                 dws->tx += dws->n_bytes;
 195         }
 196 }
 197
 198 static void dw_reader(struct dw_spi *dws)
 199 {
 200         u32 max = rx_max(dws);
 201         u16 rxw;
 202
 203         while (max--) {
 204                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 205                 /* Care rx only if the transfer's original "rx" is not null */
 206                 if (dws->rx_end - dws->len) {
 207                         if (dws->n_bytes == 1)
 208                                 *(u8 *)(dws->rx) = rxw;
 209                         else
 210                                 *(u16 *)(dws->rx) = rxw;
 211                 }
 212                 dws->rx += dws->n_bytes;
 213         }
 214 }
 215
 216 static void int_error_stop(struct dw_spi *dws, const char *msg)
 217 {
 218         spi_reset_chip(dws);
 219
 220         dev_err(&dws->master->dev, "%s\n", msg);
 221         dws->master->cur_msg->status = -EIO;
 222         spi_finalize_current_transfer(dws->master);
 223 }
 224
 225 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 226 {
 227         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 228
 229         /* Error handling */
 230         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 231                 dw_readl(dws, DW_SPI_ICR);
 232                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 233                 return IRQ_HANDLED;
 234         }
 235
 236         dw_reader(dws);
 237         if (dws->rx_end == dws->rx) {
 238                 spi_mask_intr(dws, SPI_INT_TXEI);
 239                 spi_finalize_current_transfer(dws->master);
 240                 return IRQ_HANDLED;
 241         }
 242         if (irq_status & SPI_INT_TXEI) {
 243                 spi_mask_intr(dws, SPI_INT_TXEI);
 244                 dw_writer(dws);
 245                 /* Enable TX irq always, it will be disabled when RX finished */
 246                 spi_umask_intr(dws, SPI_INT_TXEI);
 247         }
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 253 {
 254         struct spi_master *master = dev_id;
 255         struct dw_spi *dws = spi_master_get_devdata(master);
 256         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 257
 258         if (!irq_status)
 259                 return IRQ_NONE;
 260
 261         if (!master->cur_msg) {
 262                 spi_mask_intr(dws, SPI_INT_TXEI);
 263                 return IRQ_HANDLED;
 264         }
 265
 266         return dws->transfer_handler(dws);
 267 }
 268
 269 /* Must be called inside pump_transfers() */
 270 static int poll_transfer(struct dw_spi *dws)
 271 {
 272         do {
 273                 dw_writer(dws);
 274                 dw_reader(dws);
 275                 cpu_relax();
 276         } while (dws->rx_end > dws->rx);
 277
 278         return 0;
 279 }
 280
 281 static int dw_spi_transfer_one(struct spi_master *master,
 282                 struct spi_device *spi, struct spi_transfer *transfer)
 283 {
 284         struct dw_spi *dws = spi_master_get_devdata(master);
 285         struct chip_data *chip = spi_get_ctldata(spi);
 286         u8 imask = 0;
 287         u16 txlevel = 0;
 288         u16 clk_div = 0;
 289         u32 speed = 0;
 290         u32 cr0;
 291         int ret;
 292
 293         dws->dma_mapped = 0;
 294
 295         dws->tx = (void *)transfer->tx_buf;
 296         dws->tx_end = dws->tx + transfer->len;
 297         dws->rx = transfer->rx_buf;
 298         dws->rx_end = dws->rx + transfer->len;
 299         dws->len = transfer->len;
 300
 301         spi_enable_chip(dws, 0);
 302
 303         /* Handle per transfer options for bpw and speed */
 304         speed = chip->speed_hz;
 305         if ((transfer->speed_hz != speed) || !chip->clk_div) {
 306                 speed = transfer->speed_hz;
 307
 308                 /* clk_div doesn't support odd number */
 309                 clk_div = (dws->max_freq / speed + 1) & 0xfffe;
 310
 311                 chip->speed_hz = speed;
 312                 chip->clk_div = clk_div;
 313
 314                 spi_set_clk(dws, chip->clk_div);
 315         }
 316         if (transfer->bits_per_word == 8) {
 317                 dws->n_bytes = 1;
 318                 dws->dma_width = 1;
 319         } else if (transfer->bits_per_word == 16) {
 320                 dws->n_bytes = 2;
 321                 dws->dma_width = 2;
 322         } else {
 323                 return -EINVAL;
 324         }
 325         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 326         cr0 = (transfer->bits_per_word - 1)
 327                 | (chip->type << SPI_FRF_OFFSET)
 328                 | (spi->mode << SPI_MODE_OFFSET)
 329                 | (chip->tmode << SPI_TMOD_OFFSET);
 330
 331         /*
 332          * Adjust transfer mode if necessary. Requires platform dependent
 333          * chipselect mechanism.
 334          */
 335         if (chip->cs_control) {
 336                 if (dws->rx && dws->tx)
 337                         chip->tmode = SPI_TMOD_TR;
 338                 else if (dws->rx)
 339                         chip->tmode = SPI_TMOD_RO;
 340                 else
 341                         chip->tmode = SPI_TMOD_TO;
 342
 343                 cr0 &= ~SPI_TMOD_MASK;
 344                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 345         }
 346
 347         dw_writel(dws, DW_SPI_CTRL0, cr0);
 348
 349         /* Check if current transfer is a DMA transaction */
 350         if (master->can_dma && master->can_dma(master, spi, transfer))
 351                 dws->dma_mapped = master->cur_msg_mapped;
 352
 353         /* For poll mode just disable all interrupts */
 354         spi_mask_intr(dws, 0xff);
 355
 356         /*
 357          * Interrupt mode
 358          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 359          */
 360         if (dws->dma_mapped) {
 361                 ret = dws->dma_ops->dma_setup(dws, transfer);
 362                 if (ret < 0) {
 363                         spi_enable_chip(dws, 1);
 364                         return ret;
 365                 }
 366         } else if (!chip->poll_mode) {
 367                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 368                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 369
 370                 /* Set the interrupt mask */
 371                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 372                          SPI_INT_RXUI | SPI_INT_RXOI;
 373                 spi_umask_intr(dws, imask);
 374
 375                 dws->transfer_handler = interrupt_transfer;
 376         }
 377
 378         spi_enable_chip(dws, 1);
 379
 380         if (dws->dma_mapped) {
 381                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 382                 if (ret < 0)
 383                         return ret;
 384         }
 385
 386         if (chip->poll_mode)
 387                 return poll_transfer(dws);
 388
 389         return 1;
 390 }
 391
 392 static void dw_spi_handle_err(struct spi_master *master,
 393                 struct spi_message *msg)
 394 {
 395         struct dw_spi *dws = spi_master_get_devdata(master);
 396
 397         if (dws->dma_mapped)
 398                 dws->dma_ops->dma_stop(dws);
 399
 400         spi_reset_chip(dws);
 401 }
 402
 403 /* This may be called twice for each spi dev */
 404 static int dw_spi_setup(struct spi_device *spi)
 405 {
 406         struct dw_spi_chip *chip_info = NULL;
 407         struct chip_data *chip;
 408         int ret;
 409
 410         /* Only alloc on first setup */
 411         chip = spi_get_ctldata(spi);
 412         if (!chip) {
 413                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 414                 if (!chip)
 415                         return -ENOMEM;
 416                 spi_set_ctldata(spi, chip);
 417         }
 418
 419         /*
 420          * Protocol drivers may change the chip settings, so...
 421          * if chip_info exists, use it
 422          */
 423         chip_info = spi->controller_data;
 424
 425         /* chip_info doesn't always exist */
 426         if (chip_info) {
 427                 if (chip_info->cs_control)
 428                         chip->cs_control = chip_info->cs_control;
 429
 430                 chip->poll_mode = chip_info->poll_mode;
 431                 chip->type = chip_info->type;
 432
 433                 chip->rx_threshold = 0;
 434                 chip->tx_threshold = 0;
 435         }
 436
 437         chip->tmode = 0; /* Tx & Rx */
 438
 439         if (gpio_is_valid(spi->cs_gpio)) {
 440                 ret = gpio_direction_output(spi->cs_gpio,
 441                                 !(spi->mode & SPI_CS_HIGH));
 442                 if (ret)
 443                         return ret;
 444         }
 445
 446         return 0;
 447 }
 448
 449 static void dw_spi_cleanup(struct spi_device *spi)
 450 {
 451         struct chip_data *chip = spi_get_ctldata(spi);
 452
 453         kfree(chip);
 454         spi_set_ctldata(spi, NULL);
 455 }
 456
 457 /* Restart the controller, disable all interrupts, clean rx fifo */
 458 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 459 {
 460         spi_reset_chip(dws);
 461
 462         /*
 463          * Try to detect the FIFO depth if not set by interface driver,
 464          * the depth could be from 2 to 256 from HW spec
 465          */
 466         if (!dws->fifo_len) {
 467                 u32 fifo;
 468
 469                 for (fifo = 1; fifo < 256; fifo++) {
 470                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 471                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 472                                 break;
 473                 }
 474                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 475
 476                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 477                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 478         }
 479 }
 480
 481 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 482 {
 483         struct spi_master *master;
 484         int ret;
 485
 486         BUG_ON(dws == NULL);
 487
 488         master = spi_alloc_master(dev, 0);
 489         if (!master)
 490                 return -ENOMEM;
 491
 492         dws->master = master;
 493         dws->type = SSI_MOTO_SPI;
 494         dws->dma_inited = 0;
 495         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 496         snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
 497
 498         ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
 499                         dws->name, master);
 500         if (ret < 0) {
 501                 dev_err(dev, "can not get IRQ\n");
 502                 goto err_free_master;
 503         }
 504
 505         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 506         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 507         master->bus_num = dws->bus_num;
 508         master->num_chipselect = dws->num_cs;
 509         master->setup = dw_spi_setup;
 510         master->cleanup = dw_spi_cleanup;
 511         master->set_cs = dw_spi_set_cs;
 512         master->transfer_one = dw_spi_transfer_one;
 513         master->handle_err = dw_spi_handle_err;
 514         master->max_speed_hz = dws->max_freq;
 515         master->dev.of_node = dev->of_node;
 516
 517         /* Basic HW init */
 518         spi_hw_init(dev, dws);
 519
 520         if (dws->dma_ops && dws->dma_ops->dma_init) {
 521                 ret = dws->dma_ops->dma_init(dws);
 522                 if (ret) {
 523                         dev_warn(dev, "DMA init failed\n");
 524                         dws->dma_inited = 0;
 525                 } else {
 526                         master->can_dma = dws->dma_ops->can_dma;
 527                 }
 528         }
 529
 530         spi_master_set_devdata(master, dws);
 531         ret = devm_spi_register_master(dev, master);
 532         if (ret) {
 533                 dev_err(&master->dev, "problem registering spi master\n");
 534                 goto err_dma_exit;
 535         }
 536
 537         dw_spi_debugfs_init(dws);
 538         return 0;
 539
 540 err_dma_exit:
 541         if (dws->dma_ops && dws->dma_ops->dma_exit)
 542                 dws->dma_ops->dma_exit(dws);
 543         spi_enable_chip(dws, 0);
 544 err_free_master:
 545         spi_master_put(master);
 546         return ret;
 547 }
 548 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 549
 550 void dw_spi_remove_host(struct dw_spi *dws)
 551 {
 552         if (!dws)
 553                 return;
 554         dw_spi_debugfs_remove(dws);
 555
 556         if (dws->dma_ops && dws->dma_ops->dma_exit)
 557                 dws->dma_ops->dma_exit(dws);
 558         spi_enable_chip(dws, 0);
 559         /* Disable clk */
 560         spi_set_clk(dws, 0);
 561 }
 562 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 563
 564 int dw_spi_suspend_host(struct dw_spi *dws)
 565 {
 566         int ret = 0;
 567
 568         ret = spi_master_suspend(dws->master);
 569         if (ret)
 570                 return ret;
 571         spi_enable_chip(dws, 0);
 572         spi_set_clk(dws, 0);
 573         return ret;
 574 }
 575 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 576
 577 int dw_spi_resume_host(struct dw_spi *dws)
 578 {
 579         int ret;
 580
 581         spi_hw_init(&dws->master->dev, dws);
 582         ret = spi_master_resume(dws->master);
 583         if (ret)
 584                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 585         return ret;
 586 }
 587 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 588
 589 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 590 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 591 MODULE_LICENSE("GPL v2");