2 * Driver for Cirrus Logic EP93xx SPI controller.
4 * Copyright (C) 2010-2011 Mika Westerberg
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 * For more information about the SPI controller see documentation on Cirrus
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dmaengine.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/workqueue.h>
30 #include <linux/sched.h>
31 #include <linux/scatterlist.h>
32 #include <linux/spi/spi.h>
34 #include <linux/platform_data/dma-ep93xx.h>
35 #include <linux/platform_data/spi-ep93xx.h>
38 #define SSPCR0_MODE_SHIFT 6
39 #define SSPCR0_SCR_SHIFT 8
42 #define SSPCR1_RIE BIT(0)
43 #define SSPCR1_TIE BIT(1)
44 #define SSPCR1_RORIE BIT(2)
45 #define SSPCR1_LBM BIT(3)
46 #define SSPCR1_SSE BIT(4)
47 #define SSPCR1_MS BIT(5)
48 #define SSPCR1_SOD BIT(6)
53 #define SSPSR_TFE BIT(0)
54 #define SSPSR_TNF BIT(1)
55 #define SSPSR_RNE BIT(2)
56 #define SSPSR_RFF BIT(3)
57 #define SSPSR_BSY BIT(4)
58 #define SSPCPSR 0x0010
61 #define SSPIIR_RIS BIT(0)
62 #define SSPIIR_TIS BIT(1)
63 #define SSPIIR_RORIS BIT(2)
66 /* timeout in milliseconds */
68 /* maximum depth of RX/TX FIFO */
69 #define SPI_FIFO_SIZE 8
72 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @lock: spinlock that protects concurrent accesses to fields @running,
74 * @current_msg and @msg_queue
75 * @pdev: pointer to platform device
76 * @clk: clock for the controller
77 * @regs_base: pointer to ioremap()'d registers
78 * @sspdr_phys: physical address of the SSPDR register
79 * @min_rate: minimum clock rate (in Hz) supported by the controller
80 * @max_rate: maximum clock rate (in Hz) supported by the controller
81 * @running: is the queue running
82 * @wq: workqueue used by the driver
83 * @msg_work: work that is queued for the driver
84 * @wait: wait here until given transfer is completed
85 * @msg_queue: queue for the messages
86 * @current_msg: message that is currently processed (or %NULL if none)
87 * @tx: current byte in transfer to transmit
88 * @rx: current byte in transfer to receive
89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
90 * frame decreases this level and sending one frame increases it.
91 * @dma_rx: RX DMA channel
92 * @dma_tx: TX DMA channel
93 * @dma_rx_data: RX parameters passed to the DMA engine
94 * @dma_tx_data: TX parameters passed to the DMA engine
95 * @rx_sgt: sg table for RX transfers
96 * @tx_sgt: sg table for TX transfers
97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
100 * This structure holds EP93xx SPI controller specific information. When
101 * @running is %true, driver accepts transfer requests from protocol drivers.
102 * @current_msg is used to hold pointer to the message that is currently
103 * processed. If @current_msg is %NULL, it means that no processing is going
106 * Most of the fields are only written once and they can be accessed without
107 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
108 * @running, and @msg_queue.
112 const struct platform_device
*pdev
;
114 void __iomem
*regs_base
;
115 unsigned long sspdr_phys
;
116 unsigned long min_rate
;
117 unsigned long max_rate
;
119 struct workqueue_struct
*wq
;
120 struct work_struct msg_work
;
121 struct completion wait
;
122 struct list_head msg_queue
;
123 struct spi_message
*current_msg
;
127 struct dma_chan
*dma_rx
;
128 struct dma_chan
*dma_tx
;
129 struct ep93xx_dma_data dma_rx_data
;
130 struct ep93xx_dma_data dma_tx_data
;
131 struct sg_table rx_sgt
;
132 struct sg_table tx_sgt
;
137 * struct ep93xx_spi_chip - SPI device hardware settings
138 * @spi: back pointer to the SPI device
139 * @rate: max rate in hz this chip supports
140 * @div_cpsr: cpsr (pre-scaler) divider
141 * @div_scr: scr divider
142 * @dss: bits per word (4 - 16 bits)
143 * @ops: private chip operations
145 * This structure is used to store hardware register specific settings for each
146 * SPI device. Settings are written to hardware by function
147 * ep93xx_spi_chip_setup().
149 struct ep93xx_spi_chip
{
150 const struct spi_device
*spi
;
155 struct ep93xx_spi_chip_ops
*ops
;
158 /* converts bits per word to CR0.DSS value */
159 #define bits_per_word_to_dss(bpw) ((bpw) - 1)
161 static void ep93xx_spi_write_u8(const struct ep93xx_spi
*espi
,
164 writeb(value
, espi
->regs_base
+ reg
);
167 static u8
ep93xx_spi_read_u8(const struct ep93xx_spi
*spi
, u16 reg
)
169 return readb(spi
->regs_base
+ reg
);
172 static void ep93xx_spi_write_u16(const struct ep93xx_spi
*espi
,
175 writew(value
, espi
->regs_base
+ reg
);
178 static u16
ep93xx_spi_read_u16(const struct ep93xx_spi
*spi
, u16 reg
)
180 return readw(spi
->regs_base
+ reg
);
183 static int ep93xx_spi_enable(const struct ep93xx_spi
*espi
)
188 err
= clk_enable(espi
->clk
);
192 regval
= ep93xx_spi_read_u8(espi
, SSPCR1
);
193 regval
|= SSPCR1_SSE
;
194 ep93xx_spi_write_u8(espi
, SSPCR1
, regval
);
199 static void ep93xx_spi_disable(const struct ep93xx_spi
*espi
)
203 regval
= ep93xx_spi_read_u8(espi
, SSPCR1
);
204 regval
&= ~SSPCR1_SSE
;
205 ep93xx_spi_write_u8(espi
, SSPCR1
, regval
);
207 clk_disable(espi
->clk
);
210 static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi
*espi
)
214 regval
= ep93xx_spi_read_u8(espi
, SSPCR1
);
215 regval
|= (SSPCR1_RORIE
| SSPCR1_TIE
| SSPCR1_RIE
);
216 ep93xx_spi_write_u8(espi
, SSPCR1
, regval
);
219 static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi
*espi
)
223 regval
= ep93xx_spi_read_u8(espi
, SSPCR1
);
224 regval
&= ~(SSPCR1_RORIE
| SSPCR1_TIE
| SSPCR1_RIE
);
225 ep93xx_spi_write_u8(espi
, SSPCR1
, regval
);
229 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
230 * @espi: ep93xx SPI controller struct
231 * @chip: divisors are calculated for this chip
232 * @rate: desired SPI output clock rate
234 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
235 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
236 * for some reason, divisors cannot be calculated nothing is stored and
237 * %-EINVAL is returned.
239 static int ep93xx_spi_calc_divisors(const struct ep93xx_spi
*espi
,
240 struct ep93xx_spi_chip
*chip
,
243 unsigned long spi_clk_rate
= clk_get_rate(espi
->clk
);
247 * Make sure that max value is between values supported by the
248 * controller. Note that minimum value is already checked in
249 * ep93xx_spi_transfer().
251 rate
= clamp(rate
, espi
->min_rate
, espi
->max_rate
);
254 * Calculate divisors so that we can get speed according the
256 * rate = spi_clock_rate / (cpsr * (1 + scr))
258 * cpsr must be even number and starts from 2, scr can be any number
261 for (cpsr
= 2; cpsr
<= 254; cpsr
+= 2) {
262 for (scr
= 0; scr
<= 255; scr
++) {
263 if ((spi_clk_rate
/ (cpsr
* (scr
+ 1))) <= rate
) {
264 chip
->div_scr
= (u8
)scr
;
265 chip
->div_cpsr
= (u8
)cpsr
;
274 static void ep93xx_spi_cs_control(struct spi_device
*spi
, bool control
)
276 struct ep93xx_spi_chip
*chip
= spi_get_ctldata(spi
);
277 int value
= (spi
->mode
& SPI_CS_HIGH
) ? control
: !control
;
279 if (chip
->ops
&& chip
->ops
->cs_control
)
280 chip
->ops
->cs_control(spi
, value
);
284 * ep93xx_spi_setup() - setup an SPI device
285 * @spi: SPI device to setup
287 * This function sets up SPI device mode, speed etc. Can be called multiple
288 * times for a single device. Returns %0 in case of success, negative error in
289 * case of failure. When this function returns success, the device is
292 static int ep93xx_spi_setup(struct spi_device
*spi
)
294 struct ep93xx_spi
*espi
= spi_master_get_devdata(spi
->master
);
295 struct ep93xx_spi_chip
*chip
;
297 chip
= spi_get_ctldata(spi
);
299 dev_dbg(&espi
->pdev
->dev
, "initial setup for %s\n",
302 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
307 chip
->ops
= spi
->controller_data
;
309 if (chip
->ops
&& chip
->ops
->setup
) {
310 int ret
= chip
->ops
->setup(spi
);
317 spi_set_ctldata(spi
, chip
);
320 if (spi
->max_speed_hz
!= chip
->rate
) {
323 err
= ep93xx_spi_calc_divisors(espi
, chip
, spi
->max_speed_hz
);
325 spi_set_ctldata(spi
, NULL
);
329 chip
->rate
= spi
->max_speed_hz
;
332 chip
->dss
= bits_per_word_to_dss(spi
->bits_per_word
);
334 ep93xx_spi_cs_control(spi
, false);
339 * ep93xx_spi_transfer() - queue message to be transferred
340 * @spi: target SPI device
341 * @msg: message to be transferred
343 * This function is called by SPI device drivers when they are going to transfer
344 * a new message. It simply puts the message in the queue and schedules
345 * workqueue to perform the actual transfer later on.
347 * Returns %0 on success and negative error in case of failure.
349 static int ep93xx_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
351 struct ep93xx_spi
*espi
= spi_master_get_devdata(spi
->master
);
352 struct spi_transfer
*t
;
355 if (!msg
|| !msg
->complete
)
358 /* first validate each transfer */
359 list_for_each_entry(t
, &msg
->transfers
, transfer_list
) {
360 if (t
->speed_hz
&& t
->speed_hz
< espi
->min_rate
)
365 * Now that we own the message, let's initialize it so that it is
366 * suitable for us. We use @msg->status to signal whether there was
367 * error in transfer and @msg->state is used to hold pointer to the
368 * current transfer (or %NULL if no active current transfer).
372 msg
->actual_length
= 0;
374 spin_lock_irqsave(&espi
->lock
, flags
);
375 if (!espi
->running
) {
376 spin_unlock_irqrestore(&espi
->lock
, flags
);
379 list_add_tail(&msg
->queue
, &espi
->msg_queue
);
380 queue_work(espi
->wq
, &espi
->msg_work
);
381 spin_unlock_irqrestore(&espi
->lock
, flags
);
387 * ep93xx_spi_cleanup() - cleans up master controller specific state
388 * @spi: SPI device to cleanup
390 * This function releases master controller specific state for given @spi
393 static void ep93xx_spi_cleanup(struct spi_device
*spi
)
395 struct ep93xx_spi_chip
*chip
;
397 chip
= spi_get_ctldata(spi
);
399 if (chip
->ops
&& chip
->ops
->cleanup
)
400 chip
->ops
->cleanup(spi
);
401 spi_set_ctldata(spi
, NULL
);
407 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
408 * @espi: ep93xx SPI controller struct
409 * @chip: chip specific settings
411 * This function sets up the actual hardware registers with settings given in
412 * @chip. Note that no validation is done so make sure that callers validate
413 * settings before calling this.
415 static void ep93xx_spi_chip_setup(const struct ep93xx_spi
*espi
,
416 const struct ep93xx_spi_chip
*chip
)
420 cr0
= chip
->div_scr
<< SSPCR0_SCR_SHIFT
;
421 cr0
|= (chip
->spi
->mode
& (SPI_CPHA
|SPI_CPOL
)) << SSPCR0_MODE_SHIFT
;
424 dev_dbg(&espi
->pdev
->dev
, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
425 chip
->spi
->mode
, chip
->div_cpsr
, chip
->div_scr
, chip
->dss
);
426 dev_dbg(&espi
->pdev
->dev
, "setup: cr0 %#x", cr0
);
428 ep93xx_spi_write_u8(espi
, SSPCPSR
, chip
->div_cpsr
);
429 ep93xx_spi_write_u16(espi
, SSPCR0
, cr0
);
432 static void ep93xx_do_write(struct ep93xx_spi
*espi
, struct spi_transfer
*t
)
434 if (t
->bits_per_word
> 8) {
438 tx_val
= ((u16
*)t
->tx_buf
)[espi
->tx
];
439 ep93xx_spi_write_u16(espi
, SSPDR
, tx_val
);
440 espi
->tx
+= sizeof(tx_val
);
445 tx_val
= ((u8
*)t
->tx_buf
)[espi
->tx
];
446 ep93xx_spi_write_u8(espi
, SSPDR
, tx_val
);
447 espi
->tx
+= sizeof(tx_val
);
451 static void ep93xx_do_read(struct ep93xx_spi
*espi
, struct spi_transfer
*t
)
453 if (t
->bits_per_word
> 8) {
456 rx_val
= ep93xx_spi_read_u16(espi
, SSPDR
);
458 ((u16
*)t
->rx_buf
)[espi
->rx
] = rx_val
;
459 espi
->rx
+= sizeof(rx_val
);
463 rx_val
= ep93xx_spi_read_u8(espi
, SSPDR
);
465 ((u8
*)t
->rx_buf
)[espi
->rx
] = rx_val
;
466 espi
->rx
+= sizeof(rx_val
);
471 * ep93xx_spi_read_write() - perform next RX/TX transfer
472 * @espi: ep93xx SPI controller struct
474 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
475 * called several times, the whole transfer will be completed. Returns
476 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
478 * When this function is finished, RX FIFO should be empty and TX FIFO should be
481 static int ep93xx_spi_read_write(struct ep93xx_spi
*espi
)
483 struct spi_message
*msg
= espi
->current_msg
;
484 struct spi_transfer
*t
= msg
->state
;
486 /* read as long as RX FIFO has frames in it */
487 while ((ep93xx_spi_read_u8(espi
, SSPSR
) & SSPSR_RNE
)) {
488 ep93xx_do_read(espi
, t
);
492 /* write as long as TX FIFO has room */
493 while (espi
->fifo_level
< SPI_FIFO_SIZE
&& espi
->tx
< t
->len
) {
494 ep93xx_do_write(espi
, t
);
498 if (espi
->rx
== t
->len
)
504 static void ep93xx_spi_pio_transfer(struct ep93xx_spi
*espi
)
507 * Now everything is set up for the current transfer. We prime the TX
508 * FIFO, enable interrupts, and wait for the transfer to complete.
510 if (ep93xx_spi_read_write(espi
)) {
511 ep93xx_spi_enable_interrupts(espi
);
512 wait_for_completion(&espi
->wait
);
517 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
518 * @espi: ep93xx SPI controller struct
519 * @dir: DMA transfer direction
521 * Function configures the DMA, maps the buffer and prepares the DMA
522 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
523 * in case of failure.
525 static struct dma_async_tx_descriptor
*
526 ep93xx_spi_dma_prepare(struct ep93xx_spi
*espi
, enum dma_transfer_direction dir
)
528 struct spi_transfer
*t
= espi
->current_msg
->state
;
529 struct dma_async_tx_descriptor
*txd
;
530 enum dma_slave_buswidth buswidth
;
531 struct dma_slave_config conf
;
532 struct scatterlist
*sg
;
533 struct sg_table
*sgt
;
534 struct dma_chan
*chan
;
535 const void *buf
, *pbuf
;
539 if (t
->bits_per_word
> 8)
540 buswidth
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
542 buswidth
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
544 memset(&conf
, 0, sizeof(conf
));
545 conf
.direction
= dir
;
547 if (dir
== DMA_DEV_TO_MEM
) {
552 conf
.src_addr
= espi
->sspdr_phys
;
553 conf
.src_addr_width
= buswidth
;
559 conf
.dst_addr
= espi
->sspdr_phys
;
560 conf
.dst_addr_width
= buswidth
;
563 ret
= dmaengine_slave_config(chan
, &conf
);
568 * We need to split the transfer into PAGE_SIZE'd chunks. This is
569 * because we are using @espi->zeropage to provide a zero RX buffer
570 * for the TX transfers and we have only allocated one page for that.
572 * For performance reasons we allocate a new sg_table only when
573 * needed. Otherwise we will re-use the current one. Eventually the
574 * last sg_table is released in ep93xx_spi_release_dma().
577 nents
= DIV_ROUND_UP(len
, PAGE_SIZE
);
578 if (nents
!= sgt
->nents
) {
581 ret
= sg_alloc_table(sgt
, nents
, GFP_KERNEL
);
587 for_each_sg(sgt
->sgl
, sg
, sgt
->nents
, i
) {
588 size_t bytes
= min_t(size_t, len
, PAGE_SIZE
);
591 sg_set_page(sg
, virt_to_page(pbuf
), bytes
,
592 offset_in_page(pbuf
));
594 sg_set_page(sg
, virt_to_page(espi
->zeropage
),
603 dev_warn(&espi
->pdev
->dev
, "len = %d expected 0!", len
);
604 return ERR_PTR(-EINVAL
);
607 nents
= dma_map_sg(chan
->device
->dev
, sgt
->sgl
, sgt
->nents
, dir
);
609 return ERR_PTR(-ENOMEM
);
611 txd
= dmaengine_prep_slave_sg(chan
, sgt
->sgl
, nents
, dir
, DMA_CTRL_ACK
);
613 dma_unmap_sg(chan
->device
->dev
, sgt
->sgl
, sgt
->nents
, dir
);
614 return ERR_PTR(-ENOMEM
);
620 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
621 * @espi: ep93xx SPI controller struct
622 * @dir: DMA transfer direction
624 * Function finishes with the DMA transfer. After this, the DMA buffer is
627 static void ep93xx_spi_dma_finish(struct ep93xx_spi
*espi
,
628 enum dma_transfer_direction dir
)
630 struct dma_chan
*chan
;
631 struct sg_table
*sgt
;
633 if (dir
== DMA_DEV_TO_MEM
) {
641 dma_unmap_sg(chan
->device
->dev
, sgt
->sgl
, sgt
->nents
, dir
);
644 static void ep93xx_spi_dma_callback(void *callback_param
)
646 complete(callback_param
);
649 static void ep93xx_spi_dma_transfer(struct ep93xx_spi
*espi
)
651 struct spi_message
*msg
= espi
->current_msg
;
652 struct dma_async_tx_descriptor
*rxd
, *txd
;
654 rxd
= ep93xx_spi_dma_prepare(espi
, DMA_DEV_TO_MEM
);
656 dev_err(&espi
->pdev
->dev
, "DMA RX failed: %ld\n", PTR_ERR(rxd
));
657 msg
->status
= PTR_ERR(rxd
);
661 txd
= ep93xx_spi_dma_prepare(espi
, DMA_MEM_TO_DEV
);
663 ep93xx_spi_dma_finish(espi
, DMA_DEV_TO_MEM
);
664 dev_err(&espi
->pdev
->dev
, "DMA TX failed: %ld\n", PTR_ERR(rxd
));
665 msg
->status
= PTR_ERR(txd
);
669 /* We are ready when RX is done */
670 rxd
->callback
= ep93xx_spi_dma_callback
;
671 rxd
->callback_param
= &espi
->wait
;
673 /* Now submit both descriptors and wait while they finish */
674 dmaengine_submit(rxd
);
675 dmaengine_submit(txd
);
677 dma_async_issue_pending(espi
->dma_rx
);
678 dma_async_issue_pending(espi
->dma_tx
);
680 wait_for_completion(&espi
->wait
);
682 ep93xx_spi_dma_finish(espi
, DMA_MEM_TO_DEV
);
683 ep93xx_spi_dma_finish(espi
, DMA_DEV_TO_MEM
);
687 * ep93xx_spi_process_transfer() - processes one SPI transfer
688 * @espi: ep93xx SPI controller struct
689 * @msg: current message
690 * @t: transfer to process
692 * This function processes one SPI transfer given in @t. Function waits until
693 * transfer is complete (may sleep) and updates @msg->status based on whether
694 * transfer was successfully processed or not.
696 static void ep93xx_spi_process_transfer(struct ep93xx_spi
*espi
,
697 struct spi_message
*msg
,
698 struct spi_transfer
*t
)
700 struct ep93xx_spi_chip
*chip
= spi_get_ctldata(msg
->spi
);
705 err
= ep93xx_spi_calc_divisors(espi
, chip
, t
->speed_hz
);
707 dev_err(&espi
->pdev
->dev
, "failed to adjust speed\n");
712 chip
->dss
= bits_per_word_to_dss(t
->bits_per_word
);
714 ep93xx_spi_chip_setup(espi
, chip
);
720 * There is no point of setting up DMA for the transfers which will
721 * fit into the FIFO and can be transferred with a single interrupt.
722 * So in these cases we will be using PIO and don't bother for DMA.
724 if (espi
->dma_rx
&& t
->len
> SPI_FIFO_SIZE
)
725 ep93xx_spi_dma_transfer(espi
);
727 ep93xx_spi_pio_transfer(espi
);
730 * In case of error during transmit, we bail out from processing
736 msg
->actual_length
+= t
->len
;
739 * After this transfer is finished, perform any possible
740 * post-transfer actions requested by the protocol driver.
742 if (t
->delay_usecs
) {
743 set_current_state(TASK_UNINTERRUPTIBLE
);
744 schedule_timeout(usecs_to_jiffies(t
->delay_usecs
));
747 if (!list_is_last(&t
->transfer_list
, &msg
->transfers
)) {
749 * In case protocol driver is asking us to drop the
750 * chipselect briefly, we let the scheduler to handle
753 ep93xx_spi_cs_control(msg
->spi
, false);
755 ep93xx_spi_cs_control(msg
->spi
, true);
761 * ep93xx_spi_process_message() - process one SPI message
762 * @espi: ep93xx SPI controller struct
763 * @msg: message to process
765 * This function processes a single SPI message. We go through all transfers in
766 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
767 * asserted during the whole message (unless per transfer cs_change is set).
769 * @msg->status contains %0 in case of success or negative error code in case of
772 static void ep93xx_spi_process_message(struct ep93xx_spi
*espi
,
773 struct spi_message
*msg
)
775 unsigned long timeout
;
776 struct spi_transfer
*t
;
780 * Enable the SPI controller and its clock.
782 err
= ep93xx_spi_enable(espi
);
784 dev_err(&espi
->pdev
->dev
, "failed to enable SPI controller\n");
790 * Just to be sure: flush any data from RX FIFO.
792 timeout
= jiffies
+ msecs_to_jiffies(SPI_TIMEOUT
);
793 while (ep93xx_spi_read_u16(espi
, SSPSR
) & SSPSR_RNE
) {
794 if (time_after(jiffies
, timeout
)) {
795 dev_warn(&espi
->pdev
->dev
,
796 "timeout while flushing RX FIFO\n");
797 msg
->status
= -ETIMEDOUT
;
800 ep93xx_spi_read_u16(espi
, SSPDR
);
804 * We explicitly handle FIFO level. This way we don't have to check TX
805 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
807 espi
->fifo_level
= 0;
810 * Assert the chipselect.
812 ep93xx_spi_cs_control(msg
->spi
, true);
814 list_for_each_entry(t
, &msg
->transfers
, transfer_list
) {
815 ep93xx_spi_process_transfer(espi
, msg
, t
);
821 * Now the whole message is transferred (or failed for some reason). We
822 * deselect the device and disable the SPI controller.
824 ep93xx_spi_cs_control(msg
->spi
, false);
825 ep93xx_spi_disable(espi
);
828 #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
831 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
834 * Workqueue worker function. This function is called when there are new
835 * SPI messages to be processed. Message is taken out from the queue and then
836 * passed to ep93xx_spi_process_message().
838 * After message is transferred, protocol driver is notified by calling
839 * @msg->complete(). In case of error, @msg->status is set to negative error
840 * number, otherwise it contains zero (and @msg->actual_length is updated).
842 static void ep93xx_spi_work(struct work_struct
*work
)
844 struct ep93xx_spi
*espi
= work_to_espi(work
);
845 struct spi_message
*msg
;
847 spin_lock_irq(&espi
->lock
);
848 if (!espi
->running
|| espi
->current_msg
||
849 list_empty(&espi
->msg_queue
)) {
850 spin_unlock_irq(&espi
->lock
);
853 msg
= list_first_entry(&espi
->msg_queue
, struct spi_message
, queue
);
854 list_del_init(&msg
->queue
);
855 espi
->current_msg
= msg
;
856 spin_unlock_irq(&espi
->lock
);
858 ep93xx_spi_process_message(espi
, msg
);
861 * Update the current message and re-schedule ourselves if there are
862 * more messages in the queue.
864 spin_lock_irq(&espi
->lock
);
865 espi
->current_msg
= NULL
;
866 if (espi
->running
&& !list_empty(&espi
->msg_queue
))
867 queue_work(espi
->wq
, &espi
->msg_work
);
868 spin_unlock_irq(&espi
->lock
);
870 /* notify the protocol driver that we are done with this message */
871 msg
->complete(msg
->context
);
874 static irqreturn_t
ep93xx_spi_interrupt(int irq
, void *dev_id
)
876 struct ep93xx_spi
*espi
= dev_id
;
877 u8 irq_status
= ep93xx_spi_read_u8(espi
, SSPIIR
);
880 * If we got ROR (receive overrun) interrupt we know that something is
881 * wrong. Just abort the message.
883 if (unlikely(irq_status
& SSPIIR_RORIS
)) {
884 /* clear the overrun interrupt */
885 ep93xx_spi_write_u8(espi
, SSPICR
, 0);
886 dev_warn(&espi
->pdev
->dev
,
887 "receive overrun, aborting the message\n");
888 espi
->current_msg
->status
= -EIO
;
891 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
892 * simply execute next data transfer.
894 if (ep93xx_spi_read_write(espi
)) {
896 * In normal case, there still is some processing left
897 * for current transfer. Let's wait for the next
905 * Current transfer is finished, either with error or with success. In
906 * any case we disable interrupts and notify the worker to handle
907 * any post-processing of the message.
909 ep93xx_spi_disable_interrupts(espi
);
910 complete(&espi
->wait
);
914 static bool ep93xx_spi_dma_filter(struct dma_chan
*chan
, void *filter_param
)
916 if (ep93xx_dma_chan_is_m2p(chan
))
919 chan
->private = filter_param
;
923 static int ep93xx_spi_setup_dma(struct ep93xx_spi
*espi
)
928 espi
->zeropage
= (void *)get_zeroed_page(GFP_KERNEL
);
933 dma_cap_set(DMA_SLAVE
, mask
);
935 espi
->dma_rx_data
.port
= EP93XX_DMA_SSP
;
936 espi
->dma_rx_data
.direction
= DMA_DEV_TO_MEM
;
937 espi
->dma_rx_data
.name
= "ep93xx-spi-rx";
939 espi
->dma_rx
= dma_request_channel(mask
, ep93xx_spi_dma_filter
,
946 espi
->dma_tx_data
.port
= EP93XX_DMA_SSP
;
947 espi
->dma_tx_data
.direction
= DMA_MEM_TO_DEV
;
948 espi
->dma_tx_data
.name
= "ep93xx-spi-tx";
950 espi
->dma_tx
= dma_request_channel(mask
, ep93xx_spi_dma_filter
,
954 goto fail_release_rx
;
960 dma_release_channel(espi
->dma_rx
);
963 free_page((unsigned long)espi
->zeropage
);
968 static void ep93xx_spi_release_dma(struct ep93xx_spi
*espi
)
971 dma_release_channel(espi
->dma_rx
);
972 sg_free_table(&espi
->rx_sgt
);
975 dma_release_channel(espi
->dma_tx
);
976 sg_free_table(&espi
->tx_sgt
);
980 free_page((unsigned long)espi
->zeropage
);
983 static int ep93xx_spi_probe(struct platform_device
*pdev
)
985 struct spi_master
*master
;
986 struct ep93xx_spi_info
*info
;
987 struct ep93xx_spi
*espi
;
988 struct resource
*res
;
992 info
= pdev
->dev
.platform_data
;
994 master
= spi_alloc_master(&pdev
->dev
, sizeof(*espi
));
996 dev_err(&pdev
->dev
, "failed to allocate spi master\n");
1000 master
->setup
= ep93xx_spi_setup
;
1001 master
->transfer
= ep93xx_spi_transfer
;
1002 master
->cleanup
= ep93xx_spi_cleanup
;
1003 master
->bus_num
= pdev
->id
;
1004 master
->num_chipselect
= info
->num_chipselect
;
1005 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1006 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 16);
1008 platform_set_drvdata(pdev
, master
);
1010 espi
= spi_master_get_devdata(master
);
1012 espi
->clk
= clk_get(&pdev
->dev
, NULL
);
1013 if (IS_ERR(espi
->clk
)) {
1014 dev_err(&pdev
->dev
, "unable to get spi clock\n");
1015 error
= PTR_ERR(espi
->clk
);
1016 goto fail_release_master
;
1019 spin_lock_init(&espi
->lock
);
1020 init_completion(&espi
->wait
);
1023 * Calculate maximum and minimum supported clock rates
1024 * for the controller.
1026 espi
->max_rate
= clk_get_rate(espi
->clk
) / 2;
1027 espi
->min_rate
= clk_get_rate(espi
->clk
) / (254 * 256);
1030 irq
= platform_get_irq(pdev
, 0);
1033 dev_err(&pdev
->dev
, "failed to get irq resources\n");
1034 goto fail_put_clock
;
1037 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1039 dev_err(&pdev
->dev
, "unable to get iomem resource\n");
1041 goto fail_put_clock
;
1044 espi
->sspdr_phys
= res
->start
+ SSPDR
;
1046 espi
->regs_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1047 if (IS_ERR(espi
->regs_base
)) {
1048 error
= PTR_ERR(espi
->regs_base
);
1049 goto fail_put_clock
;
1052 error
= devm_request_irq(&pdev
->dev
, irq
, ep93xx_spi_interrupt
,
1053 0, "ep93xx-spi", espi
);
1055 dev_err(&pdev
->dev
, "failed to request irq\n");
1056 goto fail_put_clock
;
1059 if (info
->use_dma
&& ep93xx_spi_setup_dma(espi
))
1060 dev_warn(&pdev
->dev
, "DMA setup failed. Falling back to PIO\n");
1062 espi
->wq
= create_singlethread_workqueue("ep93xx_spid");
1064 dev_err(&pdev
->dev
, "unable to create workqueue\n");
1068 INIT_WORK(&espi
->msg_work
, ep93xx_spi_work
);
1069 INIT_LIST_HEAD(&espi
->msg_queue
);
1070 espi
->running
= true;
1072 /* make sure that the hardware is disabled */
1073 ep93xx_spi_write_u8(espi
, SSPCR1
, 0);
1075 error
= spi_register_master(master
);
1077 dev_err(&pdev
->dev
, "failed to register SPI master\n");
1078 goto fail_free_queue
;
1081 dev_info(&pdev
->dev
, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1082 (unsigned long)res
->start
, irq
);
1087 destroy_workqueue(espi
->wq
);
1089 ep93xx_spi_release_dma(espi
);
1092 fail_release_master
:
1093 spi_master_put(master
);
1098 static int ep93xx_spi_remove(struct platform_device
*pdev
)
1100 struct spi_master
*master
= platform_get_drvdata(pdev
);
1101 struct ep93xx_spi
*espi
= spi_master_get_devdata(master
);
1103 spin_lock_irq(&espi
->lock
);
1104 espi
->running
= false;
1105 spin_unlock_irq(&espi
->lock
);
1107 destroy_workqueue(espi
->wq
);
1110 * Complete remaining messages with %-ESHUTDOWN status.
1112 spin_lock_irq(&espi
->lock
);
1113 while (!list_empty(&espi
->msg_queue
)) {
1114 struct spi_message
*msg
;
1116 msg
= list_first_entry(&espi
->msg_queue
,
1117 struct spi_message
, queue
);
1118 list_del_init(&msg
->queue
);
1119 msg
->status
= -ESHUTDOWN
;
1120 spin_unlock_irq(&espi
->lock
);
1121 msg
->complete(msg
->context
);
1122 spin_lock_irq(&espi
->lock
);
1124 spin_unlock_irq(&espi
->lock
);
1126 ep93xx_spi_release_dma(espi
);
1129 spi_unregister_master(master
);
1133 static struct platform_driver ep93xx_spi_driver
= {
1135 .name
= "ep93xx-spi",
1136 .owner
= THIS_MODULE
,
1138 .probe
= ep93xx_spi_probe
,
1139 .remove
= ep93xx_spi_remove
,
1141 module_platform_driver(ep93xx_spi_driver
);
1143 MODULE_DESCRIPTION("EP93xx SPI Controller driver");
1144 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1145 MODULE_LICENSE("GPL");
1146 MODULE_ALIAS("platform:ep93xx-spi");