drivers/spi/spi-fsl-espi.c

   1 /*
   2  * Freescale eSPI controller driver.
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/delay.h>
  13 #include <linux/irq.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/fsl_devices.h>
  17 #include <linux/mm.h>
  18 #include <linux/of.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <sysdev/fsl_soc.h>
  23
  24 #include "spi-fsl-lib.h"
  25
  26 /* eSPI Controller registers */
  27 struct fsl_espi_reg {
  28         __be32 mode;            /* 0x000 - eSPI mode register */
  29         __be32 event;           /* 0x004 - eSPI event register */
  30         __be32 mask;            /* 0x008 - eSPI mask register */
  31         __be32 command;         /* 0x00c - eSPI command register */
  32         __be32 transmit;        /* 0x010 - eSPI transmit FIFO access register*/
  33         __be32 receive;         /* 0x014 - eSPI receive FIFO access register*/
  34         u8 res[8];              /* 0x018 - 0x01c reserved */
  35         __be32 csmode[4];       /* 0x020 - 0x02c eSPI cs mode register */
  36 };
  37
  38 struct fsl_espi_transfer {
  39         const void *tx_buf;
  40         void *rx_buf;
  41         unsigned len;
  42         unsigned n_tx;
  43         unsigned n_rx;
  44         unsigned actual_length;
  45         int status;
  46 };
  47
  48 /* eSPI Controller mode register definitions */
  49 #define SPMODE_ENABLE           (1 << 31)
  50 #define SPMODE_LOOP             (1 << 30)
  51 #define SPMODE_TXTHR(x)         ((x) << 8)
  52 #define SPMODE_RXTHR(x)         ((x) << 0)
  53
  54 /* eSPI Controller CS mode register definitions */
  55 #define CSMODE_CI_INACTIVEHIGH  (1 << 31)
  56 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
  57 #define CSMODE_REV              (1 << 29)
  58 #define CSMODE_DIV16            (1 << 28)
  59 #define CSMODE_PM(x)            ((x) << 24)
  60 #define CSMODE_POL_1            (1 << 20)
  61 #define CSMODE_LEN(x)           ((x) << 16)
  62 #define CSMODE_BEF(x)           ((x) << 12)
  63 #define CSMODE_AFT(x)           ((x) << 8)
  64 #define CSMODE_CG(x)            ((x) << 3)
  65
  66 /* Default mode/csmode for eSPI controller */
  67 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
  68 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
  69                 | CSMODE_AFT(0) | CSMODE_CG(1))
  70
  71 /* SPIE register values */
  72 #define SPIE_NE         0x00000200      /* Not empty */
  73 #define SPIE_NF         0x00000100      /* Not full */
  74
  75 /* SPIM register values */
  76 #define SPIM_NE         0x00000200      /* Not empty */
  77 #define SPIM_NF         0x00000100      /* Not full */
  78 #define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
  79 #define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)
  80
  81 /* SPCOM register values */
  82 #define SPCOM_CS(x)             ((x) << 30)
  83 #define SPCOM_TRANLEN(x)        ((x) << 0)
  84 #define SPCOM_TRANLEN_MAX       0xFFFF  /* Max transaction length */
  85
  86 static void fsl_espi_change_mode(struct spi_device *spi)
  87 {
  88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  90         struct fsl_espi_reg *reg_base = mspi->reg_base;
  91         __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
  92         __be32 __iomem *espi_mode = &reg_base->mode;
  93         u32 tmp;
  94         unsigned long flags;
  95
  96         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  97         local_irq_save(flags);
  98
  99         /* Turn off SPI unit prior changing mode */
 100         tmp = mpc8xxx_spi_read_reg(espi_mode);
 101         mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
 102         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 103         mpc8xxx_spi_write_reg(espi_mode, tmp);
 104
 105         local_irq_restore(flags);
 106 }
 107
 108 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
 109 {
 110         u32 data;
 111         u16 data_h;
 112         u16 data_l;
 113         const u32 *tx = mpc8xxx_spi->tx;
 114
 115         if (!tx)
 116                 return 0;
 117
 118         data = *tx++ << mpc8xxx_spi->tx_shift;
 119         data_l = data & 0xffff;
 120         data_h = (data >> 16) & 0xffff;
 121         swab16s(&data_l);
 122         swab16s(&data_h);
 123         data = data_h | data_l;
 124
 125         mpc8xxx_spi->tx = tx;
 126         return data;
 127 }
 128
 129 static int fsl_espi_setup_transfer(struct spi_device *spi,
 130                                         struct spi_transfer *t)
 131 {
 132         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 133         int bits_per_word = 0;
 134         u8 pm;
 135         u32 hz = 0;
 136         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 137
 138         if (t) {
 139                 bits_per_word = t->bits_per_word;
 140                 hz = t->speed_hz;
 141         }
 142
 143         /* spi_transfer level calls that work per-word */
 144         if (!bits_per_word)
 145                 bits_per_word = spi->bits_per_word;
 146
 147         if (!hz)
 148                 hz = spi->max_speed_hz;
 149
 150         cs->rx_shift = 0;
 151         cs->tx_shift = 0;
 152         cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 153         cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 154         if (bits_per_word <= 8) {
 155                 cs->rx_shift = 8 - bits_per_word;
 156         } else {
 157                 cs->rx_shift = 16 - bits_per_word;
 158                 if (spi->mode & SPI_LSB_FIRST)
 159                         cs->get_tx = fsl_espi_tx_buf_lsb;
 160         }
 161
 162         mpc8xxx_spi->rx_shift = cs->rx_shift;
 163         mpc8xxx_spi->tx_shift = cs->tx_shift;
 164         mpc8xxx_spi->get_rx = cs->get_rx;
 165         mpc8xxx_spi->get_tx = cs->get_tx;
 166
 167         bits_per_word = bits_per_word - 1;
 168
 169         /* mask out bits we are going to set */
 170         cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
 171
 172         cs->hw_mode |= CSMODE_LEN(bits_per_word);
 173
 174         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 175                 cs->hw_mode |= CSMODE_DIV16;
 176                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
 177
 178                 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
 179                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 180                                 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
 181                 if (pm > 33)
 182                         pm = 33;
 183         } else {
 184                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
 185         }
 186         if (pm)
 187                 pm--;
 188         if (pm < 2)
 189                 pm = 2;
 190
 191         cs->hw_mode |= CSMODE_PM(pm);
 192
 193         fsl_espi_change_mode(spi);
 194         return 0;
 195 }
 196
 197 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
 198                 unsigned int len)
 199 {
 200         u32 word;
 201         struct fsl_espi_reg *reg_base = mspi->reg_base;
 202
 203         mspi->count = len;
 204
 205         /* enable rx ints */
 206         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 207
 208         /* transmit word */
 209         word = mspi->get_tx(mspi);
 210         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 211
 212         return 0;
 213 }
 214
 215 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
 216 {
 217         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 218         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 219         unsigned int len = t->len;
 220         u8 bits_per_word;
 221         int ret;
 222
 223         bits_per_word = spi->bits_per_word;
 224         if (t->bits_per_word)
 225                 bits_per_word = t->bits_per_word;
 226
 227         mpc8xxx_spi->len = t->len;
 228         len = roundup(len, 4) / 4;
 229
 230         mpc8xxx_spi->tx = t->tx_buf;
 231         mpc8xxx_spi->rx = t->rx_buf;
 232
 233         INIT_COMPLETION(mpc8xxx_spi->done);
 234
 235         /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
 236         if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
 237                 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
 238                                 " beyond the SPCOM[TRANLEN] field\n", t->len);
 239                 return -EINVAL;
 240         }
 241         mpc8xxx_spi_write_reg(&reg_base->command,
 242                 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
 243
 244         ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
 245         if (ret)
 246                 return ret;
 247
 248         wait_for_completion(&mpc8xxx_spi->done);
 249
 250         /* disable rx ints */
 251         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 252
 253         return mpc8xxx_spi->count;
 254 }
 255
 256 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
 257 {
 258         if (cmd) {
 259                 cmd[1] = (u8)(addr >> 16);
 260                 cmd[2] = (u8)(addr >> 8);
 261                 cmd[3] = (u8)(addr >> 0);
 262         }
 263 }
 264
 265 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
 266 {
 267         if (cmd)
 268                 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
 269
 270         return 0;
 271 }
 272
 273 static void fsl_espi_do_trans(struct spi_message *m,
 274                                 struct fsl_espi_transfer *tr)
 275 {
 276         struct spi_device *spi = m->spi;
 277         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 278         struct fsl_espi_transfer *espi_trans = tr;
 279         struct spi_message message;
 280         struct spi_transfer *t, *first, trans;
 281         int status = 0;
 282
 283         spi_message_init(&message);
 284         memset(&trans, 0, sizeof(trans));
 285
 286         first = list_first_entry(&m->transfers, struct spi_transfer,
 287                         transfer_list);
 288         list_for_each_entry(t, &m->transfers, transfer_list) {
 289                 if ((first->bits_per_word != t->bits_per_word) ||
 290                         (first->speed_hz != t->speed_hz)) {
 291                         espi_trans->status = -EINVAL;
 292                         dev_err(mspi->dev, "bits_per_word/speed_hz should be"
 293                                         " same for the same SPI transfer\n");
 294                         return;
 295                 }
 296
 297                 trans.speed_hz = t->speed_hz;
 298                 trans.bits_per_word = t->bits_per_word;
 299                 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
 300         }
 301
 302         trans.len = espi_trans->len;
 303         trans.tx_buf = espi_trans->tx_buf;
 304         trans.rx_buf = espi_trans->rx_buf;
 305         spi_message_add_tail(&trans, &message);
 306
 307         list_for_each_entry(t, &message.transfers, transfer_list) {
 308                 if (t->bits_per_word || t->speed_hz) {
 309                         status = -EINVAL;
 310
 311                         status = fsl_espi_setup_transfer(spi, t);
 312                         if (status < 0)
 313                                 break;
 314                 }
 315
 316                 if (t->len)
 317                         status = fsl_espi_bufs(spi, t);
 318
 319                 if (status) {
 320                         status = -EMSGSIZE;
 321                         break;
 322                 }
 323
 324                 if (t->delay_usecs)
 325                         udelay(t->delay_usecs);
 326         }
 327
 328         espi_trans->status = status;
 329         fsl_espi_setup_transfer(spi, NULL);
 330 }
 331
 332 static void fsl_espi_cmd_trans(struct spi_message *m,
 333                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 334 {
 335         struct spi_transfer *t;
 336         u8 *local_buf;
 337         int i = 0;
 338         struct fsl_espi_transfer *espi_trans = trans;
 339
 340         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 341         if (!local_buf) {
 342                 espi_trans->status = -ENOMEM;
 343                 return;
 344         }
 345
 346         list_for_each_entry(t, &m->transfers, transfer_list) {
 347                 if (t->tx_buf) {
 348                         memcpy(local_buf + i, t->tx_buf, t->len);
 349                         i += t->len;
 350                 }
 351         }
 352
 353         espi_trans->tx_buf = local_buf;
 354         espi_trans->rx_buf = local_buf + espi_trans->n_tx;
 355         fsl_espi_do_trans(m, espi_trans);
 356
 357         espi_trans->actual_length = espi_trans->len;
 358         kfree(local_buf);
 359 }
 360
 361 static void fsl_espi_rw_trans(struct spi_message *m,
 362                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 363 {
 364         struct fsl_espi_transfer *espi_trans = trans;
 365         unsigned int n_tx = espi_trans->n_tx;
 366         unsigned int n_rx = espi_trans->n_rx;
 367         struct spi_transfer *t;
 368         u8 *local_buf;
 369         u8 *rx_buf = rx_buff;
 370         unsigned int trans_len;
 371         unsigned int addr;
 372         int i, pos, loop;
 373
 374         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 375         if (!local_buf) {
 376                 espi_trans->status = -ENOMEM;
 377                 return;
 378         }
 379
 380         for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
 381                 trans_len = n_rx - pos;
 382                 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
 383                         trans_len = SPCOM_TRANLEN_MAX - n_tx;
 384
 385                 i = 0;
 386                 list_for_each_entry(t, &m->transfers, transfer_list) {
 387                         if (t->tx_buf) {
 388                                 memcpy(local_buf + i, t->tx_buf, t->len);
 389                                 i += t->len;
 390                         }
 391                 }
 392
 393                 if (pos > 0) {
 394                         addr = fsl_espi_cmd2addr(local_buf);
 395                         addr += pos;
 396                         fsl_espi_addr2cmd(addr, local_buf);
 397                 }
 398
 399                 espi_trans->n_tx = n_tx;
 400                 espi_trans->n_rx = trans_len;
 401                 espi_trans->len = trans_len + n_tx;
 402                 espi_trans->tx_buf = local_buf;
 403                 espi_trans->rx_buf = local_buf + n_tx;
 404                 fsl_espi_do_trans(m, espi_trans);
 405
 406                 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
 407
 408                 if (loop > 0)
 409                         espi_trans->actual_length += espi_trans->len - n_tx;
 410                 else
 411                         espi_trans->actual_length += espi_trans->len;
 412         }
 413
 414         kfree(local_buf);
 415 }
 416
 417 static void fsl_espi_do_one_msg(struct spi_message *m)
 418 {
 419         struct spi_transfer *t;
 420         u8 *rx_buf = NULL;
 421         unsigned int n_tx = 0;
 422         unsigned int n_rx = 0;
 423         struct fsl_espi_transfer espi_trans;
 424
 425         list_for_each_entry(t, &m->transfers, transfer_list) {
 426                 if (t->tx_buf)
 427                         n_tx += t->len;
 428                 if (t->rx_buf) {
 429                         n_rx += t->len;
 430                         rx_buf = t->rx_buf;
 431                 }
 432         }
 433
 434         espi_trans.n_tx = n_tx;
 435         espi_trans.n_rx = n_rx;
 436         espi_trans.len = n_tx + n_rx;
 437         espi_trans.actual_length = 0;
 438         espi_trans.status = 0;
 439
 440         if (!rx_buf)
 441                 fsl_espi_cmd_trans(m, &espi_trans, NULL);
 442         else
 443                 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
 444
 445         m->actual_length = espi_trans.actual_length;
 446         m->status = espi_trans.status;
 447         m->complete(m->context);
 448 }
 449
 450 static int fsl_espi_setup(struct spi_device *spi)
 451 {
 452         struct mpc8xxx_spi *mpc8xxx_spi;
 453         struct fsl_espi_reg *reg_base;
 454         int retval;
 455         u32 hw_mode;
 456         u32 loop_mode;
 457         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 458
 459         if (!spi->max_speed_hz)
 460                 return -EINVAL;
 461
 462         if (!cs) {
 463                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 464                 if (!cs)
 465                         return -ENOMEM;
 466                 spi->controller_state = cs;
 467         }
 468
 469         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 470         reg_base = mpc8xxx_spi->reg_base;
 471
 472         hw_mode = cs->hw_mode; /* Save original settings */
 473         cs->hw_mode = mpc8xxx_spi_read_reg(
 474                         &reg_base->csmode[spi->chip_select]);
 475         /* mask out bits we are going to set */
 476         cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
 477                          | CSMODE_REV);
 478
 479         if (spi->mode & SPI_CPHA)
 480                 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
 481         if (spi->mode & SPI_CPOL)
 482                 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
 483         if (!(spi->mode & SPI_LSB_FIRST))
 484                 cs->hw_mode |= CSMODE_REV;
 485
 486         /* Handle the loop mode */
 487         loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 488         loop_mode &= ~SPMODE_LOOP;
 489         if (spi->mode & SPI_LOOP)
 490                 loop_mode |= SPMODE_LOOP;
 491         mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
 492
 493         retval = fsl_espi_setup_transfer(spi, NULL);
 494         if (retval < 0) {
 495                 cs->hw_mode = hw_mode; /* Restore settings */
 496                 return retval;
 497         }
 498         return 0;
 499 }
 500
 501 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 502 {
 503         struct fsl_espi_reg *reg_base = mspi->reg_base;
 504
 505         /* We need handle RX first */
 506         if (events & SPIE_NE) {
 507                 u32 rx_data, tmp;
 508                 u8 rx_data_8;
 509
 510                 /* Spin until RX is done */
 511                 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
 512                         cpu_relax();
 513                         events = mpc8xxx_spi_read_reg(&reg_base->event);
 514                 }
 515
 516                 if (mspi->len >= 4) {
 517                         rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 518                 } else {
 519                         tmp = mspi->len;
 520                         rx_data = 0;
 521                         while (tmp--) {
 522                                 rx_data_8 = in_8((u8 *)&reg_base->receive);
 523                                 rx_data |= (rx_data_8 << (tmp * 8));
 524                         }
 525
 526                         rx_data <<= (4 - mspi->len) * 8;
 527                 }
 528
 529                 mspi->len -= 4;
 530
 531                 if (mspi->rx)
 532                         mspi->get_rx(rx_data, mspi);
 533         }
 534
 535         if (!(events & SPIE_NF)) {
 536                 int ret;
 537
 538                 /* spin until TX is done */
 539                 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
 540                                 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
 541                 if (!ret) {
 542                         dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
 543                         return;
 544                 }
 545         }
 546
 547         /* Clear the events */
 548         mpc8xxx_spi_write_reg(&reg_base->event, events);
 549
 550         mspi->count -= 1;
 551         if (mspi->count) {
 552                 u32 word = mspi->get_tx(mspi);
 553
 554                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 555         } else {
 556                 complete(&mspi->done);
 557         }
 558 }
 559
 560 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
 561 {
 562         struct mpc8xxx_spi *mspi = context_data;
 563         struct fsl_espi_reg *reg_base = mspi->reg_base;
 564         irqreturn_t ret = IRQ_NONE;
 565         u32 events;
 566
 567         /* Get interrupt events(tx/rx) */
 568         events = mpc8xxx_spi_read_reg(&reg_base->event);
 569         if (events)
 570                 ret = IRQ_HANDLED;
 571
 572         dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
 573
 574         fsl_espi_cpu_irq(mspi, events);
 575
 576         return ret;
 577 }
 578
 579 static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
 580 {
 581         iounmap(mspi->reg_base);
 582 }
 583
 584 static struct spi_master * fsl_espi_probe(struct device *dev,
 585                 struct resource *mem, unsigned int irq)
 586 {
 587         struct fsl_spi_platform_data *pdata = dev->platform_data;
 588         struct spi_master *master;
 589         struct mpc8xxx_spi *mpc8xxx_spi;
 590         struct fsl_espi_reg *reg_base;
 591         u32 regval;
 592         int i, ret = 0;
 593
 594         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 595         if (!master) {
 596                 ret = -ENOMEM;
 597                 goto err;
 598         }
 599
 600         dev_set_drvdata(dev, master);
 601
 602         ret = mpc8xxx_spi_probe(dev, mem, irq);
 603         if (ret)
 604                 goto err_probe;
 605
 606         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 607         master->setup = fsl_espi_setup;
 608
 609         mpc8xxx_spi = spi_master_get_devdata(master);
 610         mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
 611         mpc8xxx_spi->spi_remove = fsl_espi_remove;
 612
 613         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
 614         if (!mpc8xxx_spi->reg_base) {
 615                 ret = -ENOMEM;
 616                 goto err_probe;
 617         }
 618
 619         reg_base = mpc8xxx_spi->reg_base;
 620
 621         /* Register for SPI Interrupt */
 622         ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
 623                           0, "fsl_espi", mpc8xxx_spi);
 624         if (ret)
 625                 goto free_irq;
 626
 627         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 628                 mpc8xxx_spi->rx_shift = 16;
 629                 mpc8xxx_spi->tx_shift = 24;
 630         }
 631
 632         /* SPI controller initializations */
 633         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 634         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 635         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 636         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 637
 638         /* Init eSPI CS mode register */
 639         for (i = 0; i < pdata->max_chipselect; i++)
 640                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
 641
 642         /* Enable SPI interface */
 643         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 644
 645         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 646
 647         ret = spi_register_master(master);
 648         if (ret < 0)
 649                 goto unreg_master;
 650
 651         dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
 652
 653         return master;
 654
 655 unreg_master:
 656         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 657 free_irq:
 658         iounmap(mpc8xxx_spi->reg_base);
 659 err_probe:
 660         spi_master_put(master);
 661 err:
 662         return ERR_PTR(ret);
 663 }
 664
 665 static int of_fsl_espi_get_chipselects(struct device *dev)
 666 {
 667         struct device_node *np = dev->of_node;
 668         struct fsl_spi_platform_data *pdata = dev->platform_data;
 669         const u32 *prop;
 670         int len;
 671
 672         prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
 673         if (!prop || len < sizeof(*prop)) {
 674                 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
 675                 return -EINVAL;
 676         }
 677
 678         pdata->max_chipselect = *prop;
 679         pdata->cs_control = NULL;
 680
 681         return 0;
 682 }
 683
 684 static int of_fsl_espi_probe(struct platform_device *ofdev)
 685 {
 686         struct device *dev = &ofdev->dev;
 687         struct device_node *np = ofdev->dev.of_node;
 688         struct spi_master *master;
 689         struct resource mem;
 690         struct resource irq;
 691         int ret = -ENOMEM;
 692
 693         ret = of_mpc8xxx_spi_probe(ofdev);
 694         if (ret)
 695                 return ret;
 696
 697         ret = of_fsl_espi_get_chipselects(dev);
 698         if (ret)
 699                 goto err;
 700
 701         ret = of_address_to_resource(np, 0, &mem);
 702         if (ret)
 703                 goto err;
 704
 705         ret = of_irq_to_resource(np, 0, &irq);
 706         if (!ret) {
 707                 ret = -EINVAL;
 708                 goto err;
 709         }
 710
 711         master = fsl_espi_probe(dev, &mem, irq.start);
 712         if (IS_ERR(master)) {
 713                 ret = PTR_ERR(master);
 714                 goto err;
 715         }
 716
 717         return 0;
 718
 719 err:
 720         return ret;
 721 }
 722
 723 static int of_fsl_espi_remove(struct platform_device *dev)
 724 {
 725         return mpc8xxx_spi_remove(&dev->dev);
 726 }
 727
 728 static const struct of_device_id of_fsl_espi_match[] = {
 729         { .compatible = "fsl,mpc8536-espi" },
 730         {}
 731 };
 732 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
 733
 734 static struct platform_driver fsl_espi_driver = {
 735         .driver = {
 736                 .name = "fsl_espi",
 737                 .owner = THIS_MODULE,
 738                 .of_match_table = of_fsl_espi_match,
 739         },
 740         .probe          = of_fsl_espi_probe,
 741         .remove         = of_fsl_espi_remove,
 742 };
 743 module_platform_driver(fsl_espi_driver);
 744
 745 MODULE_AUTHOR("Mingkai Hu");
 746 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
 747 MODULE_LICENSE("GPL");