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spi: imx: drop unnecessary read/modify/write
[deliverable/linux.git] / drivers / spi / spi-imx.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_gpio.h>
41
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/platform_data/spi-imx.h>
44
45 #define DRIVER_NAME "spi_imx"
46
47 #define MXC_CSPIRXDATA 0x00
48 #define MXC_CSPITXDATA 0x04
49 #define MXC_CSPICTRL 0x08
50 #define MXC_CSPIINT 0x0c
51 #define MXC_RESET 0x1c
52
53 /* generic defines to abstract from the different register layouts */
54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
57 /* The maximum bytes that a sdma BD can transfer.*/
58 #define MAX_SDMA_BD_BYTES (1 << 15)
59 struct spi_imx_config {
60 unsigned int speed_hz;
61 unsigned int bpw;
62 unsigned int mode;
63 u8 cs;
64 };
65
66 enum spi_imx_devtype {
67 IMX1_CSPI,
68 IMX21_CSPI,
69 IMX27_CSPI,
70 IMX31_CSPI,
71 IMX35_CSPI, /* CSPI on all i.mx except above */
72 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
73 };
74
75 struct spi_imx_data;
76
77 struct spi_imx_devtype_data {
78 void (*intctrl)(struct spi_imx_data *, int);
79 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
80 void (*trigger)(struct spi_imx_data *);
81 int (*rx_available)(struct spi_imx_data *);
82 void (*reset)(struct spi_imx_data *);
83 enum spi_imx_devtype devtype;
84 };
85
86 struct spi_imx_data {
87 struct spi_bitbang bitbang;
88 struct device *dev;
89
90 struct completion xfer_done;
91 void __iomem *base;
92 struct clk *clk_per;
93 struct clk *clk_ipg;
94 unsigned long spi_clk;
95 unsigned int spi_bus_clk;
96
97 unsigned int count;
98 void (*tx)(struct spi_imx_data *);
99 void (*rx)(struct spi_imx_data *);
100 void *rx_buf;
101 const void *tx_buf;
102 unsigned int txfifo; /* number of words pushed in tx FIFO */
103
104 /* DMA */
105 unsigned int dma_is_inited;
106 unsigned int dma_finished;
107 bool usedma;
108 u32 wml;
109 struct completion dma_rx_completion;
110 struct completion dma_tx_completion;
111
112 const struct spi_imx_devtype_data *devtype_data;
113 int chipselect[0];
114 };
115
116 static inline int is_imx27_cspi(struct spi_imx_data *d)
117 {
118 return d->devtype_data->devtype == IMX27_CSPI;
119 }
120
121 static inline int is_imx35_cspi(struct spi_imx_data *d)
122 {
123 return d->devtype_data->devtype == IMX35_CSPI;
124 }
125
126 static inline int is_imx51_ecspi(struct spi_imx_data *d)
127 {
128 return d->devtype_data->devtype == IMX51_ECSPI;
129 }
130
131 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
132 {
133 return is_imx51_ecspi(d) ? 64 : 8;
134 }
135
136 #define MXC_SPI_BUF_RX(type) \
137 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
138 { \
139 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
140 \
141 if (spi_imx->rx_buf) { \
142 *(type *)spi_imx->rx_buf = val; \
143 spi_imx->rx_buf += sizeof(type); \
144 } \
145 }
146
147 #define MXC_SPI_BUF_TX(type) \
148 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
149 { \
150 type val = 0; \
151 \
152 if (spi_imx->tx_buf) { \
153 val = *(type *)spi_imx->tx_buf; \
154 spi_imx->tx_buf += sizeof(type); \
155 } \
156 \
157 spi_imx->count -= sizeof(type); \
158 \
159 writel(val, spi_imx->base + MXC_CSPITXDATA); \
160 }
161
162 MXC_SPI_BUF_RX(u8)
163 MXC_SPI_BUF_TX(u8)
164 MXC_SPI_BUF_RX(u16)
165 MXC_SPI_BUF_TX(u16)
166 MXC_SPI_BUF_RX(u32)
167 MXC_SPI_BUF_TX(u32)
168
169 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
170 * (which is currently not the case in this driver)
171 */
172 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
173 256, 384, 512, 768, 1024};
174
175 /* MX21, MX27 */
176 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
177 unsigned int fspi, unsigned int max)
178 {
179 int i;
180
181 for (i = 2; i < max; i++)
182 if (fspi * mxc_clkdivs[i] >= fin)
183 return i;
184
185 return max;
186 }
187
188 /* MX1, MX31, MX35, MX51 CSPI */
189 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
190 unsigned int fspi)
191 {
192 int i, div = 4;
193
194 for (i = 0; i < 7; i++) {
195 if (fspi * div >= fin)
196 return i;
197 div <<= 1;
198 }
199
200 return 7;
201 }
202
203 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
204 struct spi_transfer *transfer)
205 {
206 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
207
208 if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml &&
209 (transfer->len % spi_imx->wml) == 0)
210 return true;
211 return false;
212 }
213
214 #define MX51_ECSPI_CTRL 0x08
215 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
216 #define MX51_ECSPI_CTRL_XCH (1 << 2)
217 #define MX51_ECSPI_CTRL_SMC (1 << 3)
218 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
219 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
220 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
221 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
222 #define MX51_ECSPI_CTRL_BL_OFFSET 20
223
224 #define MX51_ECSPI_CONFIG 0x0c
225 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
226 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
227 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
228 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
229 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
230
231 #define MX51_ECSPI_INT 0x10
232 #define MX51_ECSPI_INT_TEEN (1 << 0)
233 #define MX51_ECSPI_INT_RREN (1 << 3)
234
235 #define MX51_ECSPI_DMA 0x14
236 #define MX51_ECSPI_DMA_TX_WML_OFFSET 0
237 #define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
238 #define MX51_ECSPI_DMA_RX_WML_OFFSET 16
239 #define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
240 #define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
241 #define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
242
243 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
244 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
245 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
246
247 #define MX51_ECSPI_STAT 0x18
248 #define MX51_ECSPI_STAT_RR (1 << 3)
249
250 #define MX51_ECSPI_TESTREG 0x20
251 #define MX51_ECSPI_TESTREG_LBC BIT(31)
252
253 /* MX51 eCSPI */
254 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
255 unsigned int fspi, unsigned int *fres)
256 {
257 /*
258 * there are two 4-bit dividers, the pre-divider divides by
259 * $pre, the post-divider by 2^$post
260 */
261 unsigned int pre, post;
262 unsigned int fin = spi_imx->spi_clk;
263
264 if (unlikely(fspi > fin))
265 return 0;
266
267 post = fls(fin) - fls(fspi);
268 if (fin > fspi << post)
269 post++;
270
271 /* now we have: (fin <= fspi << post) with post being minimal */
272
273 post = max(4U, post) - 4;
274 if (unlikely(post > 0xf)) {
275 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
276 fspi, fin);
277 return 0xff;
278 }
279
280 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
281
282 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
283 __func__, fin, fspi, post, pre);
284
285 /* Resulting frequency for the SCLK line. */
286 *fres = (fin / (pre + 1)) >> post;
287
288 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
289 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
290 }
291
292 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
293 {
294 unsigned val = 0;
295
296 if (enable & MXC_INT_TE)
297 val |= MX51_ECSPI_INT_TEEN;
298
299 if (enable & MXC_INT_RR)
300 val |= MX51_ECSPI_INT_RREN;
301
302 writel(val, spi_imx->base + MX51_ECSPI_INT);
303 }
304
305 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
306 {
307 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
308
309 if (!spi_imx->usedma)
310 reg |= MX51_ECSPI_CTRL_XCH;
311 else if (!spi_imx->dma_finished)
312 reg |= MX51_ECSPI_CTRL_SMC;
313 else
314 reg &= ~MX51_ECSPI_CTRL_SMC;
315 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
316 }
317
318 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
319 struct spi_imx_config *config)
320 {
321 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
322 u32 clk = config->speed_hz, delay, reg;
323
324 /*
325 * The hardware seems to have a race condition when changing modes. The
326 * current assumption is that the selection of the channel arrives
327 * earlier in the hardware than the mode bits when they are written at
328 * the same time.
329 * So set master mode for all channels as we do not support slave mode.
330 */
331 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
332
333 /* set clock speed */
334 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
335 spi_imx->spi_bus_clk = clk;
336
337 /* set chip select to use */
338 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
339
340 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
341
342 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
343
344 if (config->mode & SPI_CPHA)
345 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
346 else
347 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
348
349 if (config->mode & SPI_CPOL) {
350 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
351 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
352 } else {
353 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
354 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
355 }
356 if (config->mode & SPI_CS_HIGH)
357 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
358 else
359 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
360
361 /* CTRL register always go first to bring out controller from reset */
362 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
363
364 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
365 if (config->mode & SPI_LOOP)
366 reg |= MX51_ECSPI_TESTREG_LBC;
367 else
368 reg &= ~MX51_ECSPI_TESTREG_LBC;
369 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
370
371 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
372
373 /*
374 * Wait until the changes in the configuration register CONFIGREG
375 * propagate into the hardware. It takes exactly one tick of the
376 * SCLK clock, but we will wait two SCLK clock just to be sure. The
377 * effect of the delay it takes for the hardware to apply changes
378 * is noticable if the SCLK clock run very slow. In such a case, if
379 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
380 * be asserted before the SCLK polarity changes, which would disrupt
381 * the SPI communication as the device on the other end would consider
382 * the change of SCLK polarity as a clock tick already.
383 */
384 delay = (2 * 1000000) / clk;
385 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
386 udelay(delay);
387 else /* SCLK is _very_ slow */
388 usleep_range(delay, delay + 10);
389
390 /*
391 * Configure the DMA register: setup the watermark
392 * and enable DMA request.
393 */
394
395 writel(spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET |
396 spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET |
397 spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET |
398 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
399 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
400
401 return 0;
402 }
403
404 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
405 {
406 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
407 }
408
409 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
410 {
411 /* drain receive buffer */
412 while (mx51_ecspi_rx_available(spi_imx))
413 readl(spi_imx->base + MXC_CSPIRXDATA);
414 }
415
416 #define MX31_INTREG_TEEN (1 << 0)
417 #define MX31_INTREG_RREN (1 << 3)
418
419 #define MX31_CSPICTRL_ENABLE (1 << 0)
420 #define MX31_CSPICTRL_MASTER (1 << 1)
421 #define MX31_CSPICTRL_XCH (1 << 2)
422 #define MX31_CSPICTRL_POL (1 << 4)
423 #define MX31_CSPICTRL_PHA (1 << 5)
424 #define MX31_CSPICTRL_SSCTL (1 << 6)
425 #define MX31_CSPICTRL_SSPOL (1 << 7)
426 #define MX31_CSPICTRL_BC_SHIFT 8
427 #define MX35_CSPICTRL_BL_SHIFT 20
428 #define MX31_CSPICTRL_CS_SHIFT 24
429 #define MX35_CSPICTRL_CS_SHIFT 12
430 #define MX31_CSPICTRL_DR_SHIFT 16
431
432 #define MX31_CSPISTATUS 0x14
433 #define MX31_STATUS_RR (1 << 3)
434
435 /* These functions also work for the i.MX35, but be aware that
436 * the i.MX35 has a slightly different register layout for bits
437 * we do not use here.
438 */
439 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
440 {
441 unsigned int val = 0;
442
443 if (enable & MXC_INT_TE)
444 val |= MX31_INTREG_TEEN;
445 if (enable & MXC_INT_RR)
446 val |= MX31_INTREG_RREN;
447
448 writel(val, spi_imx->base + MXC_CSPIINT);
449 }
450
451 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
452 {
453 unsigned int reg;
454
455 reg = readl(spi_imx->base + MXC_CSPICTRL);
456 reg |= MX31_CSPICTRL_XCH;
457 writel(reg, spi_imx->base + MXC_CSPICTRL);
458 }
459
460 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
461 struct spi_imx_config *config)
462 {
463 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
464 int cs = spi_imx->chipselect[config->cs];
465
466 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
467 MX31_CSPICTRL_DR_SHIFT;
468
469 if (is_imx35_cspi(spi_imx)) {
470 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
471 reg |= MX31_CSPICTRL_SSCTL;
472 } else {
473 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
474 }
475
476 if (config->mode & SPI_CPHA)
477 reg |= MX31_CSPICTRL_PHA;
478 if (config->mode & SPI_CPOL)
479 reg |= MX31_CSPICTRL_POL;
480 if (config->mode & SPI_CS_HIGH)
481 reg |= MX31_CSPICTRL_SSPOL;
482 if (cs < 0)
483 reg |= (cs + 32) <<
484 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
485 MX31_CSPICTRL_CS_SHIFT);
486
487 writel(reg, spi_imx->base + MXC_CSPICTRL);
488
489 return 0;
490 }
491
492 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
493 {
494 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
495 }
496
497 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
498 {
499 /* drain receive buffer */
500 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
501 readl(spi_imx->base + MXC_CSPIRXDATA);
502 }
503
504 #define MX21_INTREG_RR (1 << 4)
505 #define MX21_INTREG_TEEN (1 << 9)
506 #define MX21_INTREG_RREN (1 << 13)
507
508 #define MX21_CSPICTRL_POL (1 << 5)
509 #define MX21_CSPICTRL_PHA (1 << 6)
510 #define MX21_CSPICTRL_SSPOL (1 << 8)
511 #define MX21_CSPICTRL_XCH (1 << 9)
512 #define MX21_CSPICTRL_ENABLE (1 << 10)
513 #define MX21_CSPICTRL_MASTER (1 << 11)
514 #define MX21_CSPICTRL_DR_SHIFT 14
515 #define MX21_CSPICTRL_CS_SHIFT 19
516
517 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
518 {
519 unsigned int val = 0;
520
521 if (enable & MXC_INT_TE)
522 val |= MX21_INTREG_TEEN;
523 if (enable & MXC_INT_RR)
524 val |= MX21_INTREG_RREN;
525
526 writel(val, spi_imx->base + MXC_CSPIINT);
527 }
528
529 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
530 {
531 unsigned int reg;
532
533 reg = readl(spi_imx->base + MXC_CSPICTRL);
534 reg |= MX21_CSPICTRL_XCH;
535 writel(reg, spi_imx->base + MXC_CSPICTRL);
536 }
537
538 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
539 struct spi_imx_config *config)
540 {
541 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
542 int cs = spi_imx->chipselect[config->cs];
543 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
544
545 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
546 MX21_CSPICTRL_DR_SHIFT;
547 reg |= config->bpw - 1;
548
549 if (config->mode & SPI_CPHA)
550 reg |= MX21_CSPICTRL_PHA;
551 if (config->mode & SPI_CPOL)
552 reg |= MX21_CSPICTRL_POL;
553 if (config->mode & SPI_CS_HIGH)
554 reg |= MX21_CSPICTRL_SSPOL;
555 if (cs < 0)
556 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
557
558 writel(reg, spi_imx->base + MXC_CSPICTRL);
559
560 return 0;
561 }
562
563 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
564 {
565 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
566 }
567
568 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
569 {
570 writel(1, spi_imx->base + MXC_RESET);
571 }
572
573 #define MX1_INTREG_RR (1 << 3)
574 #define MX1_INTREG_TEEN (1 << 8)
575 #define MX1_INTREG_RREN (1 << 11)
576
577 #define MX1_CSPICTRL_POL (1 << 4)
578 #define MX1_CSPICTRL_PHA (1 << 5)
579 #define MX1_CSPICTRL_XCH (1 << 8)
580 #define MX1_CSPICTRL_ENABLE (1 << 9)
581 #define MX1_CSPICTRL_MASTER (1 << 10)
582 #define MX1_CSPICTRL_DR_SHIFT 13
583
584 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
585 {
586 unsigned int val = 0;
587
588 if (enable & MXC_INT_TE)
589 val |= MX1_INTREG_TEEN;
590 if (enable & MXC_INT_RR)
591 val |= MX1_INTREG_RREN;
592
593 writel(val, spi_imx->base + MXC_CSPIINT);
594 }
595
596 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
597 {
598 unsigned int reg;
599
600 reg = readl(spi_imx->base + MXC_CSPICTRL);
601 reg |= MX1_CSPICTRL_XCH;
602 writel(reg, spi_imx->base + MXC_CSPICTRL);
603 }
604
605 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
606 struct spi_imx_config *config)
607 {
608 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
609
610 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
611 MX1_CSPICTRL_DR_SHIFT;
612 reg |= config->bpw - 1;
613
614 if (config->mode & SPI_CPHA)
615 reg |= MX1_CSPICTRL_PHA;
616 if (config->mode & SPI_CPOL)
617 reg |= MX1_CSPICTRL_POL;
618
619 writel(reg, spi_imx->base + MXC_CSPICTRL);
620
621 return 0;
622 }
623
624 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
625 {
626 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
627 }
628
629 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
630 {
631 writel(1, spi_imx->base + MXC_RESET);
632 }
633
634 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
635 .intctrl = mx1_intctrl,
636 .config = mx1_config,
637 .trigger = mx1_trigger,
638 .rx_available = mx1_rx_available,
639 .reset = mx1_reset,
640 .devtype = IMX1_CSPI,
641 };
642
643 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
644 .intctrl = mx21_intctrl,
645 .config = mx21_config,
646 .trigger = mx21_trigger,
647 .rx_available = mx21_rx_available,
648 .reset = mx21_reset,
649 .devtype = IMX21_CSPI,
650 };
651
652 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
653 /* i.mx27 cspi shares the functions with i.mx21 one */
654 .intctrl = mx21_intctrl,
655 .config = mx21_config,
656 .trigger = mx21_trigger,
657 .rx_available = mx21_rx_available,
658 .reset = mx21_reset,
659 .devtype = IMX27_CSPI,
660 };
661
662 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
663 .intctrl = mx31_intctrl,
664 .config = mx31_config,
665 .trigger = mx31_trigger,
666 .rx_available = mx31_rx_available,
667 .reset = mx31_reset,
668 .devtype = IMX31_CSPI,
669 };
670
671 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
672 /* i.mx35 and later cspi shares the functions with i.mx31 one */
673 .intctrl = mx31_intctrl,
674 .config = mx31_config,
675 .trigger = mx31_trigger,
676 .rx_available = mx31_rx_available,
677 .reset = mx31_reset,
678 .devtype = IMX35_CSPI,
679 };
680
681 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
682 .intctrl = mx51_ecspi_intctrl,
683 .config = mx51_ecspi_config,
684 .trigger = mx51_ecspi_trigger,
685 .rx_available = mx51_ecspi_rx_available,
686 .reset = mx51_ecspi_reset,
687 .devtype = IMX51_ECSPI,
688 };
689
690 static const struct platform_device_id spi_imx_devtype[] = {
691 {
692 .name = "imx1-cspi",
693 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
694 }, {
695 .name = "imx21-cspi",
696 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
697 }, {
698 .name = "imx27-cspi",
699 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
700 }, {
701 .name = "imx31-cspi",
702 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
703 }, {
704 .name = "imx35-cspi",
705 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
706 }, {
707 .name = "imx51-ecspi",
708 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
709 }, {
710 /* sentinel */
711 }
712 };
713
714 static const struct of_device_id spi_imx_dt_ids[] = {
715 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
716 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
717 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
718 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
719 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
720 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
721 { /* sentinel */ }
722 };
723 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
724
725 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
726 {
727 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
728 int gpio = spi_imx->chipselect[spi->chip_select];
729 int active = is_active != BITBANG_CS_INACTIVE;
730 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
731
732 if (!gpio_is_valid(gpio))
733 return;
734
735 gpio_set_value(gpio, dev_is_lowactive ^ active);
736 }
737
738 static void spi_imx_push(struct spi_imx_data *spi_imx)
739 {
740 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
741 if (!spi_imx->count)
742 break;
743 spi_imx->tx(spi_imx);
744 spi_imx->txfifo++;
745 }
746
747 spi_imx->devtype_data->trigger(spi_imx);
748 }
749
750 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
751 {
752 struct spi_imx_data *spi_imx = dev_id;
753
754 while (spi_imx->devtype_data->rx_available(spi_imx)) {
755 spi_imx->rx(spi_imx);
756 spi_imx->txfifo--;
757 }
758
759 if (spi_imx->count) {
760 spi_imx_push(spi_imx);
761 return IRQ_HANDLED;
762 }
763
764 if (spi_imx->txfifo) {
765 /* No data left to push, but still waiting for rx data,
766 * enable receive data available interrupt.
767 */
768 spi_imx->devtype_data->intctrl(
769 spi_imx, MXC_INT_RR);
770 return IRQ_HANDLED;
771 }
772
773 spi_imx->devtype_data->intctrl(spi_imx, 0);
774 complete(&spi_imx->xfer_done);
775
776 return IRQ_HANDLED;
777 }
778
779 static int spi_imx_setupxfer(struct spi_device *spi,
780 struct spi_transfer *t)
781 {
782 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
783 struct spi_imx_config config;
784
785 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
786 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
787 config.mode = spi->mode;
788 config.cs = spi->chip_select;
789
790 if (!config.speed_hz)
791 config.speed_hz = spi->max_speed_hz;
792 if (!config.bpw)
793 config.bpw = spi->bits_per_word;
794
795 /* Initialize the functions for transfer */
796 if (config.bpw <= 8) {
797 spi_imx->rx = spi_imx_buf_rx_u8;
798 spi_imx->tx = spi_imx_buf_tx_u8;
799 } else if (config.bpw <= 16) {
800 spi_imx->rx = spi_imx_buf_rx_u16;
801 spi_imx->tx = spi_imx_buf_tx_u16;
802 } else {
803 spi_imx->rx = spi_imx_buf_rx_u32;
804 spi_imx->tx = spi_imx_buf_tx_u32;
805 }
806
807 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
808 spi_imx->usedma = 1;
809 else
810 spi_imx->usedma = 0;
811
812 spi_imx->devtype_data->config(spi_imx, &config);
813
814 return 0;
815 }
816
817 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
818 {
819 struct spi_master *master = spi_imx->bitbang.master;
820
821 if (master->dma_rx) {
822 dma_release_channel(master->dma_rx);
823 master->dma_rx = NULL;
824 }
825
826 if (master->dma_tx) {
827 dma_release_channel(master->dma_tx);
828 master->dma_tx = NULL;
829 }
830
831 spi_imx->dma_is_inited = 0;
832 }
833
834 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
835 struct spi_master *master,
836 const struct resource *res)
837 {
838 struct dma_slave_config slave_config = {};
839 int ret;
840
841 /* use pio mode for i.mx6dl chip TKT238285 */
842 if (of_machine_is_compatible("fsl,imx6dl"))
843 return 0;
844
845 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
846
847 /* Prepare for TX DMA: */
848 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
849 if (IS_ERR(master->dma_tx)) {
850 ret = PTR_ERR(master->dma_tx);
851 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
852 master->dma_tx = NULL;
853 goto err;
854 }
855
856 slave_config.direction = DMA_MEM_TO_DEV;
857 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
858 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
859 slave_config.dst_maxburst = spi_imx->wml;
860 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
861 if (ret) {
862 dev_err(dev, "error in TX dma configuration.\n");
863 goto err;
864 }
865
866 /* Prepare for RX : */
867 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
868 if (IS_ERR(master->dma_rx)) {
869 ret = PTR_ERR(master->dma_rx);
870 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
871 master->dma_rx = NULL;
872 goto err;
873 }
874
875 slave_config.direction = DMA_DEV_TO_MEM;
876 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
877 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
878 slave_config.src_maxburst = spi_imx->wml;
879 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
880 if (ret) {
881 dev_err(dev, "error in RX dma configuration.\n");
882 goto err;
883 }
884
885 init_completion(&spi_imx->dma_rx_completion);
886 init_completion(&spi_imx->dma_tx_completion);
887 master->can_dma = spi_imx_can_dma;
888 master->max_dma_len = MAX_SDMA_BD_BYTES;
889 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
890 SPI_MASTER_MUST_TX;
891 spi_imx->dma_is_inited = 1;
892
893 return 0;
894 err:
895 spi_imx_sdma_exit(spi_imx);
896 return ret;
897 }
898
899 static void spi_imx_dma_rx_callback(void *cookie)
900 {
901 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
902
903 complete(&spi_imx->dma_rx_completion);
904 }
905
906 static void spi_imx_dma_tx_callback(void *cookie)
907 {
908 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
909
910 complete(&spi_imx->dma_tx_completion);
911 }
912
913 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
914 {
915 unsigned long timeout = 0;
916
917 /* Time with actual data transfer and CS change delay related to HW */
918 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
919
920 /* Add extra second for scheduler related activities */
921 timeout += 1;
922
923 /* Double calculated timeout */
924 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
925 }
926
927 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
928 struct spi_transfer *transfer)
929 {
930 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
931 int ret;
932 unsigned long transfer_timeout;
933 unsigned long timeout;
934 struct spi_master *master = spi_imx->bitbang.master;
935 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
936
937 if (tx) {
938 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
939 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
940 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
941 if (!desc_tx)
942 return -EINVAL;
943
944 desc_tx->callback = spi_imx_dma_tx_callback;
945 desc_tx->callback_param = (void *)spi_imx;
946 dmaengine_submit(desc_tx);
947 }
948
949 if (rx) {
950 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
951 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
952 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
953 if (!desc_rx) {
954 dmaengine_terminate_all(master->dma_tx);
955 return -EINVAL;
956 }
957
958 desc_rx->callback = spi_imx_dma_rx_callback;
959 desc_rx->callback_param = (void *)spi_imx;
960 dmaengine_submit(desc_rx);
961 }
962
963 reinit_completion(&spi_imx->dma_rx_completion);
964 reinit_completion(&spi_imx->dma_tx_completion);
965
966 /* Trigger the cspi module. */
967 spi_imx->dma_finished = 0;
968
969 /*
970 * Set these order to avoid potential RX overflow. The overflow may
971 * happen if we enable SPI HW before starting RX DMA due to rescheduling
972 * for another task and/or interrupt.
973 * So RX DMA enabled first to make sure data would be read out from FIFO
974 * ASAP. TX DMA enabled next to start filling TX FIFO with new data.
975 * And finaly SPI HW enabled to start actual data transfer.
976 */
977 dma_async_issue_pending(master->dma_rx);
978 dma_async_issue_pending(master->dma_tx);
979 spi_imx->devtype_data->trigger(spi_imx);
980
981 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
982
983 /* Wait SDMA to finish the data transfer.*/
984 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
985 transfer_timeout);
986 if (!timeout) {
987 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
988 dmaengine_terminate_all(master->dma_tx);
989 dmaengine_terminate_all(master->dma_rx);
990 } else {
991 timeout = wait_for_completion_timeout(
992 &spi_imx->dma_rx_completion, transfer_timeout);
993 if (!timeout) {
994 dev_err(spi_imx->dev, "I/O Error in DMA RX\n");
995 spi_imx->devtype_data->reset(spi_imx);
996 dmaengine_terminate_all(master->dma_rx);
997 }
998 }
999
1000 spi_imx->dma_finished = 1;
1001 spi_imx->devtype_data->trigger(spi_imx);
1002
1003 if (!timeout)
1004 ret = -ETIMEDOUT;
1005 else
1006 ret = transfer->len;
1007
1008 return ret;
1009 }
1010
1011 static int spi_imx_pio_transfer(struct spi_device *spi,
1012 struct spi_transfer *transfer)
1013 {
1014 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1015
1016 spi_imx->tx_buf = transfer->tx_buf;
1017 spi_imx->rx_buf = transfer->rx_buf;
1018 spi_imx->count = transfer->len;
1019 spi_imx->txfifo = 0;
1020
1021 reinit_completion(&spi_imx->xfer_done);
1022
1023 spi_imx_push(spi_imx);
1024
1025 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1026
1027 wait_for_completion(&spi_imx->xfer_done);
1028
1029 return transfer->len;
1030 }
1031
1032 static int spi_imx_transfer(struct spi_device *spi,
1033 struct spi_transfer *transfer)
1034 {
1035 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1036
1037 if (spi_imx->usedma)
1038 return spi_imx_dma_transfer(spi_imx, transfer);
1039 else
1040 return spi_imx_pio_transfer(spi, transfer);
1041 }
1042
1043 static int spi_imx_setup(struct spi_device *spi)
1044 {
1045 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1046 int gpio = spi_imx->chipselect[spi->chip_select];
1047
1048 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1049 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1050
1051 if (gpio_is_valid(gpio))
1052 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1053
1054 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1055
1056 return 0;
1057 }
1058
1059 static void spi_imx_cleanup(struct spi_device *spi)
1060 {
1061 }
1062
1063 static int
1064 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1065 {
1066 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1067 int ret;
1068
1069 ret = clk_enable(spi_imx->clk_per);
1070 if (ret)
1071 return ret;
1072
1073 ret = clk_enable(spi_imx->clk_ipg);
1074 if (ret) {
1075 clk_disable(spi_imx->clk_per);
1076 return ret;
1077 }
1078
1079 return 0;
1080 }
1081
1082 static int
1083 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1084 {
1085 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1086
1087 clk_disable(spi_imx->clk_ipg);
1088 clk_disable(spi_imx->clk_per);
1089 return 0;
1090 }
1091
1092 static int spi_imx_probe(struct platform_device *pdev)
1093 {
1094 struct device_node *np = pdev->dev.of_node;
1095 const struct of_device_id *of_id =
1096 of_match_device(spi_imx_dt_ids, &pdev->dev);
1097 struct spi_imx_master *mxc_platform_info =
1098 dev_get_platdata(&pdev->dev);
1099 struct spi_master *master;
1100 struct spi_imx_data *spi_imx;
1101 struct resource *res;
1102 int i, ret, num_cs, irq;
1103
1104 if (!np && !mxc_platform_info) {
1105 dev_err(&pdev->dev, "can't get the platform data\n");
1106 return -EINVAL;
1107 }
1108
1109 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1110 if (ret < 0) {
1111 if (mxc_platform_info)
1112 num_cs = mxc_platform_info->num_chipselect;
1113 else
1114 return ret;
1115 }
1116
1117 master = spi_alloc_master(&pdev->dev,
1118 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1119 if (!master)
1120 return -ENOMEM;
1121
1122 platform_set_drvdata(pdev, master);
1123
1124 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1125 master->bus_num = pdev->id;
1126 master->num_chipselect = num_cs;
1127
1128 spi_imx = spi_master_get_devdata(master);
1129 spi_imx->bitbang.master = master;
1130 spi_imx->dev = &pdev->dev;
1131
1132 spi_imx->devtype_data = of_id ? of_id->data :
1133 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1134
1135 for (i = 0; i < master->num_chipselect; i++) {
1136 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1137 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1138 cs_gpio = mxc_platform_info->chipselect[i];
1139
1140 spi_imx->chipselect[i] = cs_gpio;
1141 if (!gpio_is_valid(cs_gpio))
1142 continue;
1143
1144 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1145 DRIVER_NAME);
1146 if (ret) {
1147 dev_err(&pdev->dev, "can't get cs gpios\n");
1148 goto out_master_put;
1149 }
1150 }
1151
1152 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1153 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1154 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1155 spi_imx->bitbang.master->setup = spi_imx_setup;
1156 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1157 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1158 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1159 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1160 if (is_imx51_ecspi(spi_imx))
1161 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1162
1163 init_completion(&spi_imx->xfer_done);
1164
1165 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1166 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1167 if (IS_ERR(spi_imx->base)) {
1168 ret = PTR_ERR(spi_imx->base);
1169 goto out_master_put;
1170 }
1171
1172 irq = platform_get_irq(pdev, 0);
1173 if (irq < 0) {
1174 ret = irq;
1175 goto out_master_put;
1176 }
1177
1178 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1179 dev_name(&pdev->dev), spi_imx);
1180 if (ret) {
1181 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1182 goto out_master_put;
1183 }
1184
1185 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1186 if (IS_ERR(spi_imx->clk_ipg)) {
1187 ret = PTR_ERR(spi_imx->clk_ipg);
1188 goto out_master_put;
1189 }
1190
1191 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1192 if (IS_ERR(spi_imx->clk_per)) {
1193 ret = PTR_ERR(spi_imx->clk_per);
1194 goto out_master_put;
1195 }
1196
1197 ret = clk_prepare_enable(spi_imx->clk_per);
1198 if (ret)
1199 goto out_master_put;
1200
1201 ret = clk_prepare_enable(spi_imx->clk_ipg);
1202 if (ret)
1203 goto out_put_per;
1204
1205 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1206 /*
1207 * Only validated on i.mx6 now, can remove the constrain if validated on
1208 * other chips.
1209 */
1210 if (is_imx51_ecspi(spi_imx)) {
1211 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res);
1212 if (ret == -EPROBE_DEFER)
1213 goto out_clk_put;
1214
1215 if (ret < 0)
1216 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1217 ret);
1218 }
1219
1220 spi_imx->devtype_data->reset(spi_imx);
1221
1222 spi_imx->devtype_data->intctrl(spi_imx, 0);
1223
1224 master->dev.of_node = pdev->dev.of_node;
1225 ret = spi_bitbang_start(&spi_imx->bitbang);
1226 if (ret) {
1227 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1228 goto out_clk_put;
1229 }
1230
1231 dev_info(&pdev->dev, "probed\n");
1232
1233 clk_disable(spi_imx->clk_ipg);
1234 clk_disable(spi_imx->clk_per);
1235 return ret;
1236
1237 out_clk_put:
1238 clk_disable_unprepare(spi_imx->clk_ipg);
1239 out_put_per:
1240 clk_disable_unprepare(spi_imx->clk_per);
1241 out_master_put:
1242 spi_master_put(master);
1243
1244 return ret;
1245 }
1246
1247 static int spi_imx_remove(struct platform_device *pdev)
1248 {
1249 struct spi_master *master = platform_get_drvdata(pdev);
1250 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1251
1252 spi_bitbang_stop(&spi_imx->bitbang);
1253
1254 writel(0, spi_imx->base + MXC_CSPICTRL);
1255 clk_unprepare(spi_imx->clk_ipg);
1256 clk_unprepare(spi_imx->clk_per);
1257 spi_imx_sdma_exit(spi_imx);
1258 spi_master_put(master);
1259
1260 return 0;
1261 }
1262
1263 static struct platform_driver spi_imx_driver = {
1264 .driver = {
1265 .name = DRIVER_NAME,
1266 .of_match_table = spi_imx_dt_ids,
1267 },
1268 .id_table = spi_imx_devtype,
1269 .probe = spi_imx_probe,
1270 .remove = spi_imx_remove,
1271 };
1272 module_platform_driver(spi_imx_driver);
1273
1274 MODULE_DESCRIPTION("SPI Master Controller driver");
1275 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1276 MODULE_LICENSE("GPL");
1277 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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