drivers/spi/spi-mt65xx.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Leilk Liu <leilk.liu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/spi-mt65xx.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/spi/spi.h>
  27
  28 #define SPI_CFG0_REG                      0x0000
  29 #define SPI_CFG1_REG                      0x0004
  30 #define SPI_TX_SRC_REG                    0x0008
  31 #define SPI_RX_DST_REG                    0x000c
  32 #define SPI_TX_DATA_REG                   0x0010
  33 #define SPI_RX_DATA_REG                   0x0014
  34 #define SPI_CMD_REG                       0x0018
  35 #define SPI_STATUS0_REG                   0x001c
  36 #define SPI_PAD_SEL_REG                   0x0024
  37
  38 #define SPI_CFG0_SCK_HIGH_OFFSET          0
  39 #define SPI_CFG0_SCK_LOW_OFFSET           8
  40 #define SPI_CFG0_CS_HOLD_OFFSET           16
  41 #define SPI_CFG0_CS_SETUP_OFFSET          24
  42
  43 #define SPI_CFG1_CS_IDLE_OFFSET           0
  44 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
  45 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
  46 #define SPI_CFG1_GET_TICK_DLY_OFFSET      30
  47
  48 #define SPI_CFG1_CS_IDLE_MASK             0xff
  49 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
  50 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
  51
  52 #define SPI_CMD_ACT                  BIT(0)
  53 #define SPI_CMD_RESUME               BIT(1)
  54 #define SPI_CMD_RST                  BIT(2)
  55 #define SPI_CMD_PAUSE_EN             BIT(4)
  56 #define SPI_CMD_DEASSERT             BIT(5)
  57 #define SPI_CMD_CPHA                 BIT(8)
  58 #define SPI_CMD_CPOL                 BIT(9)
  59 #define SPI_CMD_RX_DMA               BIT(10)
  60 #define SPI_CMD_TX_DMA               BIT(11)
  61 #define SPI_CMD_TXMSBF               BIT(12)
  62 #define SPI_CMD_RXMSBF               BIT(13)
  63 #define SPI_CMD_RX_ENDIAN            BIT(14)
  64 #define SPI_CMD_TX_ENDIAN            BIT(15)
  65 #define SPI_CMD_FINISH_IE            BIT(16)
  66 #define SPI_CMD_PAUSE_IE             BIT(17)
  67
  68 #define MT8173_SPI_MAX_PAD_SEL 3
  69
  70 #define MTK_SPI_PAUSE_INT_STATUS 0x2
  71
  72 #define MTK_SPI_IDLE 0
  73 #define MTK_SPI_PAUSED 1
  74
  75 #define MTK_SPI_MAX_FIFO_SIZE 32
  76 #define MTK_SPI_PACKET_SIZE 1024
  77
  78 struct mtk_spi_compatible {
  79         bool need_pad_sel;
  80         /* Must explicitly send dummy Tx bytes to do Rx only transfer */
  81         bool must_tx;
  82 };
  83
  84 struct mtk_spi {
  85         void __iomem *base;
  86         u32 state;
  87         u32 pad_sel;
  88         struct clk *parent_clk, *sel_clk, *spi_clk;
  89         struct spi_transfer *cur_transfer;
  90         u32 xfer_len;
  91         struct scatterlist *tx_sgl, *rx_sgl;
  92         u32 tx_sgl_len, rx_sgl_len;
  93         const struct mtk_spi_compatible *dev_comp;
  94 };
  95
  96 static const struct mtk_spi_compatible mt6589_compat;
  97 static const struct mtk_spi_compatible mt8135_compat;
  98 static const struct mtk_spi_compatible mt8173_compat = {
  99         .need_pad_sel = true,
 100         .must_tx = true,
 101 };
 102
 103 /*
 104  * A piece of default chip info unless the platform
 105  * supplies it.
 106  */
 107 static const struct mtk_chip_config mtk_default_chip_info = {
 108         .rx_mlsb = 1,
 109         .tx_mlsb = 1,
 110 };
 111
 112 static const struct of_device_id mtk_spi_of_match[] = {
 113         { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
 114         { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
 115         { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
 116         {}
 117 };
 118 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
 119
 120 static void mtk_spi_reset(struct mtk_spi *mdata)
 121 {
 122         u32 reg_val;
 123
 124         /* set the software reset bit in SPI_CMD_REG. */
 125         reg_val = readl(mdata->base + SPI_CMD_REG);
 126         reg_val |= SPI_CMD_RST;
 127         writel(reg_val, mdata->base + SPI_CMD_REG);
 128
 129         reg_val = readl(mdata->base + SPI_CMD_REG);
 130         reg_val &= ~SPI_CMD_RST;
 131         writel(reg_val, mdata->base + SPI_CMD_REG);
 132 }
 133
 134 static int mtk_spi_prepare_message(struct spi_master *master,
 135                                    struct spi_message *msg)
 136 {
 137         u16 cpha, cpol;
 138         u32 reg_val;
 139         struct mtk_chip_config *chip_config;
 140         struct spi_device *spi = msg->spi;
 141         struct mtk_spi *mdata = spi_master_get_devdata(master);
 142
 143         cpha = spi->mode & SPI_CPHA ? 1 : 0;
 144         cpol = spi->mode & SPI_CPOL ? 1 : 0;
 145
 146         chip_config = spi->controller_data;
 147         if (!chip_config) {
 148                 chip_config = (void *)&mtk_default_chip_info;
 149                 spi->controller_data = chip_config;
 150         }
 151
 152         reg_val = readl(mdata->base + SPI_CMD_REG);
 153         if (cpha)
 154                 reg_val |= SPI_CMD_CPHA;
 155         else
 156                 reg_val &= ~SPI_CMD_CPHA;
 157         if (cpol)
 158                 reg_val |= SPI_CMD_CPOL;
 159         else
 160                 reg_val &= ~SPI_CMD_CPOL;
 161         writel(reg_val, mdata->base + SPI_CMD_REG);
 162
 163         reg_val = readl(mdata->base + SPI_CMD_REG);
 164
 165         /* set the mlsbx and mlsbtx */
 166         if (chip_config->tx_mlsb)
 167                 reg_val |= SPI_CMD_TXMSBF;
 168         else
 169                 reg_val &= ~SPI_CMD_TXMSBF;
 170         if (chip_config->rx_mlsb)
 171                 reg_val |= SPI_CMD_RXMSBF;
 172         else
 173                 reg_val &= ~SPI_CMD_RXMSBF;
 174
 175         /* set the tx/rx endian */
 176 #ifdef __LITTLE_ENDIAN
 177         reg_val &= ~SPI_CMD_TX_ENDIAN;
 178         reg_val &= ~SPI_CMD_RX_ENDIAN;
 179 #else
 180         reg_val |= SPI_CMD_TX_ENDIAN;
 181         reg_val |= SPI_CMD_RX_ENDIAN;
 182 #endif
 183
 184         /* set finish and pause interrupt always enable */
 185         reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
 186
 187         /* disable dma mode */
 188         reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
 189
 190         /* disable deassert mode */
 191         reg_val &= ~SPI_CMD_DEASSERT;
 192
 193         writel(reg_val, mdata->base + SPI_CMD_REG);
 194
 195         /* pad select */
 196         if (mdata->dev_comp->need_pad_sel)
 197                 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
 198
 199         return 0;
 200 }
 201
 202 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
 203 {
 204         u32 reg_val;
 205         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 206
 207         reg_val = readl(mdata->base + SPI_CMD_REG);
 208         if (!enable) {
 209                 reg_val |= SPI_CMD_PAUSE_EN;
 210                 writel(reg_val, mdata->base + SPI_CMD_REG);
 211         } else {
 212                 reg_val &= ~SPI_CMD_PAUSE_EN;
 213                 writel(reg_val, mdata->base + SPI_CMD_REG);
 214                 mdata->state = MTK_SPI_IDLE;
 215                 mtk_spi_reset(mdata);
 216         }
 217 }
 218
 219 static void mtk_spi_prepare_transfer(struct spi_master *master,
 220                                      struct spi_transfer *xfer)
 221 {
 222         u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
 223         struct mtk_spi *mdata = spi_master_get_devdata(master);
 224
 225         spi_clk_hz = clk_get_rate(mdata->spi_clk);
 226         if (xfer->speed_hz < spi_clk_hz / 2)
 227                 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
 228         else
 229                 div = 1;
 230
 231         sck_time = (div + 1) / 2;
 232         cs_time = sck_time * 2;
 233
 234         reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
 235         reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
 236         reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
 237         reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
 238         writel(reg_val, mdata->base + SPI_CFG0_REG);
 239
 240         reg_val = readl(mdata->base + SPI_CFG1_REG);
 241         reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
 242         reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
 243         writel(reg_val, mdata->base + SPI_CFG1_REG);
 244 }
 245
 246 static void mtk_spi_setup_packet(struct spi_master *master)
 247 {
 248         u32 packet_size, packet_loop, reg_val;
 249         struct mtk_spi *mdata = spi_master_get_devdata(master);
 250
 251         packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
 252         packet_loop = mdata->xfer_len / packet_size;
 253
 254         reg_val = readl(mdata->base + SPI_CFG1_REG);
 255         reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
 256         reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
 257         reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
 258         writel(reg_val, mdata->base + SPI_CFG1_REG);
 259 }
 260
 261 static void mtk_spi_enable_transfer(struct spi_master *master)
 262 {
 263         u32 cmd;
 264         struct mtk_spi *mdata = spi_master_get_devdata(master);
 265
 266         cmd = readl(mdata->base + SPI_CMD_REG);
 267         if (mdata->state == MTK_SPI_IDLE)
 268                 cmd |= SPI_CMD_ACT;
 269         else
 270                 cmd |= SPI_CMD_RESUME;
 271         writel(cmd, mdata->base + SPI_CMD_REG);
 272 }
 273
 274 static int mtk_spi_get_mult_delta(u32 xfer_len)
 275 {
 276         u32 mult_delta;
 277
 278         if (xfer_len > MTK_SPI_PACKET_SIZE)
 279                 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
 280         else
 281                 mult_delta = 0;
 282
 283         return mult_delta;
 284 }
 285
 286 static void mtk_spi_update_mdata_len(struct spi_master *master)
 287 {
 288         int mult_delta;
 289         struct mtk_spi *mdata = spi_master_get_devdata(master);
 290
 291         if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
 292                 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
 293                         mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 294                         mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 295                         mdata->rx_sgl_len = mult_delta;
 296                         mdata->tx_sgl_len -= mdata->xfer_len;
 297                 } else {
 298                         mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 299                         mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 300                         mdata->tx_sgl_len = mult_delta;
 301                         mdata->rx_sgl_len -= mdata->xfer_len;
 302                 }
 303         } else if (mdata->tx_sgl_len) {
 304                 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 305                 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 306                 mdata->tx_sgl_len = mult_delta;
 307         } else if (mdata->rx_sgl_len) {
 308                 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 309                 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 310                 mdata->rx_sgl_len = mult_delta;
 311         }
 312 }
 313
 314 static void mtk_spi_setup_dma_addr(struct spi_master *master,
 315                                    struct spi_transfer *xfer)
 316 {
 317         struct mtk_spi *mdata = spi_master_get_devdata(master);
 318
 319         if (mdata->tx_sgl)
 320                 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
 321         if (mdata->rx_sgl)
 322                 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
 323 }
 324
 325 static int mtk_spi_fifo_transfer(struct spi_master *master,
 326                                  struct spi_device *spi,
 327                                  struct spi_transfer *xfer)
 328 {
 329         int cnt;
 330         struct mtk_spi *mdata = spi_master_get_devdata(master);
 331
 332         mdata->cur_transfer = xfer;
 333         mdata->xfer_len = xfer->len;
 334         mtk_spi_prepare_transfer(master, xfer);
 335         mtk_spi_setup_packet(master);
 336
 337         if (xfer->len % 4)
 338                 cnt = xfer->len / 4 + 1;
 339         else
 340                 cnt = xfer->len / 4;
 341         iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
 342
 343         mtk_spi_enable_transfer(master);
 344
 345         return 1;
 346 }
 347
 348 static int mtk_spi_dma_transfer(struct spi_master *master,
 349                                 struct spi_device *spi,
 350                                 struct spi_transfer *xfer)
 351 {
 352         int cmd;
 353         struct mtk_spi *mdata = spi_master_get_devdata(master);
 354
 355         mdata->tx_sgl = NULL;
 356         mdata->rx_sgl = NULL;
 357         mdata->tx_sgl_len = 0;
 358         mdata->rx_sgl_len = 0;
 359         mdata->cur_transfer = xfer;
 360
 361         mtk_spi_prepare_transfer(master, xfer);
 362
 363         cmd = readl(mdata->base + SPI_CMD_REG);
 364         if (xfer->tx_buf)
 365                 cmd |= SPI_CMD_TX_DMA;
 366         if (xfer->rx_buf)
 367                 cmd |= SPI_CMD_RX_DMA;
 368         writel(cmd, mdata->base + SPI_CMD_REG);
 369
 370         if (xfer->tx_buf)
 371                 mdata->tx_sgl = xfer->tx_sg.sgl;
 372         if (xfer->rx_buf)
 373                 mdata->rx_sgl = xfer->rx_sg.sgl;
 374
 375         if (mdata->tx_sgl) {
 376                 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
 377                 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 378         }
 379         if (mdata->rx_sgl) {
 380                 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
 381                 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 382         }
 383
 384         mtk_spi_update_mdata_len(master);
 385         mtk_spi_setup_packet(master);
 386         mtk_spi_setup_dma_addr(master, xfer);
 387         mtk_spi_enable_transfer(master);
 388
 389         return 1;
 390 }
 391
 392 static int mtk_spi_transfer_one(struct spi_master *master,
 393                                 struct spi_device *spi,
 394                                 struct spi_transfer *xfer)
 395 {
 396         if (master->can_dma(master, spi, xfer))
 397                 return mtk_spi_dma_transfer(master, spi, xfer);
 398         else
 399                 return mtk_spi_fifo_transfer(master, spi, xfer);
 400 }
 401
 402 static bool mtk_spi_can_dma(struct spi_master *master,
 403                             struct spi_device *spi,
 404                             struct spi_transfer *xfer)
 405 {
 406         return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
 407 }
 408
 409 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
 410 {
 411         u32 cmd, reg_val, cnt;
 412         struct spi_master *master = dev_id;
 413         struct mtk_spi *mdata = spi_master_get_devdata(master);
 414         struct spi_transfer *trans = mdata->cur_transfer;
 415
 416         reg_val = readl(mdata->base + SPI_STATUS0_REG);
 417         if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
 418                 mdata->state = MTK_SPI_PAUSED;
 419         else
 420                 mdata->state = MTK_SPI_IDLE;
 421
 422         if (!master->can_dma(master, master->cur_msg->spi, trans)) {
 423                 if (trans->rx_buf) {
 424                         if (mdata->xfer_len % 4)
 425                                 cnt = mdata->xfer_len / 4 + 1;
 426                         else
 427                                 cnt = mdata->xfer_len / 4;
 428                         ioread32_rep(mdata->base + SPI_RX_DATA_REG,
 429                                      trans->rx_buf, cnt);
 430                 }
 431                 spi_finalize_current_transfer(master);
 432                 return IRQ_HANDLED;
 433         }
 434
 435         if (mdata->tx_sgl)
 436                 trans->tx_dma += mdata->xfer_len;
 437         if (mdata->rx_sgl)
 438                 trans->rx_dma += mdata->xfer_len;
 439
 440         if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
 441                 mdata->tx_sgl = sg_next(mdata->tx_sgl);
 442                 if (mdata->tx_sgl) {
 443                         trans->tx_dma = sg_dma_address(mdata->tx_sgl);
 444                         mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 445                 }
 446         }
 447         if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
 448                 mdata->rx_sgl = sg_next(mdata->rx_sgl);
 449                 if (mdata->rx_sgl) {
 450                         trans->rx_dma = sg_dma_address(mdata->rx_sgl);
 451                         mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 452                 }
 453         }
 454
 455         if (!mdata->tx_sgl && !mdata->rx_sgl) {
 456                 /* spi disable dma */
 457                 cmd = readl(mdata->base + SPI_CMD_REG);
 458                 cmd &= ~SPI_CMD_TX_DMA;
 459                 cmd &= ~SPI_CMD_RX_DMA;
 460                 writel(cmd, mdata->base + SPI_CMD_REG);
 461
 462                 spi_finalize_current_transfer(master);
 463                 return IRQ_HANDLED;
 464         }
 465
 466         mtk_spi_update_mdata_len(master);
 467         mtk_spi_setup_packet(master);
 468         mtk_spi_setup_dma_addr(master, trans);
 469         mtk_spi_enable_transfer(master);
 470
 471         return IRQ_HANDLED;
 472 }
 473
 474 static int mtk_spi_probe(struct platform_device *pdev)
 475 {
 476         struct spi_master *master;
 477         struct mtk_spi *mdata;
 478         const struct of_device_id *of_id;
 479         struct resource *res;
 480         int irq, ret;
 481
 482         master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
 483         if (!master) {
 484                 dev_err(&pdev->dev, "failed to alloc spi master\n");
 485                 return -ENOMEM;
 486         }
 487
 488         master->auto_runtime_pm = true;
 489         master->dev.of_node = pdev->dev.of_node;
 490         master->mode_bits = SPI_CPOL | SPI_CPHA;
 491
 492         master->set_cs = mtk_spi_set_cs;
 493         master->prepare_message = mtk_spi_prepare_message;
 494         master->transfer_one = mtk_spi_transfer_one;
 495         master->can_dma = mtk_spi_can_dma;
 496
 497         of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
 498         if (!of_id) {
 499                 dev_err(&pdev->dev, "failed to probe of_node\n");
 500                 ret = -EINVAL;
 501                 goto err_put_master;
 502         }
 503
 504         mdata = spi_master_get_devdata(master);
 505         mdata->dev_comp = of_id->data;
 506         if (mdata->dev_comp->must_tx)
 507                 master->flags = SPI_MASTER_MUST_TX;
 508
 509         if (mdata->dev_comp->need_pad_sel) {
 510                 ret = of_property_read_u32(pdev->dev.of_node,
 511                                            "mediatek,pad-select",
 512                                            &mdata->pad_sel);
 513                 if (ret) {
 514                         dev_err(&pdev->dev, "failed to read pad select: %d\n",
 515                                 ret);
 516                         goto err_put_master;
 517                 }
 518
 519                 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
 520                         dev_err(&pdev->dev, "wrong pad-select: %u\n",
 521                                 mdata->pad_sel);
 522                         ret = -EINVAL;
 523                         goto err_put_master;
 524                 }
 525         }
 526
 527         platform_set_drvdata(pdev, master);
 528
 529         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 530         if (!res) {
 531                 ret = -ENODEV;
 532                 dev_err(&pdev->dev, "failed to determine base address\n");
 533                 goto err_put_master;
 534         }
 535
 536         mdata->base = devm_ioremap_resource(&pdev->dev, res);
 537         if (IS_ERR(mdata->base)) {
 538                 ret = PTR_ERR(mdata->base);
 539                 goto err_put_master;
 540         }
 541
 542         irq = platform_get_irq(pdev, 0);
 543         if (irq < 0) {
 544                 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
 545                 ret = irq;
 546                 goto err_put_master;
 547         }
 548
 549         if (!pdev->dev.dma_mask)
 550                 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 551
 552         ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
 553                                IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
 554         if (ret) {
 555                 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
 556                 goto err_put_master;
 557         }
 558
 559         mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
 560         if (IS_ERR(mdata->parent_clk)) {
 561                 ret = PTR_ERR(mdata->parent_clk);
 562                 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
 563                 goto err_put_master;
 564         }
 565
 566         mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
 567         if (IS_ERR(mdata->sel_clk)) {
 568                 ret = PTR_ERR(mdata->sel_clk);
 569                 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
 570                 goto err_put_master;
 571         }
 572
 573         mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
 574         if (IS_ERR(mdata->spi_clk)) {
 575                 ret = PTR_ERR(mdata->spi_clk);
 576                 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
 577                 goto err_put_master;
 578         }
 579
 580         ret = clk_prepare_enable(mdata->spi_clk);
 581         if (ret < 0) {
 582                 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
 583                 goto err_put_master;
 584         }
 585
 586         ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
 587         if (ret < 0) {
 588                 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
 589                 goto err_disable_clk;
 590         }
 591
 592         clk_disable_unprepare(mdata->spi_clk);
 593
 594         pm_runtime_enable(&pdev->dev);
 595
 596         ret = devm_spi_register_master(&pdev->dev, master);
 597         if (ret) {
 598                 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
 599                 goto err_put_master;
 600         }
 601
 602         return 0;
 603
 604 err_disable_clk:
 605         clk_disable_unprepare(mdata->spi_clk);
 606 err_put_master:
 607         spi_master_put(master);
 608
 609         return ret;
 610 }
 611
 612 static int mtk_spi_remove(struct platform_device *pdev)
 613 {
 614         struct spi_master *master = platform_get_drvdata(pdev);
 615         struct mtk_spi *mdata = spi_master_get_devdata(master);
 616
 617         pm_runtime_disable(&pdev->dev);
 618
 619         mtk_spi_reset(mdata);
 620         spi_master_put(master);
 621
 622         return 0;
 623 }
 624
 625 #ifdef CONFIG_PM_SLEEP
 626 static int mtk_spi_suspend(struct device *dev)
 627 {
 628         int ret;
 629         struct spi_master *master = dev_get_drvdata(dev);
 630         struct mtk_spi *mdata = spi_master_get_devdata(master);
 631
 632         ret = spi_master_suspend(master);
 633         if (ret)
 634                 return ret;
 635
 636         if (!pm_runtime_suspended(dev))
 637                 clk_disable_unprepare(mdata->spi_clk);
 638
 639         return ret;
 640 }
 641
 642 static int mtk_spi_resume(struct device *dev)
 643 {
 644         int ret;
 645         struct spi_master *master = dev_get_drvdata(dev);
 646         struct mtk_spi *mdata = spi_master_get_devdata(master);
 647
 648         if (!pm_runtime_suspended(dev)) {
 649                 ret = clk_prepare_enable(mdata->spi_clk);
 650                 if (ret < 0) {
 651                         dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 652                         return ret;
 653                 }
 654         }
 655
 656         ret = spi_master_resume(master);
 657         if (ret < 0)
 658                 clk_disable_unprepare(mdata->spi_clk);
 659
 660         return ret;
 661 }
 662 #endif /* CONFIG_PM_SLEEP */
 663
 664 #ifdef CONFIG_PM
 665 static int mtk_spi_runtime_suspend(struct device *dev)
 666 {
 667         struct spi_master *master = dev_get_drvdata(dev);
 668         struct mtk_spi *mdata = spi_master_get_devdata(master);
 669
 670         clk_disable_unprepare(mdata->spi_clk);
 671
 672         return 0;
 673 }
 674
 675 static int mtk_spi_runtime_resume(struct device *dev)
 676 {
 677         struct spi_master *master = dev_get_drvdata(dev);
 678         struct mtk_spi *mdata = spi_master_get_devdata(master);
 679         int ret;
 680
 681         ret = clk_prepare_enable(mdata->spi_clk);
 682         if (ret < 0) {
 683                 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 684                 return ret;
 685         }
 686
 687         return 0;
 688 }
 689 #endif /* CONFIG_PM */
 690
 691 static const struct dev_pm_ops mtk_spi_pm = {
 692         SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
 693         SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
 694                            mtk_spi_runtime_resume, NULL)
 695 };
 696
 697 static struct platform_driver mtk_spi_driver = {
 698         .driver = {
 699                 .name = "mtk-spi",
 700                 .pm     = &mtk_spi_pm,
 701                 .of_match_table = mtk_spi_of_match,
 702         },
 703         .probe = mtk_spi_probe,
 704         .remove = mtk_spi_remove,
 705 };
 706
 707 module_platform_driver(mtk_spi_driver);
 708
 709 MODULE_DESCRIPTION("MTK SPI Controller driver");
 710 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
 711 MODULE_LICENSE("GPL v2");
 712 MODULE_ALIAS("platform:mtk-spi");