2 * Freescale MXS SPI master driver
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
42 #include <linux/highmem.h>
43 #include <linux/clk.h>
44 #include <linux/err.h>
45 #include <linux/completion.h>
46 #include <linux/gpio.h>
47 #include <linux/regulator/consumer.h>
48 #include <linux/module.h>
49 #include <linux/stmp_device.h>
50 #include <linux/spi/spi.h>
51 #include <linux/spi/mxs-spi.h>
53 #define DRIVER_NAME "mxs-spi"
55 /* Use 10S timeout for very long transfers, it should suffice. */
56 #define SSP_TIMEOUT 10000
58 #define SG_MAXLEN 0xff00
61 * Flags for txrx functions. More efficient that using an argument register for
64 #define TXRX_WRITE (1<<0) /* This is a write */
65 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
70 unsigned int sck
; /* Rate requested (vs actual) */
73 static int mxs_spi_setup_transfer(struct spi_device
*dev
,
74 const struct spi_transfer
*t
)
76 struct mxs_spi
*spi
= spi_master_get_devdata(dev
->master
);
77 struct mxs_ssp
*ssp
= &spi
->ssp
;
78 const unsigned int hz
= min(dev
->max_speed_hz
, t
->speed_hz
);
81 dev_err(&dev
->dev
, "SPI clock rate of zero not allowed\n");
86 mxs_ssp_set_clk_rate(ssp
, hz
);
88 * Save requested rate, hz, rather than the actual rate,
89 * ssp->clk_rate. Otherwise we would set the rate every trasfer
90 * when the actual rate is not quite the same as requested rate.
94 * Perhaps we should return an error if the actual clock is
95 * nowhere close to what was requested?
99 writel(BM_SSP_CTRL0_LOCK_CS
,
100 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
102 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI
) |
103 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS
) |
104 ((dev
->mode
& SPI_CPOL
) ? BM_SSP_CTRL1_POLARITY
: 0) |
105 ((dev
->mode
& SPI_CPHA
) ? BM_SSP_CTRL1_PHASE
: 0),
106 ssp
->base
+ HW_SSP_CTRL1(ssp
));
108 writel(0x0, ssp
->base
+ HW_SSP_CMD0
);
109 writel(0x0, ssp
->base
+ HW_SSP_CMD1
);
114 static int mxs_spi_setup(struct spi_device
*dev
)
116 if (!dev
->bits_per_word
)
117 dev
->bits_per_word
= 8;
122 static u32
mxs_spi_cs_to_reg(unsigned cs
)
127 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
129 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
130 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
131 * the datasheet for further details. In SPI mode, they are used to
132 * toggle the chip-select lines (nCS pins).
135 select
|= BM_SSP_CTRL0_WAIT_FOR_CMD
;
137 select
|= BM_SSP_CTRL0_WAIT_FOR_IRQ
;
142 static int mxs_ssp_wait(struct mxs_spi
*spi
, int offset
, int mask
, bool set
)
144 const unsigned long timeout
= jiffies
+ msecs_to_jiffies(SSP_TIMEOUT
);
145 struct mxs_ssp
*ssp
= &spi
->ssp
;
149 reg
= readl_relaxed(ssp
->base
+ offset
);
158 } while (time_before(jiffies
, timeout
));
163 static void mxs_ssp_dma_irq_callback(void *param
)
165 struct mxs_spi
*spi
= param
;
169 static irqreturn_t
mxs_ssp_irq_handler(int irq
, void *dev_id
)
171 struct mxs_ssp
*ssp
= dev_id
;
172 dev_err(ssp
->dev
, "%s[%i] CTRL1=%08x STATUS=%08x\n",
174 readl(ssp
->base
+ HW_SSP_CTRL1(ssp
)),
175 readl(ssp
->base
+ HW_SSP_STATUS(ssp
)));
179 static int mxs_spi_txrx_dma(struct mxs_spi
*spi
,
180 unsigned char *buf
, int len
,
183 struct mxs_ssp
*ssp
= &spi
->ssp
;
184 struct dma_async_tx_descriptor
*desc
= NULL
;
185 const bool vmalloced_buf
= is_vmalloc_addr(buf
);
186 const int desc_len
= vmalloced_buf
? PAGE_SIZE
: SG_MAXLEN
;
187 const int sgs
= DIV_ROUND_UP(len
, desc_len
);
191 struct page
*vm_page
;
195 struct scatterlist sg
;
201 dma_xfer
= kzalloc(sizeof(*dma_xfer
) * sgs
, GFP_KERNEL
);
205 reinit_completion(&spi
->c
);
207 /* Chip select was already programmed into CTRL0 */
208 ctrl0
= readl(ssp
->base
+ HW_SSP_CTRL0
);
209 ctrl0
&= ~(BM_SSP_CTRL0_XFER_COUNT
| BM_SSP_CTRL0_IGNORE_CRC
|
211 ctrl0
|= BM_SSP_CTRL0_DATA_XFER
;
213 if (!(flags
& TXRX_WRITE
))
214 ctrl0
|= BM_SSP_CTRL0_READ
;
216 /* Queue the DMA data transfer. */
217 for (sg_count
= 0; sg_count
< sgs
; sg_count
++) {
218 /* Prepare the transfer descriptor. */
219 min
= min(len
, desc_len
);
222 * De-assert CS on last segment if flag is set (i.e., no more
223 * transfers will follow)
225 if ((sg_count
+ 1 == sgs
) && (flags
& TXRX_DEASSERT_CS
))
226 ctrl0
|= BM_SSP_CTRL0_IGNORE_CRC
;
228 if (ssp
->devid
== IMX23_SSP
) {
229 ctrl0
&= ~BM_SSP_CTRL0_XFER_COUNT
;
233 dma_xfer
[sg_count
].pio
[0] = ctrl0
;
234 dma_xfer
[sg_count
].pio
[3] = min
;
237 vm_page
= vmalloc_to_page(buf
);
242 sg_buf
= page_address(vm_page
) +
243 ((size_t)buf
& ~PAGE_MASK
);
248 sg_init_one(&dma_xfer
[sg_count
].sg
, sg_buf
, min
);
249 ret
= dma_map_sg(ssp
->dev
, &dma_xfer
[sg_count
].sg
, 1,
250 (flags
& TXRX_WRITE
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
255 /* Queue the PIO register write transfer. */
256 desc
= dmaengine_prep_slave_sg(ssp
->dmach
,
257 (struct scatterlist
*)dma_xfer
[sg_count
].pio
,
258 (ssp
->devid
== IMX23_SSP
) ? 1 : 4,
260 sg_count
? DMA_PREP_INTERRUPT
: 0);
263 "Failed to get PIO reg. write descriptor.\n");
268 desc
= dmaengine_prep_slave_sg(ssp
->dmach
,
269 &dma_xfer
[sg_count
].sg
, 1,
270 (flags
& TXRX_WRITE
) ? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
271 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
275 "Failed to get DMA data write descriptor.\n");
282 * The last descriptor must have this callback,
283 * to finish the DMA transaction.
285 desc
->callback
= mxs_ssp_dma_irq_callback
;
286 desc
->callback_param
= spi
;
288 /* Start the transfer. */
289 dmaengine_submit(desc
);
290 dma_async_issue_pending(ssp
->dmach
);
292 ret
= wait_for_completion_timeout(&spi
->c
,
293 msecs_to_jiffies(SSP_TIMEOUT
));
295 dev_err(ssp
->dev
, "DMA transfer timeout\n");
297 dmaengine_terminate_all(ssp
->dmach
);
304 while (--sg_count
>= 0) {
306 dma_unmap_sg(ssp
->dev
, &dma_xfer
[sg_count
].sg
, 1,
307 (flags
& TXRX_WRITE
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
315 static int mxs_spi_txrx_pio(struct mxs_spi
*spi
,
316 unsigned char *buf
, int len
,
319 struct mxs_ssp
*ssp
= &spi
->ssp
;
321 writel(BM_SSP_CTRL0_IGNORE_CRC
,
322 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
325 if (len
== 0 && (flags
& TXRX_DEASSERT_CS
))
326 writel(BM_SSP_CTRL0_IGNORE_CRC
,
327 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
329 if (ssp
->devid
== IMX23_SSP
) {
330 writel(BM_SSP_CTRL0_XFER_COUNT
,
331 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
333 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
335 writel(1, ssp
->base
+ HW_SSP_XFER_SIZE
);
338 if (flags
& TXRX_WRITE
)
339 writel(BM_SSP_CTRL0_READ
,
340 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
342 writel(BM_SSP_CTRL0_READ
,
343 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
345 writel(BM_SSP_CTRL0_RUN
,
346 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
348 if (mxs_ssp_wait(spi
, HW_SSP_CTRL0
, BM_SSP_CTRL0_RUN
, 1))
351 if (flags
& TXRX_WRITE
)
352 writel(*buf
, ssp
->base
+ HW_SSP_DATA(ssp
));
354 writel(BM_SSP_CTRL0_DATA_XFER
,
355 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
357 if (!(flags
& TXRX_WRITE
)) {
358 if (mxs_ssp_wait(spi
, HW_SSP_STATUS(ssp
),
359 BM_SSP_STATUS_FIFO_EMPTY
, 0))
362 *buf
= (readl(ssp
->base
+ HW_SSP_DATA(ssp
)) & 0xff);
365 if (mxs_ssp_wait(spi
, HW_SSP_CTRL0
, BM_SSP_CTRL0_RUN
, 0))
377 static int mxs_spi_transfer_one(struct spi_master
*master
,
378 struct spi_message
*m
)
380 struct mxs_spi
*spi
= spi_master_get_devdata(master
);
381 struct mxs_ssp
*ssp
= &spi
->ssp
;
382 struct spi_transfer
*t
, *tmp_t
;
386 /* Program CS register bits here, it will be used for all transfers. */
387 writel(BM_SSP_CTRL0_WAIT_FOR_CMD
| BM_SSP_CTRL0_WAIT_FOR_IRQ
,
388 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
389 writel(mxs_spi_cs_to_reg(m
->spi
->chip_select
),
390 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
392 list_for_each_entry_safe(t
, tmp_t
, &m
->transfers
, transfer_list
) {
394 status
= mxs_spi_setup_transfer(m
->spi
, t
);
398 /* De-assert on last transfer, inverted by cs_change flag */
399 flag
= (&t
->transfer_list
== m
->transfers
.prev
) ^ t
->cs_change
?
400 TXRX_DEASSERT_CS
: 0;
403 * Small blocks can be transfered via PIO.
404 * Measured by empiric means:
406 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
408 * DMA only: 2.164808 seconds, 473.0KB/s
409 * Combined: 1.676276 seconds, 610.9KB/s
412 writel(BM_SSP_CTRL1_DMA_ENABLE
,
413 ssp
->base
+ HW_SSP_CTRL1(ssp
) +
414 STMP_OFFSET_REG_CLR
);
417 status
= mxs_spi_txrx_pio(spi
,
419 t
->len
, flag
| TXRX_WRITE
);
421 status
= mxs_spi_txrx_pio(spi
,
425 writel(BM_SSP_CTRL1_DMA_ENABLE
,
426 ssp
->base
+ HW_SSP_CTRL1(ssp
) +
427 STMP_OFFSET_REG_SET
);
430 status
= mxs_spi_txrx_dma(spi
,
431 (void *)t
->tx_buf
, t
->len
,
434 status
= mxs_spi_txrx_dma(spi
,
440 stmp_reset_block(ssp
->base
);
444 m
->actual_length
+= t
->len
;
448 spi_finalize_current_message(master
);
453 static const struct of_device_id mxs_spi_dt_ids
[] = {
454 { .compatible
= "fsl,imx23-spi", .data
= (void *) IMX23_SSP
, },
455 { .compatible
= "fsl,imx28-spi", .data
= (void *) IMX28_SSP
, },
458 MODULE_DEVICE_TABLE(of
, mxs_spi_dt_ids
);
460 static int mxs_spi_probe(struct platform_device
*pdev
)
462 const struct of_device_id
*of_id
=
463 of_match_device(mxs_spi_dt_ids
, &pdev
->dev
);
464 struct device_node
*np
= pdev
->dev
.of_node
;
465 struct spi_master
*master
;
468 struct resource
*iores
;
472 int ret
= 0, irq_err
;
475 * Default clock speed for the SPI core. 160MHz seems to
476 * work reasonably well with most SPI flashes, so use this
477 * as a default. Override with "clock-frequency" DT prop.
479 const int clk_freq_default
= 160000000;
481 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
482 irq_err
= platform_get_irq(pdev
, 0);
486 base
= devm_ioremap_resource(&pdev
->dev
, iores
);
488 return PTR_ERR(base
);
490 clk
= devm_clk_get(&pdev
->dev
, NULL
);
494 devid
= (enum mxs_ssp_id
) of_id
->data
;
495 ret
= of_property_read_u32(np
, "clock-frequency",
498 clk_freq
= clk_freq_default
;
500 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
504 master
->transfer_one_message
= mxs_spi_transfer_one
;
505 master
->setup
= mxs_spi_setup
;
506 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
507 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
;
508 master
->num_chipselect
= 3;
509 master
->dev
.of_node
= np
;
510 master
->flags
= SPI_MASTER_HALF_DUPLEX
;
512 spi
= spi_master_get_devdata(master
);
514 ssp
->dev
= &pdev
->dev
;
519 init_completion(&spi
->c
);
521 ret
= devm_request_irq(&pdev
->dev
, irq_err
, mxs_ssp_irq_handler
, 0,
524 goto out_master_free
;
526 ssp
->dmach
= dma_request_slave_channel(&pdev
->dev
, "rx-tx");
528 dev_err(ssp
->dev
, "Failed to request DMA\n");
530 goto out_master_free
;
533 ret
= clk_prepare_enable(ssp
->clk
);
535 goto out_dma_release
;
537 clk_set_rate(ssp
->clk
, clk_freq
);
539 ret
= stmp_reset_block(ssp
->base
);
541 goto out_disable_clk
;
543 platform_set_drvdata(pdev
, master
);
545 ret
= devm_spi_register_master(&pdev
->dev
, master
);
547 dev_err(&pdev
->dev
, "Cannot register SPI master, %d\n", ret
);
548 goto out_disable_clk
;
554 clk_disable_unprepare(ssp
->clk
);
556 dma_release_channel(ssp
->dmach
);
558 spi_master_put(master
);
562 static int mxs_spi_remove(struct platform_device
*pdev
)
564 struct spi_master
*master
;
568 master
= platform_get_drvdata(pdev
);
569 spi
= spi_master_get_devdata(master
);
572 clk_disable_unprepare(ssp
->clk
);
573 dma_release_channel(ssp
->dmach
);
578 static struct platform_driver mxs_spi_driver
= {
579 .probe
= mxs_spi_probe
,
580 .remove
= mxs_spi_remove
,
583 .owner
= THIS_MODULE
,
584 .of_match_table
= mxs_spi_dt_ids
,
588 module_platform_driver(mxs_spi_driver
);
590 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
591 MODULE_DESCRIPTION("MXS SPI master driver");
592 MODULE_LICENSE("GPL");
593 MODULE_ALIAS("platform:mxs-spi");