2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
37 #include <linux/spi/spi.h>
38 #include <linux/gpio.h>
40 #include <linux/platform_data/spi-omap2-mcspi.h>
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43 #define OMAP2_MCSPI_MAX_DIVIDER 4096
44 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
45 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
46 #define SPI_AUTOSUSPEND_TIMEOUT 2000
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSSTATUS 0x14
50 #define OMAP2_MCSPI_IRQSTATUS 0x18
51 #define OMAP2_MCSPI_IRQENABLE 0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
53 #define OMAP2_MCSPI_SYST 0x24
54 #define OMAP2_MCSPI_MODULCTRL 0x28
55 #define OMAP2_MCSPI_XFERLEVEL 0x7c
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
65 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
88 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
90 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
93 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
95 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma
{
102 struct dma_chan
*dma_tx
;
103 struct dma_chan
*dma_rx
;
105 struct completion dma_tx_completion
;
106 struct completion dma_rx_completion
;
108 char dma_rx_ch_name
[14];
109 char dma_tx_ch_name
[14];
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
115 #define DMA_MIN_BYTES 160
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
122 struct omap2_mcspi_regs
{
129 struct spi_master
*master
;
130 /* Virtual base address of the controller */
133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma
*dma_channels
;
136 struct omap2_mcspi_regs ctx
;
138 unsigned int pin_dir
:1;
141 struct omap2_mcspi_cs
{
146 struct list_head node
;
147 /* Context save and restore shadow register */
148 u32 chconf0
, chctrl0
;
151 static inline void mcspi_write_reg(struct spi_master
*master
,
154 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
156 writel_relaxed(val
, mcspi
->base
+ idx
);
159 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
161 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
163 return readl_relaxed(mcspi
->base
+ idx
);
166 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
169 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
171 writel_relaxed(val
, cs
->base
+ idx
);
174 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
176 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
178 return readl_relaxed(cs
->base
+ idx
);
181 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
183 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
188 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
190 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
193 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
194 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
197 static inline int mcspi_bytes_per_word(int word_len
)
201 else if (word_len
<= 16)
203 else /* word_len <= 32 */
207 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
208 int is_read
, int enable
)
212 l
= mcspi_cached_chconf0(spi
);
214 if (is_read
) /* 1 is read, 0 write */
215 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
217 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
224 mcspi_write_chconf0(spi
, l
);
227 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
229 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
234 l
|= OMAP2_MCSPI_CHCTRL_EN
;
236 l
&= ~OMAP2_MCSPI_CHCTRL_EN
;
238 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
243 static void omap2_mcspi_set_cs(struct spi_device
*spi
, bool enable
)
245 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
252 if (spi
->mode
& SPI_CS_HIGH
)
255 if (spi
->controller_state
) {
256 int err
= pm_runtime_get_sync(mcspi
->dev
);
258 dev_err(mcspi
->dev
, "failed to get sync: %d\n", err
);
262 l
= mcspi_cached_chconf0(spi
);
265 l
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
267 l
|= OMAP2_MCSPI_CHCONF_FORCE
;
269 mcspi_write_chconf0(spi
, l
);
271 pm_runtime_mark_last_busy(mcspi
->dev
);
272 pm_runtime_put_autosuspend(mcspi
->dev
);
276 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
278 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
279 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
283 * Setup when switching from (reset default) slave mode
284 * to single-channel master mode
286 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
287 l
&= ~(OMAP2_MCSPI_MODULCTRL_STEST
| OMAP2_MCSPI_MODULCTRL_MS
);
288 l
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
289 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
294 static void omap2_mcspi_set_fifo(const struct spi_device
*spi
,
295 struct spi_transfer
*t
, int enable
)
297 struct spi_master
*master
= spi
->master
;
298 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
299 struct omap2_mcspi
*mcspi
;
301 int max_fifo_depth
, fifo_depth
, bytes_per_word
;
302 u32 chconf
, xferlevel
;
304 mcspi
= spi_master_get_devdata(master
);
306 chconf
= mcspi_cached_chconf0(spi
);
308 bytes_per_word
= mcspi_bytes_per_word(cs
->word_len
);
309 if (t
->len
% bytes_per_word
!= 0)
312 if (t
->rx_buf
!= NULL
&& t
->tx_buf
!= NULL
)
313 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
/ 2;
315 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
;
317 fifo_depth
= gcd(t
->len
, max_fifo_depth
);
318 if (fifo_depth
< 2 || fifo_depth
% bytes_per_word
!= 0)
321 wcnt
= t
->len
/ bytes_per_word
;
322 if (wcnt
> OMAP2_MCSPI_MAX_FIFOWCNT
)
325 xferlevel
= wcnt
<< 16;
326 if (t
->rx_buf
!= NULL
) {
327 chconf
|= OMAP2_MCSPI_CHCONF_FFER
;
328 xferlevel
|= (fifo_depth
- 1) << 8;
330 if (t
->tx_buf
!= NULL
) {
331 chconf
|= OMAP2_MCSPI_CHCONF_FFET
;
332 xferlevel
|= fifo_depth
- 1;
335 mcspi_write_reg(master
, OMAP2_MCSPI_XFERLEVEL
, xferlevel
);
336 mcspi_write_chconf0(spi
, chconf
);
337 mcspi
->fifo_depth
= fifo_depth
;
343 if (t
->rx_buf
!= NULL
)
344 chconf
&= ~OMAP2_MCSPI_CHCONF_FFER
;
346 if (t
->tx_buf
!= NULL
)
347 chconf
&= ~OMAP2_MCSPI_CHCONF_FFET
;
349 mcspi_write_chconf0(spi
, chconf
);
350 mcspi
->fifo_depth
= 0;
353 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
355 struct spi_master
*spi_cntrl
= mcspi
->master
;
356 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
357 struct omap2_mcspi_cs
*cs
;
359 /* McSPI: context restore */
360 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
, ctx
->modulctrl
);
361 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
, ctx
->wakeupenable
);
363 list_for_each_entry(cs
, &ctx
->cs
, node
)
364 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
367 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
369 unsigned long timeout
;
371 timeout
= jiffies
+ msecs_to_jiffies(1000);
372 while (!(readl_relaxed(reg
) & bit
)) {
373 if (time_after(jiffies
, timeout
)) {
374 if (!(readl_relaxed(reg
) & bit
))
384 static void omap2_mcspi_rx_callback(void *data
)
386 struct spi_device
*spi
= data
;
387 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
388 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
390 /* We must disable the DMA RX request */
391 omap2_mcspi_set_dma_req(spi
, 1, 0);
393 complete(&mcspi_dma
->dma_rx_completion
);
396 static void omap2_mcspi_tx_callback(void *data
)
398 struct spi_device
*spi
= data
;
399 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
400 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
402 /* We must disable the DMA TX request */
403 omap2_mcspi_set_dma_req(spi
, 0, 0);
405 complete(&mcspi_dma
->dma_tx_completion
);
408 static void omap2_mcspi_tx_dma(struct spi_device
*spi
,
409 struct spi_transfer
*xfer
,
410 struct dma_slave_config cfg
)
412 struct omap2_mcspi
*mcspi
;
413 struct omap2_mcspi_dma
*mcspi_dma
;
416 mcspi
= spi_master_get_devdata(spi
->master
);
417 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
420 if (mcspi_dma
->dma_tx
) {
421 struct dma_async_tx_descriptor
*tx
;
422 struct scatterlist sg
;
424 dmaengine_slave_config(mcspi_dma
->dma_tx
, &cfg
);
426 sg_init_table(&sg
, 1);
427 sg_dma_address(&sg
) = xfer
->tx_dma
;
428 sg_dma_len(&sg
) = xfer
->len
;
430 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_tx
, &sg
, 1,
431 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
433 tx
->callback
= omap2_mcspi_tx_callback
;
434 tx
->callback_param
= spi
;
435 dmaengine_submit(tx
);
437 /* FIXME: fall back to PIO? */
440 dma_async_issue_pending(mcspi_dma
->dma_tx
);
441 omap2_mcspi_set_dma_req(spi
, 0, 1);
446 omap2_mcspi_rx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
,
447 struct dma_slave_config cfg
,
450 struct omap2_mcspi
*mcspi
;
451 struct omap2_mcspi_dma
*mcspi_dma
;
452 unsigned int count
, dma_count
;
455 int word_len
, element_count
;
456 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
457 mcspi
= spi_master_get_devdata(spi
->master
);
458 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
460 dma_count
= xfer
->len
;
462 if (mcspi
->fifo_depth
== 0)
465 word_len
= cs
->word_len
;
466 l
= mcspi_cached_chconf0(spi
);
469 element_count
= count
;
470 else if (word_len
<= 16)
471 element_count
= count
>> 1;
472 else /* word_len <= 32 */
473 element_count
= count
>> 2;
475 if (mcspi_dma
->dma_rx
) {
476 struct dma_async_tx_descriptor
*tx
;
477 struct scatterlist sg
;
479 dmaengine_slave_config(mcspi_dma
->dma_rx
, &cfg
);
481 if ((l
& OMAP2_MCSPI_CHCONF_TURBO
) && mcspi
->fifo_depth
== 0)
484 sg_init_table(&sg
, 1);
485 sg_dma_address(&sg
) = xfer
->rx_dma
;
486 sg_dma_len(&sg
) = dma_count
;
488 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_rx
, &sg
, 1,
489 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
|
492 tx
->callback
= omap2_mcspi_rx_callback
;
493 tx
->callback_param
= spi
;
494 dmaengine_submit(tx
);
496 /* FIXME: fall back to PIO? */
500 dma_async_issue_pending(mcspi_dma
->dma_rx
);
501 omap2_mcspi_set_dma_req(spi
, 1, 1);
503 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
504 dma_unmap_single(mcspi
->dev
, xfer
->rx_dma
, count
,
507 if (mcspi
->fifo_depth
> 0)
510 omap2_mcspi_set_enable(spi
, 0);
512 elements
= element_count
- 1;
514 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
517 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
518 & OMAP2_MCSPI_CHSTAT_RXS
)) {
521 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
523 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
524 else if (word_len
<= 16)
525 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
526 else /* word_len <= 32 */
527 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
529 int bytes_per_word
= mcspi_bytes_per_word(word_len
);
530 dev_err(&spi
->dev
, "DMA RX penultimate word empty\n");
531 count
-= (bytes_per_word
<< 1);
532 omap2_mcspi_set_enable(spi
, 1);
536 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
537 & OMAP2_MCSPI_CHSTAT_RXS
)) {
540 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
542 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
543 else if (word_len
<= 16)
544 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
545 else /* word_len <= 32 */
546 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
548 dev_err(&spi
->dev
, "DMA RX last word empty\n");
549 count
-= mcspi_bytes_per_word(word_len
);
551 omap2_mcspi_set_enable(spi
, 1);
556 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
558 struct omap2_mcspi
*mcspi
;
559 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
560 struct omap2_mcspi_dma
*mcspi_dma
;
565 struct dma_slave_config cfg
;
566 enum dma_slave_buswidth width
;
569 void __iomem
*chstat_reg
;
570 void __iomem
*irqstat_reg
;
573 mcspi
= spi_master_get_devdata(spi
->master
);
574 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
575 l
= mcspi_cached_chconf0(spi
);
578 if (cs
->word_len
<= 8) {
579 width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
581 } else if (cs
->word_len
<= 16) {
582 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
585 width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
592 if (mcspi
->fifo_depth
> 0) {
593 if (count
> mcspi
->fifo_depth
)
594 burst
= mcspi
->fifo_depth
/ es
;
599 memset(&cfg
, 0, sizeof(cfg
));
600 cfg
.src_addr
= cs
->phys
+ OMAP2_MCSPI_RX0
;
601 cfg
.dst_addr
= cs
->phys
+ OMAP2_MCSPI_TX0
;
602 cfg
.src_addr_width
= width
;
603 cfg
.dst_addr_width
= width
;
604 cfg
.src_maxburst
= burst
;
605 cfg
.dst_maxburst
= burst
;
611 omap2_mcspi_tx_dma(spi
, xfer
, cfg
);
614 count
= omap2_mcspi_rx_dma(spi
, xfer
, cfg
, es
);
617 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
618 dma_unmap_single(mcspi
->dev
, xfer
->tx_dma
, xfer
->len
,
621 if (mcspi
->fifo_depth
> 0) {
622 irqstat_reg
= mcspi
->base
+ OMAP2_MCSPI_IRQSTATUS
;
624 if (mcspi_wait_for_reg_bit(irqstat_reg
,
625 OMAP2_MCSPI_IRQSTATUS_EOW
) < 0)
626 dev_err(&spi
->dev
, "EOW timed out\n");
628 mcspi_write_reg(mcspi
->master
, OMAP2_MCSPI_IRQSTATUS
,
629 OMAP2_MCSPI_IRQSTATUS_EOW
);
632 /* for TX_ONLY mode, be sure all words have shifted out */
634 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
635 if (mcspi
->fifo_depth
> 0) {
636 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
637 OMAP2_MCSPI_CHSTAT_TXFFE
);
639 dev_err(&spi
->dev
, "TXFFE timed out\n");
641 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
642 OMAP2_MCSPI_CHSTAT_TXS
);
644 dev_err(&spi
->dev
, "TXS timed out\n");
647 (mcspi_wait_for_reg_bit(chstat_reg
,
648 OMAP2_MCSPI_CHSTAT_EOT
) < 0))
649 dev_err(&spi
->dev
, "EOT timed out\n");
656 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
658 struct omap2_mcspi
*mcspi
;
659 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
660 unsigned int count
, c
;
662 void __iomem
*base
= cs
->base
;
663 void __iomem
*tx_reg
;
664 void __iomem
*rx_reg
;
665 void __iomem
*chstat_reg
;
668 mcspi
= spi_master_get_devdata(spi
->master
);
671 word_len
= cs
->word_len
;
673 l
= mcspi_cached_chconf0(spi
);
675 /* We store the pre-calculated register addresses on stack to speed
676 * up the transfer loop. */
677 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
678 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
679 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
681 if (c
< (word_len
>>3))
694 if (mcspi_wait_for_reg_bit(chstat_reg
,
695 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
696 dev_err(&spi
->dev
, "TXS timed out\n");
699 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
701 writel_relaxed(*tx
++, tx_reg
);
704 if (mcspi_wait_for_reg_bit(chstat_reg
,
705 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
706 dev_err(&spi
->dev
, "RXS timed out\n");
710 if (c
== 1 && tx
== NULL
&&
711 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
712 omap2_mcspi_set_enable(spi
, 0);
713 *rx
++ = readl_relaxed(rx_reg
);
714 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
715 word_len
, *(rx
- 1));
716 if (mcspi_wait_for_reg_bit(chstat_reg
,
717 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
723 } else if (c
== 0 && tx
== NULL
) {
724 omap2_mcspi_set_enable(spi
, 0);
727 *rx
++ = readl_relaxed(rx_reg
);
728 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
729 word_len
, *(rx
- 1));
732 } else if (word_len
<= 16) {
741 if (mcspi_wait_for_reg_bit(chstat_reg
,
742 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
743 dev_err(&spi
->dev
, "TXS timed out\n");
746 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
748 writel_relaxed(*tx
++, tx_reg
);
751 if (mcspi_wait_for_reg_bit(chstat_reg
,
752 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
753 dev_err(&spi
->dev
, "RXS timed out\n");
757 if (c
== 2 && tx
== NULL
&&
758 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
759 omap2_mcspi_set_enable(spi
, 0);
760 *rx
++ = readl_relaxed(rx_reg
);
761 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
762 word_len
, *(rx
- 1));
763 if (mcspi_wait_for_reg_bit(chstat_reg
,
764 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
770 } else if (c
== 0 && tx
== NULL
) {
771 omap2_mcspi_set_enable(spi
, 0);
774 *rx
++ = readl_relaxed(rx_reg
);
775 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
776 word_len
, *(rx
- 1));
779 } else if (word_len
<= 32) {
788 if (mcspi_wait_for_reg_bit(chstat_reg
,
789 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
790 dev_err(&spi
->dev
, "TXS timed out\n");
793 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
795 writel_relaxed(*tx
++, tx_reg
);
798 if (mcspi_wait_for_reg_bit(chstat_reg
,
799 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
800 dev_err(&spi
->dev
, "RXS timed out\n");
804 if (c
== 4 && tx
== NULL
&&
805 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
806 omap2_mcspi_set_enable(spi
, 0);
807 *rx
++ = readl_relaxed(rx_reg
);
808 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
809 word_len
, *(rx
- 1));
810 if (mcspi_wait_for_reg_bit(chstat_reg
,
811 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
817 } else if (c
== 0 && tx
== NULL
) {
818 omap2_mcspi_set_enable(spi
, 0);
821 *rx
++ = readl_relaxed(rx_reg
);
822 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
823 word_len
, *(rx
- 1));
828 /* for TX_ONLY mode, be sure all words have shifted out */
829 if (xfer
->rx_buf
== NULL
) {
830 if (mcspi_wait_for_reg_bit(chstat_reg
,
831 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
832 dev_err(&spi
->dev
, "TXS timed out\n");
833 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
834 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
835 dev_err(&spi
->dev
, "EOT timed out\n");
837 /* disable chan to purge rx datas received in TX_ONLY transfer,
838 * otherwise these rx datas will affect the direct following
841 omap2_mcspi_set_enable(spi
, 0);
844 omap2_mcspi_set_enable(spi
, 1);
848 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
852 for (div
= 0; div
< 15; div
++)
853 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
859 /* called only when no transfer is active to this device */
860 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
861 struct spi_transfer
*t
)
863 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
864 struct omap2_mcspi
*mcspi
;
865 struct spi_master
*spi_cntrl
;
866 u32 l
= 0, clkd
= 0, div
, extclk
= 0, clkg
= 0;
867 u8 word_len
= spi
->bits_per_word
;
868 u32 speed_hz
= spi
->max_speed_hz
;
870 mcspi
= spi_master_get_devdata(spi
->master
);
871 spi_cntrl
= mcspi
->master
;
873 if (t
!= NULL
&& t
->bits_per_word
)
874 word_len
= t
->bits_per_word
;
876 cs
->word_len
= word_len
;
878 if (t
&& t
->speed_hz
)
879 speed_hz
= t
->speed_hz
;
881 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
882 if (speed_hz
< (OMAP2_MCSPI_MAX_FREQ
/ OMAP2_MCSPI_MAX_DIVIDER
)) {
883 clkd
= omap2_mcspi_calc_divisor(speed_hz
);
884 speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> clkd
;
887 div
= (OMAP2_MCSPI_MAX_FREQ
+ speed_hz
- 1) / speed_hz
;
888 speed_hz
= OMAP2_MCSPI_MAX_FREQ
/ div
;
889 clkd
= (div
- 1) & 0xf;
890 extclk
= (div
- 1) >> 4;
891 clkg
= OMAP2_MCSPI_CHCONF_CLKG
;
894 l
= mcspi_cached_chconf0(spi
);
896 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
897 * REVISIT: this controller could support SPI_3WIRE mode.
899 if (mcspi
->pin_dir
== MCSPI_PINDIR_D0_IN_D1_OUT
) {
900 l
&= ~OMAP2_MCSPI_CHCONF_IS
;
901 l
&= ~OMAP2_MCSPI_CHCONF_DPE1
;
902 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
904 l
|= OMAP2_MCSPI_CHCONF_IS
;
905 l
|= OMAP2_MCSPI_CHCONF_DPE1
;
906 l
&= ~OMAP2_MCSPI_CHCONF_DPE0
;
910 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
911 l
|= (word_len
- 1) << 7;
913 /* set chipselect polarity; manage with FORCE */
914 if (!(spi
->mode
& SPI_CS_HIGH
))
915 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
917 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
919 /* set clock divisor */
920 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
923 /* set clock granularity */
924 l
&= ~OMAP2_MCSPI_CHCONF_CLKG
;
927 cs
->chctrl0
&= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK
;
928 cs
->chctrl0
|= extclk
<< 8;
929 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
932 /* set SPI mode 0..3 */
933 if (spi
->mode
& SPI_CPOL
)
934 l
|= OMAP2_MCSPI_CHCONF_POL
;
936 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
937 if (spi
->mode
& SPI_CPHA
)
938 l
|= OMAP2_MCSPI_CHCONF_PHA
;
940 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
942 mcspi_write_chconf0(spi
, l
);
944 cs
->mode
= spi
->mode
;
946 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
948 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
949 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
955 * Note that we currently allow DMA only if we get a channel
956 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
958 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
960 struct spi_master
*master
= spi
->master
;
961 struct omap2_mcspi
*mcspi
;
962 struct omap2_mcspi_dma
*mcspi_dma
;
965 mcspi
= spi_master_get_devdata(master
);
966 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
968 init_completion(&mcspi_dma
->dma_rx_completion
);
969 init_completion(&mcspi_dma
->dma_tx_completion
);
971 mcspi_dma
->dma_rx
= dma_request_chan(&master
->dev
,
972 mcspi_dma
->dma_rx_ch_name
);
973 if (IS_ERR(mcspi_dma
->dma_rx
)) {
974 ret
= PTR_ERR(mcspi_dma
->dma_rx
);
975 mcspi_dma
->dma_rx
= NULL
;
979 mcspi_dma
->dma_tx
= dma_request_chan(&master
->dev
,
980 mcspi_dma
->dma_tx_ch_name
);
981 if (IS_ERR(mcspi_dma
->dma_tx
)) {
982 ret
= PTR_ERR(mcspi_dma
->dma_tx
);
983 mcspi_dma
->dma_tx
= NULL
;
984 dma_release_channel(mcspi_dma
->dma_rx
);
985 mcspi_dma
->dma_rx
= NULL
;
992 static int omap2_mcspi_setup(struct spi_device
*spi
)
995 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
996 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
997 struct omap2_mcspi_dma
*mcspi_dma
;
998 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
1000 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
1003 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
1006 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
1007 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
1011 spi
->controller_state
= cs
;
1012 /* Link this to context save list */
1013 list_add_tail(&cs
->node
, &ctx
->cs
);
1015 if (gpio_is_valid(spi
->cs_gpio
)) {
1016 ret
= gpio_request(spi
->cs_gpio
, dev_name(&spi
->dev
));
1018 dev_err(&spi
->dev
, "failed to request gpio\n");
1021 gpio_direction_output(spi
->cs_gpio
,
1022 !(spi
->mode
& SPI_CS_HIGH
));
1026 if (!mcspi_dma
->dma_rx
|| !mcspi_dma
->dma_tx
) {
1027 ret
= omap2_mcspi_request_dma(spi
);
1029 dev_warn(&spi
->dev
, "not using DMA for McSPI (%d)\n",
1033 ret
= pm_runtime_get_sync(mcspi
->dev
);
1037 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
1038 pm_runtime_mark_last_busy(mcspi
->dev
);
1039 pm_runtime_put_autosuspend(mcspi
->dev
);
1044 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
1046 struct omap2_mcspi
*mcspi
;
1047 struct omap2_mcspi_dma
*mcspi_dma
;
1048 struct omap2_mcspi_cs
*cs
;
1050 mcspi
= spi_master_get_devdata(spi
->master
);
1052 if (spi
->controller_state
) {
1053 /* Unlink controller state from context save list */
1054 cs
= spi
->controller_state
;
1055 list_del(&cs
->node
);
1060 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
1061 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
1063 if (mcspi_dma
->dma_rx
) {
1064 dma_release_channel(mcspi_dma
->dma_rx
);
1065 mcspi_dma
->dma_rx
= NULL
;
1067 if (mcspi_dma
->dma_tx
) {
1068 dma_release_channel(mcspi_dma
->dma_tx
);
1069 mcspi_dma
->dma_tx
= NULL
;
1073 if (gpio_is_valid(spi
->cs_gpio
))
1074 gpio_free(spi
->cs_gpio
);
1077 static int omap2_mcspi_work_one(struct omap2_mcspi
*mcspi
,
1078 struct spi_device
*spi
, struct spi_transfer
*t
)
1081 /* We only enable one channel at a time -- the one whose message is
1082 * -- although this controller would gladly
1083 * arbitrate among multiple channels. This corresponds to "single
1084 * channel" master mode. As a side effect, we need to manage the
1085 * chipselect with the FORCE bit ... CS != channel enable.
1088 struct spi_master
*master
;
1089 struct omap2_mcspi_dma
*mcspi_dma
;
1090 struct omap2_mcspi_cs
*cs
;
1091 struct omap2_mcspi_device_config
*cd
;
1092 int par_override
= 0;
1096 master
= spi
->master
;
1097 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1098 cs
= spi
->controller_state
;
1099 cd
= spi
->controller_data
;
1102 * The slave driver could have changed spi->mode in which case
1103 * it will be different from cs->mode (the current hardware setup).
1104 * If so, set par_override (even though its not a parity issue) so
1105 * omap2_mcspi_setup_transfer will be called to configure the hardware
1106 * with the correct mode on the first iteration of the loop below.
1108 if (spi
->mode
!= cs
->mode
)
1111 omap2_mcspi_set_enable(spi
, 0);
1113 if (gpio_is_valid(spi
->cs_gpio
))
1114 omap2_mcspi_set_cs(spi
, spi
->mode
& SPI_CS_HIGH
);
1117 (t
->speed_hz
!= spi
->max_speed_hz
) ||
1118 (t
->bits_per_word
!= spi
->bits_per_word
)) {
1120 status
= omap2_mcspi_setup_transfer(spi
, t
);
1123 if (t
->speed_hz
== spi
->max_speed_hz
&&
1124 t
->bits_per_word
== spi
->bits_per_word
)
1127 if (cd
&& cd
->cs_per_word
) {
1128 chconf
= mcspi
->ctx
.modulctrl
;
1129 chconf
&= ~OMAP2_MCSPI_MODULCTRL_SINGLE
;
1130 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1131 mcspi
->ctx
.modulctrl
=
1132 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1135 chconf
= mcspi_cached_chconf0(spi
);
1136 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
1137 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
1139 if (t
->tx_buf
== NULL
)
1140 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
1141 else if (t
->rx_buf
== NULL
)
1142 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
1144 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
1145 /* Turbo mode is for more than one word */
1146 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
1147 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
1150 mcspi_write_chconf0(spi
, chconf
);
1155 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1156 (t
->len
>= DMA_MIN_BYTES
))
1157 omap2_mcspi_set_fifo(spi
, t
, 1);
1159 omap2_mcspi_set_enable(spi
, 1);
1161 /* RX_ONLY mode needs dummy data in TX reg */
1162 if (t
->tx_buf
== NULL
)
1163 writel_relaxed(0, cs
->base
1166 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1167 (t
->len
>= DMA_MIN_BYTES
))
1168 count
= omap2_mcspi_txrx_dma(spi
, t
);
1170 count
= omap2_mcspi_txrx_pio(spi
, t
);
1172 if (count
!= t
->len
) {
1178 omap2_mcspi_set_enable(spi
, 0);
1180 if (mcspi
->fifo_depth
> 0)
1181 omap2_mcspi_set_fifo(spi
, t
, 0);
1184 /* Restore defaults if they were overriden */
1187 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
1190 if (cd
&& cd
->cs_per_word
) {
1191 chconf
= mcspi
->ctx
.modulctrl
;
1192 chconf
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
1193 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1194 mcspi
->ctx
.modulctrl
=
1195 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1198 omap2_mcspi_set_enable(spi
, 0);
1200 if (gpio_is_valid(spi
->cs_gpio
))
1201 omap2_mcspi_set_cs(spi
, !(spi
->mode
& SPI_CS_HIGH
));
1203 if (mcspi
->fifo_depth
> 0 && t
)
1204 omap2_mcspi_set_fifo(spi
, t
, 0);
1209 static int omap2_mcspi_prepare_message(struct spi_master
*master
,
1210 struct spi_message
*msg
)
1212 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1213 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1214 struct omap2_mcspi_cs
*cs
;
1216 /* Only a single channel can have the FORCE bit enabled
1217 * in its chconf0 register.
1218 * Scan all channels and disable them except the current one.
1219 * A FORCE can remain from a last transfer having cs_change enabled
1221 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1222 if (msg
->spi
->controller_state
== cs
)
1225 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
)) {
1226 cs
->chconf0
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
1227 writel_relaxed(cs
->chconf0
,
1228 cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1229 readl_relaxed(cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1236 static int omap2_mcspi_transfer_one(struct spi_master
*master
,
1237 struct spi_device
*spi
, struct spi_transfer
*t
)
1239 struct omap2_mcspi
*mcspi
;
1240 struct omap2_mcspi_dma
*mcspi_dma
;
1241 const void *tx_buf
= t
->tx_buf
;
1242 void *rx_buf
= t
->rx_buf
;
1243 unsigned len
= t
->len
;
1245 mcspi
= spi_master_get_devdata(master
);
1246 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1248 if ((len
&& !(rx_buf
|| tx_buf
))) {
1249 dev_dbg(mcspi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
1258 if (len
< DMA_MIN_BYTES
)
1261 if (mcspi_dma
->dma_tx
&& tx_buf
!= NULL
) {
1262 t
->tx_dma
= dma_map_single(mcspi
->dev
, (void *) tx_buf
,
1263 len
, DMA_TO_DEVICE
);
1264 if (dma_mapping_error(mcspi
->dev
, t
->tx_dma
)) {
1265 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1270 if (mcspi_dma
->dma_rx
&& rx_buf
!= NULL
) {
1271 t
->rx_dma
= dma_map_single(mcspi
->dev
, rx_buf
, t
->len
,
1273 if (dma_mapping_error(mcspi
->dev
, t
->rx_dma
)) {
1274 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1277 dma_unmap_single(mcspi
->dev
, t
->tx_dma
,
1278 len
, DMA_TO_DEVICE
);
1284 return omap2_mcspi_work_one(mcspi
, spi
, t
);
1287 static int omap2_mcspi_master_setup(struct omap2_mcspi
*mcspi
)
1289 struct spi_master
*master
= mcspi
->master
;
1290 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1293 ret
= pm_runtime_get_sync(mcspi
->dev
);
1297 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
,
1298 OMAP2_MCSPI_WAKEUPENABLE_WKEN
);
1299 ctx
->wakeupenable
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1301 omap2_mcspi_set_master_mode(master
);
1302 pm_runtime_mark_last_busy(mcspi
->dev
);
1303 pm_runtime_put_autosuspend(mcspi
->dev
);
1307 static int omap_mcspi_runtime_resume(struct device
*dev
)
1309 struct omap2_mcspi
*mcspi
;
1310 struct spi_master
*master
;
1312 master
= dev_get_drvdata(dev
);
1313 mcspi
= spi_master_get_devdata(master
);
1314 omap2_mcspi_restore_ctx(mcspi
);
1319 static struct omap2_mcspi_platform_config omap2_pdata
= {
1323 static struct omap2_mcspi_platform_config omap4_pdata
= {
1324 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
1327 static const struct of_device_id omap_mcspi_of_match
[] = {
1329 .compatible
= "ti,omap2-mcspi",
1330 .data
= &omap2_pdata
,
1333 .compatible
= "ti,omap4-mcspi",
1334 .data
= &omap4_pdata
,
1338 MODULE_DEVICE_TABLE(of
, omap_mcspi_of_match
);
1340 static int omap2_mcspi_probe(struct platform_device
*pdev
)
1342 struct spi_master
*master
;
1343 const struct omap2_mcspi_platform_config
*pdata
;
1344 struct omap2_mcspi
*mcspi
;
1347 u32 regs_offset
= 0;
1348 static int bus_num
= 1;
1349 struct device_node
*node
= pdev
->dev
.of_node
;
1350 const struct of_device_id
*match
;
1352 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1353 if (master
== NULL
) {
1354 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1358 /* the spi->mode bits understood by this driver: */
1359 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1360 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1361 master
->setup
= omap2_mcspi_setup
;
1362 master
->auto_runtime_pm
= true;
1363 master
->prepare_message
= omap2_mcspi_prepare_message
;
1364 master
->transfer_one
= omap2_mcspi_transfer_one
;
1365 master
->set_cs
= omap2_mcspi_set_cs
;
1366 master
->cleanup
= omap2_mcspi_cleanup
;
1367 master
->dev
.of_node
= node
;
1368 master
->max_speed_hz
= OMAP2_MCSPI_MAX_FREQ
;
1369 master
->min_speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> 15;
1371 platform_set_drvdata(pdev
, master
);
1373 mcspi
= spi_master_get_devdata(master
);
1374 mcspi
->master
= master
;
1376 match
= of_match_device(omap_mcspi_of_match
, &pdev
->dev
);
1378 u32 num_cs
= 1; /* default number of chipselect */
1379 pdata
= match
->data
;
1381 of_property_read_u32(node
, "ti,spi-num-cs", &num_cs
);
1382 master
->num_chipselect
= num_cs
;
1383 master
->bus_num
= bus_num
++;
1384 if (of_get_property(node
, "ti,pindir-d0-out-d1-in", NULL
))
1385 mcspi
->pin_dir
= MCSPI_PINDIR_D0_OUT_D1_IN
;
1387 pdata
= dev_get_platdata(&pdev
->dev
);
1388 master
->num_chipselect
= pdata
->num_cs
;
1390 master
->bus_num
= pdev
->id
;
1391 mcspi
->pin_dir
= pdata
->pin_dir
;
1393 regs_offset
= pdata
->regs_offset
;
1395 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1401 r
->start
+= regs_offset
;
1402 r
->end
+= regs_offset
;
1403 mcspi
->phys
= r
->start
;
1405 mcspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1406 if (IS_ERR(mcspi
->base
)) {
1407 status
= PTR_ERR(mcspi
->base
);
1411 mcspi
->dev
= &pdev
->dev
;
1413 INIT_LIST_HEAD(&mcspi
->ctx
.cs
);
1415 mcspi
->dma_channels
= devm_kcalloc(&pdev
->dev
, master
->num_chipselect
,
1416 sizeof(struct omap2_mcspi_dma
),
1418 if (mcspi
->dma_channels
== NULL
) {
1423 for (i
= 0; i
< master
->num_chipselect
; i
++) {
1424 sprintf(mcspi
->dma_channels
[i
].dma_rx_ch_name
, "rx%d", i
);
1425 sprintf(mcspi
->dma_channels
[i
].dma_tx_ch_name
, "tx%d", i
);
1431 pm_runtime_use_autosuspend(&pdev
->dev
);
1432 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
1433 pm_runtime_enable(&pdev
->dev
);
1435 status
= omap2_mcspi_master_setup(mcspi
);
1439 status
= devm_spi_register_master(&pdev
->dev
, master
);
1446 pm_runtime_dont_use_autosuspend(&pdev
->dev
);
1447 pm_runtime_put_sync(&pdev
->dev
);
1448 pm_runtime_disable(&pdev
->dev
);
1450 spi_master_put(master
);
1454 static int omap2_mcspi_remove(struct platform_device
*pdev
)
1456 struct spi_master
*master
= platform_get_drvdata(pdev
);
1457 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1459 pm_runtime_dont_use_autosuspend(mcspi
->dev
);
1460 pm_runtime_put_sync(mcspi
->dev
);
1461 pm_runtime_disable(&pdev
->dev
);
1466 /* work with hotplug and coldplug */
1467 MODULE_ALIAS("platform:omap2_mcspi");
1469 #ifdef CONFIG_SUSPEND
1471 * When SPI wake up from off-mode, CS is in activate state. If it was in
1472 * unactive state when driver was suspend, then force it to unactive state at
1475 static int omap2_mcspi_resume(struct device
*dev
)
1477 struct spi_master
*master
= dev_get_drvdata(dev
);
1478 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1479 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1480 struct omap2_mcspi_cs
*cs
;
1482 pm_runtime_get_sync(mcspi
->dev
);
1483 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1484 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1486 * We need to toggle CS state for OMAP take this
1487 * change in account.
1489 cs
->chconf0
|= OMAP2_MCSPI_CHCONF_FORCE
;
1490 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1491 cs
->chconf0
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
1492 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1495 pm_runtime_mark_last_busy(mcspi
->dev
);
1496 pm_runtime_put_autosuspend(mcspi
->dev
);
1498 return pinctrl_pm_select_default_state(dev
);
1501 static int omap2_mcspi_suspend(struct device
*dev
)
1503 return pinctrl_pm_select_sleep_state(dev
);
1507 #define omap2_mcspi_suspend NULL
1508 #define omap2_mcspi_resume NULL
1511 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1512 .resume
= omap2_mcspi_resume
,
1513 .suspend
= omap2_mcspi_suspend
,
1514 .runtime_resume
= omap_mcspi_runtime_resume
,
1517 static struct platform_driver omap2_mcspi_driver
= {
1519 .name
= "omap2_mcspi",
1520 .pm
= &omap2_mcspi_pm_ops
,
1521 .of_match_table
= omap_mcspi_of_match
,
1523 .probe
= omap2_mcspi_probe
,
1524 .remove
= omap2_mcspi_remove
,
1527 module_platform_driver(omap2_mcspi_driver
);
1528 MODULE_LICENSE("GPL");