2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/omap-dma.h>
32 #include <linux/platform_device.h>
33 #include <linux/err.h>
34 #include <linux/clk.h>
36 #include <linux/slab.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/of_device.h>
40 #include <linux/gcd.h>
42 #include <linux/spi/spi.h>
44 #include <linux/platform_data/spi-omap2-mcspi.h>
46 #define OMAP2_MCSPI_MAX_FREQ 48000000
47 #define OMAP2_MCSPI_MAX_DIVIDER 4096
48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50 #define SPI_AUTOSUSPEND_TIMEOUT 2000
52 #define OMAP2_MCSPI_REVISION 0x00
53 #define OMAP2_MCSPI_SYSSTATUS 0x14
54 #define OMAP2_MCSPI_IRQSTATUS 0x18
55 #define OMAP2_MCSPI_IRQENABLE 0x1c
56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
57 #define OMAP2_MCSPI_SYST 0x24
58 #define OMAP2_MCSPI_MODULCTRL 0x28
59 #define OMAP2_MCSPI_XFERLEVEL 0x7c
61 /* per-channel banks, 0x14 bytes each, first is: */
62 #define OMAP2_MCSPI_CHCONF0 0x2c
63 #define OMAP2_MCSPI_CHSTAT0 0x30
64 #define OMAP2_MCSPI_CHCTRL0 0x34
65 #define OMAP2_MCSPI_TX0 0x38
66 #define OMAP2_MCSPI_RX0 0x3c
68 /* per-register bitmasks: */
69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
76 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
87 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
94 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
95 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
96 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
97 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
99 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
102 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
104 /* We have 2 DMA channels per CS, one for RX and one for TX */
105 struct omap2_mcspi_dma
{
106 struct dma_chan
*dma_tx
;
107 struct dma_chan
*dma_rx
;
112 struct completion dma_tx_completion
;
113 struct completion dma_rx_completion
;
115 char dma_rx_ch_name
[14];
116 char dma_tx_ch_name
[14];
119 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
120 * cache operations; better heuristics consider wordsize and bitrate.
122 #define DMA_MIN_BYTES 160
126 * Used for context save and restore, structure members to be updated whenever
127 * corresponding registers are modified.
129 struct omap2_mcspi_regs
{
136 struct spi_master
*master
;
137 /* Virtual base address of the controller */
140 /* SPI1 has 4 channels, while SPI2 has 2 */
141 struct omap2_mcspi_dma
*dma_channels
;
143 struct omap2_mcspi_regs ctx
;
145 unsigned int pin_dir
:1;
148 struct omap2_mcspi_cs
{
153 struct list_head node
;
154 /* Context save and restore shadow register */
155 u32 chconf0
, chctrl0
;
158 static inline void mcspi_write_reg(struct spi_master
*master
,
161 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
163 writel_relaxed(val
, mcspi
->base
+ idx
);
166 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
168 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
170 return readl_relaxed(mcspi
->base
+ idx
);
173 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
176 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
178 writel_relaxed(val
, cs
->base
+ idx
);
181 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
183 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
185 return readl_relaxed(cs
->base
+ idx
);
188 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
190 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
195 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
197 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
200 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
201 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
204 static inline int mcspi_bytes_per_word(int word_len
)
208 else if (word_len
<= 16)
210 else /* word_len <= 32 */
214 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
215 int is_read
, int enable
)
219 l
= mcspi_cached_chconf0(spi
);
221 if (is_read
) /* 1 is read, 0 write */
222 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
224 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
231 mcspi_write_chconf0(spi
, l
);
234 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
236 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
241 l
|= OMAP2_MCSPI_CHCTRL_EN
;
243 l
&= ~OMAP2_MCSPI_CHCTRL_EN
;
245 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
246 /* Flash post-writes */
247 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
250 static void omap2_mcspi_force_cs(struct spi_device
*spi
, int cs_active
)
254 l
= mcspi_cached_chconf0(spi
);
256 l
|= OMAP2_MCSPI_CHCONF_FORCE
;
258 l
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
260 mcspi_write_chconf0(spi
, l
);
263 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
265 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
266 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
270 * Setup when switching from (reset default) slave mode
271 * to single-channel master mode
273 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
274 l
&= ~(OMAP2_MCSPI_MODULCTRL_STEST
| OMAP2_MCSPI_MODULCTRL_MS
);
275 l
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
276 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
281 static void omap2_mcspi_set_fifo(const struct spi_device
*spi
,
282 struct spi_transfer
*t
, int enable
)
284 struct spi_master
*master
= spi
->master
;
285 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
286 struct omap2_mcspi
*mcspi
;
288 int max_fifo_depth
, fifo_depth
, bytes_per_word
;
289 u32 chconf
, xferlevel
;
291 mcspi
= spi_master_get_devdata(master
);
293 chconf
= mcspi_cached_chconf0(spi
);
295 bytes_per_word
= mcspi_bytes_per_word(cs
->word_len
);
296 if (t
->len
% bytes_per_word
!= 0)
299 if (t
->rx_buf
!= NULL
&& t
->tx_buf
!= NULL
)
300 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
/ 2;
302 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
;
304 fifo_depth
= gcd(t
->len
, max_fifo_depth
);
305 if (fifo_depth
< 2 || fifo_depth
% bytes_per_word
!= 0)
308 wcnt
= t
->len
/ bytes_per_word
;
309 if (wcnt
> OMAP2_MCSPI_MAX_FIFOWCNT
)
312 xferlevel
= wcnt
<< 16;
313 if (t
->rx_buf
!= NULL
) {
314 chconf
|= OMAP2_MCSPI_CHCONF_FFER
;
315 xferlevel
|= (fifo_depth
- 1) << 8;
317 if (t
->tx_buf
!= NULL
) {
318 chconf
|= OMAP2_MCSPI_CHCONF_FFET
;
319 xferlevel
|= fifo_depth
- 1;
322 mcspi_write_reg(master
, OMAP2_MCSPI_XFERLEVEL
, xferlevel
);
323 mcspi_write_chconf0(spi
, chconf
);
324 mcspi
->fifo_depth
= fifo_depth
;
330 if (t
->rx_buf
!= NULL
)
331 chconf
&= ~OMAP2_MCSPI_CHCONF_FFER
;
333 if (t
->tx_buf
!= NULL
)
334 chconf
&= ~OMAP2_MCSPI_CHCONF_FFET
;
336 mcspi_write_chconf0(spi
, chconf
);
337 mcspi
->fifo_depth
= 0;
340 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
342 struct spi_master
*spi_cntrl
= mcspi
->master
;
343 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
344 struct omap2_mcspi_cs
*cs
;
346 /* McSPI: context restore */
347 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
, ctx
->modulctrl
);
348 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
, ctx
->wakeupenable
);
350 list_for_each_entry(cs
, &ctx
->cs
, node
)
351 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
354 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
356 unsigned long timeout
;
358 timeout
= jiffies
+ msecs_to_jiffies(1000);
359 while (!(readl_relaxed(reg
) & bit
)) {
360 if (time_after(jiffies
, timeout
)) {
361 if (!(readl_relaxed(reg
) & bit
))
371 static void omap2_mcspi_rx_callback(void *data
)
373 struct spi_device
*spi
= data
;
374 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
375 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
377 /* We must disable the DMA RX request */
378 omap2_mcspi_set_dma_req(spi
, 1, 0);
380 complete(&mcspi_dma
->dma_rx_completion
);
383 static void omap2_mcspi_tx_callback(void *data
)
385 struct spi_device
*spi
= data
;
386 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
387 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
389 /* We must disable the DMA TX request */
390 omap2_mcspi_set_dma_req(spi
, 0, 0);
392 complete(&mcspi_dma
->dma_tx_completion
);
395 static void omap2_mcspi_tx_dma(struct spi_device
*spi
,
396 struct spi_transfer
*xfer
,
397 struct dma_slave_config cfg
)
399 struct omap2_mcspi
*mcspi
;
400 struct omap2_mcspi_dma
*mcspi_dma
;
403 mcspi
= spi_master_get_devdata(spi
->master
);
404 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
407 if (mcspi_dma
->dma_tx
) {
408 struct dma_async_tx_descriptor
*tx
;
409 struct scatterlist sg
;
411 dmaengine_slave_config(mcspi_dma
->dma_tx
, &cfg
);
413 sg_init_table(&sg
, 1);
414 sg_dma_address(&sg
) = xfer
->tx_dma
;
415 sg_dma_len(&sg
) = xfer
->len
;
417 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_tx
, &sg
, 1,
418 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
420 tx
->callback
= omap2_mcspi_tx_callback
;
421 tx
->callback_param
= spi
;
422 dmaengine_submit(tx
);
424 /* FIXME: fall back to PIO? */
427 dma_async_issue_pending(mcspi_dma
->dma_tx
);
428 omap2_mcspi_set_dma_req(spi
, 0, 1);
433 omap2_mcspi_rx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
,
434 struct dma_slave_config cfg
,
437 struct omap2_mcspi
*mcspi
;
438 struct omap2_mcspi_dma
*mcspi_dma
;
439 unsigned int count
, dma_count
;
442 int word_len
, element_count
;
443 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
444 mcspi
= spi_master_get_devdata(spi
->master
);
445 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
447 dma_count
= xfer
->len
;
449 if (mcspi
->fifo_depth
== 0)
452 word_len
= cs
->word_len
;
453 l
= mcspi_cached_chconf0(spi
);
456 element_count
= count
;
457 else if (word_len
<= 16)
458 element_count
= count
>> 1;
459 else /* word_len <= 32 */
460 element_count
= count
>> 2;
462 if (mcspi_dma
->dma_rx
) {
463 struct dma_async_tx_descriptor
*tx
;
464 struct scatterlist sg
;
466 dmaengine_slave_config(mcspi_dma
->dma_rx
, &cfg
);
468 if ((l
& OMAP2_MCSPI_CHCONF_TURBO
) && mcspi
->fifo_depth
== 0)
471 sg_init_table(&sg
, 1);
472 sg_dma_address(&sg
) = xfer
->rx_dma
;
473 sg_dma_len(&sg
) = dma_count
;
475 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_rx
, &sg
, 1,
476 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
|
479 tx
->callback
= omap2_mcspi_rx_callback
;
480 tx
->callback_param
= spi
;
481 dmaengine_submit(tx
);
483 /* FIXME: fall back to PIO? */
487 dma_async_issue_pending(mcspi_dma
->dma_rx
);
488 omap2_mcspi_set_dma_req(spi
, 1, 1);
490 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
491 dma_unmap_single(mcspi
->dev
, xfer
->rx_dma
, count
,
494 if (mcspi
->fifo_depth
> 0)
497 omap2_mcspi_set_enable(spi
, 0);
499 elements
= element_count
- 1;
501 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
504 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
505 & OMAP2_MCSPI_CHSTAT_RXS
)) {
508 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
510 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
511 else if (word_len
<= 16)
512 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
513 else /* word_len <= 32 */
514 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
516 int bytes_per_word
= mcspi_bytes_per_word(word_len
);
517 dev_err(&spi
->dev
, "DMA RX penultimate word empty\n");
518 count
-= (bytes_per_word
<< 1);
519 omap2_mcspi_set_enable(spi
, 1);
523 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
524 & OMAP2_MCSPI_CHSTAT_RXS
)) {
527 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
529 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
530 else if (word_len
<= 16)
531 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
532 else /* word_len <= 32 */
533 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
535 dev_err(&spi
->dev
, "DMA RX last word empty\n");
536 count
-= mcspi_bytes_per_word(word_len
);
538 omap2_mcspi_set_enable(spi
, 1);
543 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
545 struct omap2_mcspi
*mcspi
;
546 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
547 struct omap2_mcspi_dma
*mcspi_dma
;
552 struct dma_slave_config cfg
;
553 enum dma_slave_buswidth width
;
556 void __iomem
*chstat_reg
;
557 void __iomem
*irqstat_reg
;
560 mcspi
= spi_master_get_devdata(spi
->master
);
561 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
562 l
= mcspi_cached_chconf0(spi
);
565 if (cs
->word_len
<= 8) {
566 width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
568 } else if (cs
->word_len
<= 16) {
569 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
572 width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
579 if (mcspi
->fifo_depth
> 0) {
580 if (count
> mcspi
->fifo_depth
)
581 burst
= mcspi
->fifo_depth
/ es
;
586 memset(&cfg
, 0, sizeof(cfg
));
587 cfg
.src_addr
= cs
->phys
+ OMAP2_MCSPI_RX0
;
588 cfg
.dst_addr
= cs
->phys
+ OMAP2_MCSPI_TX0
;
589 cfg
.src_addr_width
= width
;
590 cfg
.dst_addr_width
= width
;
591 cfg
.src_maxburst
= burst
;
592 cfg
.dst_maxburst
= burst
;
598 omap2_mcspi_tx_dma(spi
, xfer
, cfg
);
601 count
= omap2_mcspi_rx_dma(spi
, xfer
, cfg
, es
);
604 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
605 dma_unmap_single(mcspi
->dev
, xfer
->tx_dma
, xfer
->len
,
608 if (mcspi
->fifo_depth
> 0) {
609 irqstat_reg
= mcspi
->base
+ OMAP2_MCSPI_IRQSTATUS
;
611 if (mcspi_wait_for_reg_bit(irqstat_reg
,
612 OMAP2_MCSPI_IRQSTATUS_EOW
) < 0)
613 dev_err(&spi
->dev
, "EOW timed out\n");
615 mcspi_write_reg(mcspi
->master
, OMAP2_MCSPI_IRQSTATUS
,
616 OMAP2_MCSPI_IRQSTATUS_EOW
);
619 /* for TX_ONLY mode, be sure all words have shifted out */
621 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
622 if (mcspi
->fifo_depth
> 0) {
623 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
624 OMAP2_MCSPI_CHSTAT_TXFFE
);
626 dev_err(&spi
->dev
, "TXFFE timed out\n");
628 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
629 OMAP2_MCSPI_CHSTAT_TXS
);
631 dev_err(&spi
->dev
, "TXS timed out\n");
634 (mcspi_wait_for_reg_bit(chstat_reg
,
635 OMAP2_MCSPI_CHSTAT_EOT
) < 0))
636 dev_err(&spi
->dev
, "EOT timed out\n");
643 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
645 struct omap2_mcspi
*mcspi
;
646 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
647 unsigned int count
, c
;
649 void __iomem
*base
= cs
->base
;
650 void __iomem
*tx_reg
;
651 void __iomem
*rx_reg
;
652 void __iomem
*chstat_reg
;
655 mcspi
= spi_master_get_devdata(spi
->master
);
658 word_len
= cs
->word_len
;
660 l
= mcspi_cached_chconf0(spi
);
662 /* We store the pre-calculated register addresses on stack to speed
663 * up the transfer loop. */
664 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
665 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
666 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
668 if (c
< (word_len
>>3))
681 if (mcspi_wait_for_reg_bit(chstat_reg
,
682 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
683 dev_err(&spi
->dev
, "TXS timed out\n");
686 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
688 writel_relaxed(*tx
++, tx_reg
);
691 if (mcspi_wait_for_reg_bit(chstat_reg
,
692 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
693 dev_err(&spi
->dev
, "RXS timed out\n");
697 if (c
== 1 && tx
== NULL
&&
698 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
699 omap2_mcspi_set_enable(spi
, 0);
700 *rx
++ = readl_relaxed(rx_reg
);
701 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
702 word_len
, *(rx
- 1));
703 if (mcspi_wait_for_reg_bit(chstat_reg
,
704 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
710 } else if (c
== 0 && tx
== NULL
) {
711 omap2_mcspi_set_enable(spi
, 0);
714 *rx
++ = readl_relaxed(rx_reg
);
715 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
716 word_len
, *(rx
- 1));
719 } else if (word_len
<= 16) {
728 if (mcspi_wait_for_reg_bit(chstat_reg
,
729 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
730 dev_err(&spi
->dev
, "TXS timed out\n");
733 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
735 writel_relaxed(*tx
++, tx_reg
);
738 if (mcspi_wait_for_reg_bit(chstat_reg
,
739 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
740 dev_err(&spi
->dev
, "RXS timed out\n");
744 if (c
== 2 && tx
== NULL
&&
745 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
746 omap2_mcspi_set_enable(spi
, 0);
747 *rx
++ = readl_relaxed(rx_reg
);
748 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
749 word_len
, *(rx
- 1));
750 if (mcspi_wait_for_reg_bit(chstat_reg
,
751 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
757 } else if (c
== 0 && tx
== NULL
) {
758 omap2_mcspi_set_enable(spi
, 0);
761 *rx
++ = readl_relaxed(rx_reg
);
762 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
763 word_len
, *(rx
- 1));
766 } else if (word_len
<= 32) {
775 if (mcspi_wait_for_reg_bit(chstat_reg
,
776 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
777 dev_err(&spi
->dev
, "TXS timed out\n");
780 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
782 writel_relaxed(*tx
++, tx_reg
);
785 if (mcspi_wait_for_reg_bit(chstat_reg
,
786 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
787 dev_err(&spi
->dev
, "RXS timed out\n");
791 if (c
== 4 && tx
== NULL
&&
792 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
793 omap2_mcspi_set_enable(spi
, 0);
794 *rx
++ = readl_relaxed(rx_reg
);
795 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
796 word_len
, *(rx
- 1));
797 if (mcspi_wait_for_reg_bit(chstat_reg
,
798 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
804 } else if (c
== 0 && tx
== NULL
) {
805 omap2_mcspi_set_enable(spi
, 0);
808 *rx
++ = readl_relaxed(rx_reg
);
809 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
810 word_len
, *(rx
- 1));
815 /* for TX_ONLY mode, be sure all words have shifted out */
816 if (xfer
->rx_buf
== NULL
) {
817 if (mcspi_wait_for_reg_bit(chstat_reg
,
818 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
819 dev_err(&spi
->dev
, "TXS timed out\n");
820 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
821 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
822 dev_err(&spi
->dev
, "EOT timed out\n");
824 /* disable chan to purge rx datas received in TX_ONLY transfer,
825 * otherwise these rx datas will affect the direct following
828 omap2_mcspi_set_enable(spi
, 0);
831 omap2_mcspi_set_enable(spi
, 1);
835 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
839 for (div
= 0; div
< 15; div
++)
840 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
846 /* called only when no transfer is active to this device */
847 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
848 struct spi_transfer
*t
)
850 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
851 struct omap2_mcspi
*mcspi
;
852 struct spi_master
*spi_cntrl
;
853 u32 l
= 0, clkd
= 0, div
, extclk
= 0, clkg
= 0;
854 u8 word_len
= spi
->bits_per_word
;
855 u32 speed_hz
= spi
->max_speed_hz
;
857 mcspi
= spi_master_get_devdata(spi
->master
);
858 spi_cntrl
= mcspi
->master
;
860 if (t
!= NULL
&& t
->bits_per_word
)
861 word_len
= t
->bits_per_word
;
863 cs
->word_len
= word_len
;
865 if (t
&& t
->speed_hz
)
866 speed_hz
= t
->speed_hz
;
868 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
869 if (speed_hz
< (OMAP2_MCSPI_MAX_FREQ
/ OMAP2_MCSPI_MAX_DIVIDER
)) {
870 clkd
= omap2_mcspi_calc_divisor(speed_hz
);
871 speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> clkd
;
874 div
= (OMAP2_MCSPI_MAX_FREQ
+ speed_hz
- 1) / speed_hz
;
875 speed_hz
= OMAP2_MCSPI_MAX_FREQ
/ div
;
876 clkd
= (div
- 1) & 0xf;
877 extclk
= (div
- 1) >> 4;
878 clkg
= OMAP2_MCSPI_CHCONF_CLKG
;
881 l
= mcspi_cached_chconf0(spi
);
883 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
884 * REVISIT: this controller could support SPI_3WIRE mode.
886 if (mcspi
->pin_dir
== MCSPI_PINDIR_D0_IN_D1_OUT
) {
887 l
&= ~OMAP2_MCSPI_CHCONF_IS
;
888 l
&= ~OMAP2_MCSPI_CHCONF_DPE1
;
889 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
891 l
|= OMAP2_MCSPI_CHCONF_IS
;
892 l
|= OMAP2_MCSPI_CHCONF_DPE1
;
893 l
&= ~OMAP2_MCSPI_CHCONF_DPE0
;
897 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
898 l
|= (word_len
- 1) << 7;
900 /* set chipselect polarity; manage with FORCE */
901 if (!(spi
->mode
& SPI_CS_HIGH
))
902 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
904 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
906 /* set clock divisor */
907 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
910 /* set clock granularity */
911 l
&= ~OMAP2_MCSPI_CHCONF_CLKG
;
914 cs
->chctrl0
&= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK
;
915 cs
->chctrl0
|= extclk
<< 8;
916 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
919 /* set SPI mode 0..3 */
920 if (spi
->mode
& SPI_CPOL
)
921 l
|= OMAP2_MCSPI_CHCONF_POL
;
923 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
924 if (spi
->mode
& SPI_CPHA
)
925 l
|= OMAP2_MCSPI_CHCONF_PHA
;
927 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
929 mcspi_write_chconf0(spi
, l
);
931 cs
->mode
= spi
->mode
;
933 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
935 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
936 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
942 * Note that we currently allow DMA only if we get a channel
943 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
945 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
947 struct spi_master
*master
= spi
->master
;
948 struct omap2_mcspi
*mcspi
;
949 struct omap2_mcspi_dma
*mcspi_dma
;
953 mcspi
= spi_master_get_devdata(master
);
954 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
956 init_completion(&mcspi_dma
->dma_rx_completion
);
957 init_completion(&mcspi_dma
->dma_tx_completion
);
960 dma_cap_set(DMA_SLAVE
, mask
);
961 sig
= mcspi_dma
->dma_rx_sync_dev
;
964 dma_request_slave_channel_compat(mask
, omap_dma_filter_fn
,
966 mcspi_dma
->dma_rx_ch_name
);
967 if (!mcspi_dma
->dma_rx
)
970 sig
= mcspi_dma
->dma_tx_sync_dev
;
972 dma_request_slave_channel_compat(mask
, omap_dma_filter_fn
,
974 mcspi_dma
->dma_tx_ch_name
);
976 if (!mcspi_dma
->dma_tx
) {
977 dma_release_channel(mcspi_dma
->dma_rx
);
978 mcspi_dma
->dma_rx
= NULL
;
985 dev_warn(&spi
->dev
, "not using DMA for McSPI\n");
989 static int omap2_mcspi_setup(struct spi_device
*spi
)
992 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
993 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
994 struct omap2_mcspi_dma
*mcspi_dma
;
995 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
997 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
1000 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
1003 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
1004 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
1008 spi
->controller_state
= cs
;
1009 /* Link this to context save list */
1010 list_add_tail(&cs
->node
, &ctx
->cs
);
1013 if (!mcspi_dma
->dma_rx
|| !mcspi_dma
->dma_tx
) {
1014 ret
= omap2_mcspi_request_dma(spi
);
1015 if (ret
< 0 && ret
!= -EAGAIN
)
1019 ret
= pm_runtime_get_sync(mcspi
->dev
);
1023 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
1024 pm_runtime_mark_last_busy(mcspi
->dev
);
1025 pm_runtime_put_autosuspend(mcspi
->dev
);
1030 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
1032 struct omap2_mcspi
*mcspi
;
1033 struct omap2_mcspi_dma
*mcspi_dma
;
1034 struct omap2_mcspi_cs
*cs
;
1036 mcspi
= spi_master_get_devdata(spi
->master
);
1038 if (spi
->controller_state
) {
1039 /* Unlink controller state from context save list */
1040 cs
= spi
->controller_state
;
1041 list_del(&cs
->node
);
1046 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
1047 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
1049 if (mcspi_dma
->dma_rx
) {
1050 dma_release_channel(mcspi_dma
->dma_rx
);
1051 mcspi_dma
->dma_rx
= NULL
;
1053 if (mcspi_dma
->dma_tx
) {
1054 dma_release_channel(mcspi_dma
->dma_tx
);
1055 mcspi_dma
->dma_tx
= NULL
;
1060 static void omap2_mcspi_work(struct omap2_mcspi
*mcspi
, struct spi_message
*m
)
1063 /* We only enable one channel at a time -- the one whose message is
1064 * -- although this controller would gladly
1065 * arbitrate among multiple channels. This corresponds to "single
1066 * channel" master mode. As a side effect, we need to manage the
1067 * chipselect with the FORCE bit ... CS != channel enable.
1070 struct spi_device
*spi
;
1071 struct spi_transfer
*t
= NULL
;
1072 struct spi_master
*master
;
1073 struct omap2_mcspi_dma
*mcspi_dma
;
1075 struct omap2_mcspi_cs
*cs
;
1076 struct omap2_mcspi_device_config
*cd
;
1077 int par_override
= 0;
1082 master
= spi
->master
;
1083 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1084 cs
= spi
->controller_state
;
1085 cd
= spi
->controller_data
;
1088 * The slave driver could have changed spi->mode in which case
1089 * it will be different from cs->mode (the current hardware setup).
1090 * If so, set par_override (even though its not a parity issue) so
1091 * omap2_mcspi_setup_transfer will be called to configure the hardware
1092 * with the correct mode on the first iteration of the loop below.
1094 if (spi
->mode
!= cs
->mode
)
1097 omap2_mcspi_set_enable(spi
, 0);
1098 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1099 if (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
&& t
->len
) {
1104 (t
->speed_hz
!= spi
->max_speed_hz
) ||
1105 (t
->bits_per_word
!= spi
->bits_per_word
)) {
1107 status
= omap2_mcspi_setup_transfer(spi
, t
);
1110 if (t
->speed_hz
== spi
->max_speed_hz
&&
1111 t
->bits_per_word
== spi
->bits_per_word
)
1114 if (cd
&& cd
->cs_per_word
) {
1115 chconf
= mcspi
->ctx
.modulctrl
;
1116 chconf
&= ~OMAP2_MCSPI_MODULCTRL_SINGLE
;
1117 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1118 mcspi
->ctx
.modulctrl
=
1119 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1124 omap2_mcspi_force_cs(spi
, 1);
1128 chconf
= mcspi_cached_chconf0(spi
);
1129 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
1130 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
1132 if (t
->tx_buf
== NULL
)
1133 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
1134 else if (t
->rx_buf
== NULL
)
1135 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
1137 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
1138 /* Turbo mode is for more than one word */
1139 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
1140 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
1143 mcspi_write_chconf0(spi
, chconf
);
1148 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1149 (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
))
1150 omap2_mcspi_set_fifo(spi
, t
, 1);
1152 omap2_mcspi_set_enable(spi
, 1);
1154 /* RX_ONLY mode needs dummy data in TX reg */
1155 if (t
->tx_buf
== NULL
)
1156 writel_relaxed(0, cs
->base
1159 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1160 (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
))
1161 count
= omap2_mcspi_txrx_dma(spi
, t
);
1163 count
= omap2_mcspi_txrx_pio(spi
, t
);
1164 m
->actual_length
+= count
;
1166 if (count
!= t
->len
) {
1173 udelay(t
->delay_usecs
);
1175 /* ignore the "leave it on after last xfer" hint */
1177 omap2_mcspi_force_cs(spi
, 0);
1181 omap2_mcspi_set_enable(spi
, 0);
1183 if (mcspi
->fifo_depth
> 0)
1184 omap2_mcspi_set_fifo(spi
, t
, 0);
1186 /* Restore defaults if they were overriden */
1189 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
1193 omap2_mcspi_force_cs(spi
, 0);
1195 if (cd
&& cd
->cs_per_word
) {
1196 chconf
= mcspi
->ctx
.modulctrl
;
1197 chconf
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
1198 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1199 mcspi
->ctx
.modulctrl
=
1200 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1203 omap2_mcspi_set_enable(spi
, 0);
1205 if (mcspi
->fifo_depth
> 0 && t
)
1206 omap2_mcspi_set_fifo(spi
, t
, 0);
1211 static int omap2_mcspi_transfer_one_message(struct spi_master
*master
,
1212 struct spi_message
*m
)
1214 struct spi_device
*spi
;
1215 struct omap2_mcspi
*mcspi
;
1216 struct omap2_mcspi_dma
*mcspi_dma
;
1217 struct spi_transfer
*t
;
1220 mcspi
= spi_master_get_devdata(master
);
1221 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1222 m
->actual_length
= 0;
1225 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1226 const void *tx_buf
= t
->tx_buf
;
1227 void *rx_buf
= t
->rx_buf
;
1228 unsigned len
= t
->len
;
1230 if ((len
&& !(rx_buf
|| tx_buf
))) {
1231 dev_dbg(mcspi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
1240 if (m
->is_dma_mapped
|| len
< DMA_MIN_BYTES
)
1243 if (mcspi_dma
->dma_tx
&& tx_buf
!= NULL
) {
1244 t
->tx_dma
= dma_map_single(mcspi
->dev
, (void *) tx_buf
,
1245 len
, DMA_TO_DEVICE
);
1246 if (dma_mapping_error(mcspi
->dev
, t
->tx_dma
)) {
1247 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1252 if (mcspi_dma
->dma_rx
&& rx_buf
!= NULL
) {
1253 t
->rx_dma
= dma_map_single(mcspi
->dev
, rx_buf
, t
->len
,
1255 if (dma_mapping_error(mcspi
->dev
, t
->rx_dma
)) {
1256 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1259 dma_unmap_single(mcspi
->dev
, t
->tx_dma
,
1260 len
, DMA_TO_DEVICE
);
1266 omap2_mcspi_work(mcspi
, m
);
1267 spi_finalize_current_message(master
);
1271 static int omap2_mcspi_master_setup(struct omap2_mcspi
*mcspi
)
1273 struct spi_master
*master
= mcspi
->master
;
1274 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1277 ret
= pm_runtime_get_sync(mcspi
->dev
);
1281 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
,
1282 OMAP2_MCSPI_WAKEUPENABLE_WKEN
);
1283 ctx
->wakeupenable
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1285 omap2_mcspi_set_master_mode(master
);
1286 pm_runtime_mark_last_busy(mcspi
->dev
);
1287 pm_runtime_put_autosuspend(mcspi
->dev
);
1291 static int omap_mcspi_runtime_resume(struct device
*dev
)
1293 struct omap2_mcspi
*mcspi
;
1294 struct spi_master
*master
;
1296 master
= dev_get_drvdata(dev
);
1297 mcspi
= spi_master_get_devdata(master
);
1298 omap2_mcspi_restore_ctx(mcspi
);
1303 static struct omap2_mcspi_platform_config omap2_pdata
= {
1307 static struct omap2_mcspi_platform_config omap4_pdata
= {
1308 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
1311 static const struct of_device_id omap_mcspi_of_match
[] = {
1313 .compatible
= "ti,omap2-mcspi",
1314 .data
= &omap2_pdata
,
1317 .compatible
= "ti,omap4-mcspi",
1318 .data
= &omap4_pdata
,
1322 MODULE_DEVICE_TABLE(of
, omap_mcspi_of_match
);
1324 static int omap2_mcspi_probe(struct platform_device
*pdev
)
1326 struct spi_master
*master
;
1327 const struct omap2_mcspi_platform_config
*pdata
;
1328 struct omap2_mcspi
*mcspi
;
1331 u32 regs_offset
= 0;
1332 static int bus_num
= 1;
1333 struct device_node
*node
= pdev
->dev
.of_node
;
1334 const struct of_device_id
*match
;
1336 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1337 if (master
== NULL
) {
1338 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1342 /* the spi->mode bits understood by this driver: */
1343 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1344 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1345 master
->setup
= omap2_mcspi_setup
;
1346 master
->auto_runtime_pm
= true;
1347 master
->transfer_one_message
= omap2_mcspi_transfer_one_message
;
1348 master
->cleanup
= omap2_mcspi_cleanup
;
1349 master
->dev
.of_node
= node
;
1350 master
->max_speed_hz
= OMAP2_MCSPI_MAX_FREQ
;
1351 master
->min_speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> 15;
1353 platform_set_drvdata(pdev
, master
);
1355 mcspi
= spi_master_get_devdata(master
);
1356 mcspi
->master
= master
;
1358 match
= of_match_device(omap_mcspi_of_match
, &pdev
->dev
);
1360 u32 num_cs
= 1; /* default number of chipselect */
1361 pdata
= match
->data
;
1363 of_property_read_u32(node
, "ti,spi-num-cs", &num_cs
);
1364 master
->num_chipselect
= num_cs
;
1365 master
->bus_num
= bus_num
++;
1366 if (of_get_property(node
, "ti,pindir-d0-out-d1-in", NULL
))
1367 mcspi
->pin_dir
= MCSPI_PINDIR_D0_OUT_D1_IN
;
1369 pdata
= dev_get_platdata(&pdev
->dev
);
1370 master
->num_chipselect
= pdata
->num_cs
;
1372 master
->bus_num
= pdev
->id
;
1373 mcspi
->pin_dir
= pdata
->pin_dir
;
1375 regs_offset
= pdata
->regs_offset
;
1377 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1383 r
->start
+= regs_offset
;
1384 r
->end
+= regs_offset
;
1385 mcspi
->phys
= r
->start
;
1387 mcspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1388 if (IS_ERR(mcspi
->base
)) {
1389 status
= PTR_ERR(mcspi
->base
);
1393 mcspi
->dev
= &pdev
->dev
;
1395 INIT_LIST_HEAD(&mcspi
->ctx
.cs
);
1397 mcspi
->dma_channels
= devm_kcalloc(&pdev
->dev
, master
->num_chipselect
,
1398 sizeof(struct omap2_mcspi_dma
),
1400 if (mcspi
->dma_channels
== NULL
) {
1405 for (i
= 0; i
< master
->num_chipselect
; i
++) {
1406 char *dma_rx_ch_name
= mcspi
->dma_channels
[i
].dma_rx_ch_name
;
1407 char *dma_tx_ch_name
= mcspi
->dma_channels
[i
].dma_tx_ch_name
;
1408 struct resource
*dma_res
;
1410 sprintf(dma_rx_ch_name
, "rx%d", i
);
1411 if (!pdev
->dev
.of_node
) {
1413 platform_get_resource_byname(pdev
,
1418 "cannot get DMA RX channel\n");
1423 mcspi
->dma_channels
[i
].dma_rx_sync_dev
=
1426 sprintf(dma_tx_ch_name
, "tx%d", i
);
1427 if (!pdev
->dev
.of_node
) {
1429 platform_get_resource_byname(pdev
,
1434 "cannot get DMA TX channel\n");
1439 mcspi
->dma_channels
[i
].dma_tx_sync_dev
=
1447 pm_runtime_use_autosuspend(&pdev
->dev
);
1448 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
1449 pm_runtime_enable(&pdev
->dev
);
1451 status
= omap2_mcspi_master_setup(mcspi
);
1455 status
= devm_spi_register_master(&pdev
->dev
, master
);
1462 pm_runtime_disable(&pdev
->dev
);
1464 spi_master_put(master
);
1468 static int omap2_mcspi_remove(struct platform_device
*pdev
)
1470 struct spi_master
*master
= platform_get_drvdata(pdev
);
1471 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1473 pm_runtime_put_sync(mcspi
->dev
);
1474 pm_runtime_disable(&pdev
->dev
);
1479 /* work with hotplug and coldplug */
1480 MODULE_ALIAS("platform:omap2_mcspi");
1482 #ifdef CONFIG_SUSPEND
1484 * When SPI wake up from off-mode, CS is in activate state. If it was in
1485 * unactive state when driver was suspend, then force it to unactive state at
1488 static int omap2_mcspi_resume(struct device
*dev
)
1490 struct spi_master
*master
= dev_get_drvdata(dev
);
1491 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1492 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1493 struct omap2_mcspi_cs
*cs
;
1495 pm_runtime_get_sync(mcspi
->dev
);
1496 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1497 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1499 * We need to toggle CS state for OMAP take this
1500 * change in account.
1502 cs
->chconf0
|= OMAP2_MCSPI_CHCONF_FORCE
;
1503 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1504 cs
->chconf0
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
1505 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1508 pm_runtime_mark_last_busy(mcspi
->dev
);
1509 pm_runtime_put_autosuspend(mcspi
->dev
);
1513 #define omap2_mcspi_resume NULL
1516 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1517 .resume
= omap2_mcspi_resume
,
1518 .runtime_resume
= omap_mcspi_runtime_resume
,
1521 static struct platform_driver omap2_mcspi_driver
= {
1523 .name
= "omap2_mcspi",
1524 .owner
= THIS_MODULE
,
1525 .pm
= &omap2_mcspi_pm_ops
,
1526 .of_match_table
= omap_mcspi_of_match
,
1528 .probe
= omap2_mcspi_probe
,
1529 .remove
= omap2_mcspi_remove
,
1532 module_platform_driver(omap2_mcspi_driver
);
1533 MODULE_LICENSE("GPL");