2 * PXA2xx SPI DMA engine support.
4 * Copyright (C) 2013, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/pxa2xx_ssp.h>
16 #include <linux/scatterlist.h>
17 #include <linux/sizes.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/pxa2xx_spi.h>
21 #include "spi-pxa2xx.h"
23 static int pxa2xx_spi_map_dma_buffer(struct driver_data
*drv_data
,
24 enum dma_data_direction dir
)
26 int i
, nents
, len
= drv_data
->len
;
27 struct scatterlist
*sg
;
28 struct device
*dmadev
;
32 if (dir
== DMA_TO_DEVICE
) {
33 dmadev
= drv_data
->tx_chan
->device
->dev
;
34 sgt
= &drv_data
->tx_sgt
;
36 drv_data
->tx_map_len
= len
;
38 dmadev
= drv_data
->rx_chan
->device
->dev
;
39 sgt
= &drv_data
->rx_sgt
;
41 drv_data
->rx_map_len
= len
;
44 nents
= DIV_ROUND_UP(len
, SZ_2K
);
45 if (nents
!= sgt
->nents
) {
49 ret
= sg_alloc_table(sgt
, nents
, GFP_ATOMIC
);
55 for_each_sg(sgt
->sgl
, sg
, sgt
->nents
, i
) {
56 size_t bytes
= min_t(size_t, len
, SZ_2K
);
59 sg_set_buf(sg
, pbuf
, bytes
);
61 sg_set_buf(sg
, drv_data
->dummy
, bytes
);
67 nents
= dma_map_sg(dmadev
, sgt
->sgl
, sgt
->nents
, dir
);
74 static void pxa2xx_spi_unmap_dma_buffer(struct driver_data
*drv_data
,
75 enum dma_data_direction dir
)
77 struct device
*dmadev
;
80 if (dir
== DMA_TO_DEVICE
) {
81 dmadev
= drv_data
->tx_chan
->device
->dev
;
82 sgt
= &drv_data
->tx_sgt
;
84 dmadev
= drv_data
->rx_chan
->device
->dev
;
85 sgt
= &drv_data
->rx_sgt
;
88 dma_unmap_sg(dmadev
, sgt
->sgl
, sgt
->nents
, dir
);
91 static void pxa2xx_spi_unmap_dma_buffers(struct driver_data
*drv_data
)
93 if (!drv_data
->dma_mapped
)
96 pxa2xx_spi_unmap_dma_buffer(drv_data
, DMA_FROM_DEVICE
);
97 pxa2xx_spi_unmap_dma_buffer(drv_data
, DMA_TO_DEVICE
);
99 drv_data
->dma_mapped
= 0;
102 static void pxa2xx_spi_dma_transfer_complete(struct driver_data
*drv_data
,
105 struct spi_message
*msg
= drv_data
->cur_msg
;
108 * It is possible that one CPU is handling ROR interrupt and other
109 * just gets DMA completion. Calling pump_transfers() twice for the
110 * same transfer leads to problems thus we prevent concurrent calls
111 * by using ->dma_running.
113 if (atomic_dec_and_test(&drv_data
->dma_running
)) {
114 void __iomem
*reg
= drv_data
->ioaddr
;
117 * If the other CPU is still handling the ROR interrupt we
118 * might not know about the error yet. So we re-check the
119 * ROR bit here before we clear the status register.
122 u32 status
= read_SSSR(reg
) & drv_data
->mask_sr
;
123 error
= status
& SSSR_ROR
;
126 /* Clear status & disable interrupts */
127 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
128 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
129 if (!pxa25x_ssp_comp(drv_data
))
133 pxa2xx_spi_unmap_dma_buffers(drv_data
);
135 drv_data
->tx
+= drv_data
->tx_map_len
;
136 drv_data
->rx
+= drv_data
->rx_map_len
;
138 msg
->actual_length
+= drv_data
->len
;
139 msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
141 /* In case we got an error we disable the SSP now */
142 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
144 msg
->state
= ERROR_STATE
;
147 tasklet_schedule(&drv_data
->pump_transfers
);
151 static void pxa2xx_spi_dma_callback(void *data
)
153 pxa2xx_spi_dma_transfer_complete(data
, false);
156 static struct dma_async_tx_descriptor
*
157 pxa2xx_spi_dma_prepare_one(struct driver_data
*drv_data
,
158 enum dma_transfer_direction dir
)
160 struct pxa2xx_spi_master
*pdata
= drv_data
->master_info
;
161 struct chip_data
*chip
= drv_data
->cur_chip
;
162 enum dma_slave_buswidth width
;
163 struct dma_slave_config cfg
;
164 struct dma_chan
*chan
;
165 struct sg_table
*sgt
;
168 switch (drv_data
->n_bytes
) {
170 width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
173 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
176 width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
180 memset(&cfg
, 0, sizeof(cfg
));
183 if (dir
== DMA_MEM_TO_DEV
) {
184 cfg
.dst_addr
= drv_data
->ssdr_physical
;
185 cfg
.dst_addr_width
= width
;
186 cfg
.dst_maxburst
= chip
->dma_burst_size
;
187 cfg
.slave_id
= pdata
->tx_slave_id
;
189 sgt
= &drv_data
->tx_sgt
;
190 nents
= drv_data
->tx_nents
;
191 chan
= drv_data
->tx_chan
;
193 cfg
.src_addr
= drv_data
->ssdr_physical
;
194 cfg
.src_addr_width
= width
;
195 cfg
.src_maxburst
= chip
->dma_burst_size
;
196 cfg
.slave_id
= pdata
->rx_slave_id
;
198 sgt
= &drv_data
->rx_sgt
;
199 nents
= drv_data
->rx_nents
;
200 chan
= drv_data
->rx_chan
;
203 ret
= dmaengine_slave_config(chan
, &cfg
);
205 dev_warn(&drv_data
->pdev
->dev
, "DMA slave config failed\n");
209 return dmaengine_prep_slave_sg(chan
, sgt
->sgl
, nents
, dir
,
210 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
213 static bool pxa2xx_spi_dma_filter(struct dma_chan
*chan
, void *param
)
215 const struct pxa2xx_spi_master
*pdata
= param
;
217 return chan
->chan_id
== pdata
->tx_chan_id
||
218 chan
->chan_id
== pdata
->rx_chan_id
;
221 bool pxa2xx_spi_dma_is_possible(size_t len
)
223 return len
<= MAX_DMA_LEN
;
226 int pxa2xx_spi_map_dma_buffers(struct driver_data
*drv_data
)
228 const struct chip_data
*chip
= drv_data
->cur_chip
;
231 if (!chip
->enable_dma
)
234 /* Don't bother with DMA if we can't do even a single burst */
235 if (drv_data
->len
< chip
->dma_burst_size
)
238 ret
= pxa2xx_spi_map_dma_buffer(drv_data
, DMA_TO_DEVICE
);
240 dev_warn(&drv_data
->pdev
->dev
, "failed to DMA map TX\n");
244 drv_data
->tx_nents
= ret
;
246 ret
= pxa2xx_spi_map_dma_buffer(drv_data
, DMA_FROM_DEVICE
);
248 pxa2xx_spi_unmap_dma_buffer(drv_data
, DMA_TO_DEVICE
);
249 dev_warn(&drv_data
->pdev
->dev
, "failed to DMA map RX\n");
253 drv_data
->rx_nents
= ret
;
257 irqreturn_t
pxa2xx_spi_dma_transfer(struct driver_data
*drv_data
)
261 status
= read_SSSR(drv_data
->ioaddr
) & drv_data
->mask_sr
;
262 if (status
& SSSR_ROR
) {
263 dev_err(&drv_data
->pdev
->dev
, "FIFO overrun\n");
265 dmaengine_terminate_all(drv_data
->rx_chan
);
266 dmaengine_terminate_all(drv_data
->tx_chan
);
268 pxa2xx_spi_dma_transfer_complete(drv_data
, true);
275 int pxa2xx_spi_dma_prepare(struct driver_data
*drv_data
, u32 dma_burst
)
277 struct dma_async_tx_descriptor
*tx_desc
, *rx_desc
;
279 tx_desc
= pxa2xx_spi_dma_prepare_one(drv_data
, DMA_MEM_TO_DEV
);
281 dev_err(&drv_data
->pdev
->dev
,
282 "failed to get DMA TX descriptor\n");
286 rx_desc
= pxa2xx_spi_dma_prepare_one(drv_data
, DMA_DEV_TO_MEM
);
288 dev_err(&drv_data
->pdev
->dev
,
289 "failed to get DMA RX descriptor\n");
293 /* We are ready when RX completes */
294 rx_desc
->callback
= pxa2xx_spi_dma_callback
;
295 rx_desc
->callback_param
= drv_data
;
297 dmaengine_submit(rx_desc
);
298 dmaengine_submit(tx_desc
);
302 void pxa2xx_spi_dma_start(struct driver_data
*drv_data
)
304 dma_async_issue_pending(drv_data
->rx_chan
);
305 dma_async_issue_pending(drv_data
->tx_chan
);
307 atomic_set(&drv_data
->dma_running
, 1);
310 int pxa2xx_spi_dma_setup(struct driver_data
*drv_data
)
312 struct pxa2xx_spi_master
*pdata
= drv_data
->master_info
;
313 struct device
*dev
= &drv_data
->pdev
->dev
;
317 dma_cap_set(DMA_SLAVE
, mask
);
319 drv_data
->dummy
= devm_kzalloc(dev
, SZ_2K
, GFP_KERNEL
);
320 if (!drv_data
->dummy
)
323 drv_data
->tx_chan
= dma_request_slave_channel_compat(mask
,
324 pxa2xx_spi_dma_filter
, pdata
, dev
, "tx");
325 if (!drv_data
->tx_chan
)
328 drv_data
->rx_chan
= dma_request_slave_channel_compat(mask
,
329 pxa2xx_spi_dma_filter
, pdata
, dev
, "rx");
330 if (!drv_data
->rx_chan
) {
331 dma_release_channel(drv_data
->tx_chan
);
332 drv_data
->tx_chan
= NULL
;
339 void pxa2xx_spi_dma_release(struct driver_data
*drv_data
)
341 if (drv_data
->rx_chan
) {
342 dmaengine_terminate_all(drv_data
->rx_chan
);
343 dma_release_channel(drv_data
->rx_chan
);
344 sg_free_table(&drv_data
->rx_sgt
);
345 drv_data
->rx_chan
= NULL
;
347 if (drv_data
->tx_chan
) {
348 dmaengine_terminate_all(drv_data
->tx_chan
);
349 dma_release_channel(drv_data
->tx_chan
);
350 sg_free_table(&drv_data
->tx_sgt
);
351 drv_data
->tx_chan
= NULL
;
355 void pxa2xx_spi_dma_resume(struct driver_data
*drv_data
)
359 int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data
*chip
,
360 struct spi_device
*spi
,
361 u8 bits_per_word
, u32
*burst_code
,
364 struct pxa2xx_spi_chip
*chip_info
= spi
->controller_data
;
367 * If the DMA burst size is given in chip_info we use that,
368 * otherwise we use the default. Also we use the default FIFO
369 * thresholds for now.
371 *burst_code
= chip_info
? chip_info
->dma_burst_size
: 1;
372 *threshold
= SSCR1_RxTresh(RX_THRESH_DFLT
)
373 | SSCR1_TxTresh(TX_THRESH_DFLT
);