2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/gpio.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/acpi.h>
40 #include <asm/delay.h>
42 #include "spi-pxa2xx.h"
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:pxa2xx-spi");
51 #define TIMOUT_DFLT 1000
54 * for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables, the pxa270 developer
56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
57 * list, but the PXA255 dev man says all bits without really meaning the
58 * service and interrupt enables
60 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67 #define LPSS_RX_THRESH_DFLT 64
68 #define LPSS_TX_LOTHRESH_DFLT 160
69 #define LPSS_TX_HITHRESH_DFLT 224
71 /* Offset from drv_data->lpss_base */
72 #define GENERAL_REG 0x08
73 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
75 #define SPI_CS_CONTROL 0x18
76 #define SPI_CS_CONTROL_SW_MODE BIT(0)
77 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
79 static bool is_lpss_ssp(const struct driver_data
*drv_data
)
81 return drv_data
->ssp_type
== LPSS_SSP
;
85 * Read and write LPSS SSP private registers. Caller must first check that
86 * is_lpss_ssp() returns true before these can be called.
88 static u32
__lpss_ssp_read_priv(struct driver_data
*drv_data
, unsigned offset
)
90 WARN_ON(!drv_data
->lpss_base
);
91 return readl(drv_data
->lpss_base
+ offset
);
94 static void __lpss_ssp_write_priv(struct driver_data
*drv_data
,
95 unsigned offset
, u32 value
)
97 WARN_ON(!drv_data
->lpss_base
);
98 writel(value
, drv_data
->lpss_base
+ offset
);
102 * lpss_ssp_setup - perform LPSS SSP specific setup
103 * @drv_data: pointer to the driver private data
105 * Perform LPSS SSP specific setup. This function must be called first if
106 * one is going to use LPSS SSP private registers.
108 static void lpss_ssp_setup(struct driver_data
*drv_data
)
110 unsigned offset
= 0x400;
113 if (!is_lpss_ssp(drv_data
))
117 * Perform auto-detection of the LPSS SSP private registers. They
118 * can be either at 1k or 2k offset from the base address.
120 orig
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
122 value
= orig
| SPI_CS_CONTROL_SW_MODE
;
123 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
124 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
125 if (value
!= (orig
| SPI_CS_CONTROL_SW_MODE
)) {
130 value
&= ~SPI_CS_CONTROL_SW_MODE
;
131 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
132 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
139 /* Now set the LPSS base */
140 drv_data
->lpss_base
= drv_data
->ioaddr
+ offset
;
142 /* Enable software chip select control */
143 value
= SPI_CS_CONTROL_SW_MODE
| SPI_CS_CONTROL_CS_HIGH
;
144 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
146 /* Enable multiblock DMA transfers */
147 if (drv_data
->master_info
->enable_dma
) {
148 __lpss_ssp_write_priv(drv_data
, SSP_REG
, 1);
150 value
= __lpss_ssp_read_priv(drv_data
, GENERAL_REG
);
151 value
|= GENERAL_REG_RXTO_HOLDOFF_DISABLE
;
152 __lpss_ssp_write_priv(drv_data
, GENERAL_REG
, value
);
156 static void lpss_ssp_cs_control(struct driver_data
*drv_data
, bool enable
)
160 if (!is_lpss_ssp(drv_data
))
163 value
= __lpss_ssp_read_priv(drv_data
, SPI_CS_CONTROL
);
165 value
&= ~SPI_CS_CONTROL_CS_HIGH
;
167 value
|= SPI_CS_CONTROL_CS_HIGH
;
168 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
171 static void cs_assert(struct driver_data
*drv_data
)
173 struct chip_data
*chip
= drv_data
->cur_chip
;
175 if (drv_data
->ssp_type
== CE4100_SSP
) {
176 write_SSSR(drv_data
->cur_chip
->frm
, drv_data
->ioaddr
);
180 if (chip
->cs_control
) {
181 chip
->cs_control(PXA2XX_CS_ASSERT
);
185 if (gpio_is_valid(chip
->gpio_cs
)) {
186 gpio_set_value(chip
->gpio_cs
, chip
->gpio_cs_inverted
);
190 lpss_ssp_cs_control(drv_data
, true);
193 static void cs_deassert(struct driver_data
*drv_data
)
195 struct chip_data
*chip
= drv_data
->cur_chip
;
197 if (drv_data
->ssp_type
== CE4100_SSP
)
200 if (chip
->cs_control
) {
201 chip
->cs_control(PXA2XX_CS_DEASSERT
);
205 if (gpio_is_valid(chip
->gpio_cs
)) {
206 gpio_set_value(chip
->gpio_cs
, !chip
->gpio_cs_inverted
);
210 lpss_ssp_cs_control(drv_data
, false);
213 int pxa2xx_spi_flush(struct driver_data
*drv_data
)
215 unsigned long limit
= loops_per_jiffy
<< 1;
217 void __iomem
*reg
= drv_data
->ioaddr
;
220 while (read_SSSR(reg
) & SSSR_RNE
) {
223 } while ((read_SSSR(reg
) & SSSR_BSY
) && --limit
);
224 write_SSSR_CS(drv_data
, SSSR_ROR
);
229 static int null_writer(struct driver_data
*drv_data
)
231 void __iomem
*reg
= drv_data
->ioaddr
;
232 u8 n_bytes
= drv_data
->n_bytes
;
234 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
235 || (drv_data
->tx
== drv_data
->tx_end
))
239 drv_data
->tx
+= n_bytes
;
244 static int null_reader(struct driver_data
*drv_data
)
246 void __iomem
*reg
= drv_data
->ioaddr
;
247 u8 n_bytes
= drv_data
->n_bytes
;
249 while ((read_SSSR(reg
) & SSSR_RNE
)
250 && (drv_data
->rx
< drv_data
->rx_end
)) {
252 drv_data
->rx
+= n_bytes
;
255 return drv_data
->rx
== drv_data
->rx_end
;
258 static int u8_writer(struct driver_data
*drv_data
)
260 void __iomem
*reg
= drv_data
->ioaddr
;
262 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
263 || (drv_data
->tx
== drv_data
->tx_end
))
266 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
272 static int u8_reader(struct driver_data
*drv_data
)
274 void __iomem
*reg
= drv_data
->ioaddr
;
276 while ((read_SSSR(reg
) & SSSR_RNE
)
277 && (drv_data
->rx
< drv_data
->rx_end
)) {
278 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
282 return drv_data
->rx
== drv_data
->rx_end
;
285 static int u16_writer(struct driver_data
*drv_data
)
287 void __iomem
*reg
= drv_data
->ioaddr
;
289 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
290 || (drv_data
->tx
== drv_data
->tx_end
))
293 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
299 static int u16_reader(struct driver_data
*drv_data
)
301 void __iomem
*reg
= drv_data
->ioaddr
;
303 while ((read_SSSR(reg
) & SSSR_RNE
)
304 && (drv_data
->rx
< drv_data
->rx_end
)) {
305 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
309 return drv_data
->rx
== drv_data
->rx_end
;
312 static int u32_writer(struct driver_data
*drv_data
)
314 void __iomem
*reg
= drv_data
->ioaddr
;
316 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
317 || (drv_data
->tx
== drv_data
->tx_end
))
320 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
326 static int u32_reader(struct driver_data
*drv_data
)
328 void __iomem
*reg
= drv_data
->ioaddr
;
330 while ((read_SSSR(reg
) & SSSR_RNE
)
331 && (drv_data
->rx
< drv_data
->rx_end
)) {
332 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
336 return drv_data
->rx
== drv_data
->rx_end
;
339 void *pxa2xx_spi_next_transfer(struct driver_data
*drv_data
)
341 struct spi_message
*msg
= drv_data
->cur_msg
;
342 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
344 /* Move to next transfer */
345 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
346 drv_data
->cur_transfer
=
347 list_entry(trans
->transfer_list
.next
,
350 return RUNNING_STATE
;
355 /* caller already set message->status; dma and pio irqs are blocked */
356 static void giveback(struct driver_data
*drv_data
)
358 struct spi_transfer
* last_transfer
;
359 struct spi_message
*msg
;
361 msg
= drv_data
->cur_msg
;
362 drv_data
->cur_msg
= NULL
;
363 drv_data
->cur_transfer
= NULL
;
365 last_transfer
= list_entry(msg
->transfers
.prev
,
369 /* Delay if requested before any change in chip select */
370 if (last_transfer
->delay_usecs
)
371 udelay(last_transfer
->delay_usecs
);
373 /* Drop chip select UNLESS cs_change is true or we are returning
374 * a message with an error, or next message is for another chip
376 if (!last_transfer
->cs_change
)
377 cs_deassert(drv_data
);
379 struct spi_message
*next_msg
;
381 /* Holding of cs was hinted, but we need to make sure
382 * the next message is for the same chip. Don't waste
383 * time with the following tests unless this was hinted.
385 * We cannot postpone this until pump_messages, because
386 * after calling msg->complete (below) the driver that
387 * sent the current message could be unloaded, which
388 * could invalidate the cs_control() callback...
391 /* get a pointer to the next message, if any */
392 next_msg
= spi_get_next_queued_message(drv_data
->master
);
394 /* see if the next and current messages point
397 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
399 if (!next_msg
|| msg
->state
== ERROR_STATE
)
400 cs_deassert(drv_data
);
403 spi_finalize_current_message(drv_data
->master
);
404 drv_data
->cur_chip
= NULL
;
407 static void reset_sccr1(struct driver_data
*drv_data
)
409 void __iomem
*reg
= drv_data
->ioaddr
;
410 struct chip_data
*chip
= drv_data
->cur_chip
;
413 sccr1_reg
= read_SSCR1(reg
) & ~drv_data
->int_cr1
;
414 sccr1_reg
&= ~SSCR1_RFT
;
415 sccr1_reg
|= chip
->threshold
;
416 write_SSCR1(sccr1_reg
, reg
);
419 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
421 void __iomem
*reg
= drv_data
->ioaddr
;
423 /* Stop and reset SSP */
424 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
425 reset_sccr1(drv_data
);
426 if (!pxa25x_ssp_comp(drv_data
))
428 pxa2xx_spi_flush(drv_data
);
429 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
431 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
433 drv_data
->cur_msg
->state
= ERROR_STATE
;
434 tasklet_schedule(&drv_data
->pump_transfers
);
437 static void int_transfer_complete(struct driver_data
*drv_data
)
439 void __iomem
*reg
= drv_data
->ioaddr
;
442 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
443 reset_sccr1(drv_data
);
444 if (!pxa25x_ssp_comp(drv_data
))
447 /* Update total byte transferred return count actual bytes read */
448 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
449 (drv_data
->rx_end
- drv_data
->rx
);
451 /* Transfer delays and chip select release are
452 * handled in pump_transfers or giveback
455 /* Move to next transfer */
456 drv_data
->cur_msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
458 /* Schedule transfer tasklet */
459 tasklet_schedule(&drv_data
->pump_transfers
);
462 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
464 void __iomem
*reg
= drv_data
->ioaddr
;
466 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
467 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
469 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
471 if (irq_status
& SSSR_ROR
) {
472 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
476 if (irq_status
& SSSR_TINT
) {
477 write_SSSR(SSSR_TINT
, reg
);
478 if (drv_data
->read(drv_data
)) {
479 int_transfer_complete(drv_data
);
484 /* Drain rx fifo, Fill tx fifo and prevent overruns */
486 if (drv_data
->read(drv_data
)) {
487 int_transfer_complete(drv_data
);
490 } while (drv_data
->write(drv_data
));
492 if (drv_data
->read(drv_data
)) {
493 int_transfer_complete(drv_data
);
497 if (drv_data
->tx
== drv_data
->tx_end
) {
501 sccr1_reg
= read_SSCR1(reg
);
502 sccr1_reg
&= ~SSCR1_TIE
;
505 * PXA25x_SSP has no timeout, set up rx threshould for the
506 * remaining RX bytes.
508 if (pxa25x_ssp_comp(drv_data
)) {
510 sccr1_reg
&= ~SSCR1_RFT
;
512 bytes_left
= drv_data
->rx_end
- drv_data
->rx
;
513 switch (drv_data
->n_bytes
) {
520 if (bytes_left
> RX_THRESH_DFLT
)
521 bytes_left
= RX_THRESH_DFLT
;
523 sccr1_reg
|= SSCR1_RxTresh(bytes_left
);
525 write_SSCR1(sccr1_reg
, reg
);
528 /* We did something */
532 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
534 struct driver_data
*drv_data
= dev_id
;
535 void __iomem
*reg
= drv_data
->ioaddr
;
537 u32 mask
= drv_data
->mask_sr
;
541 * The IRQ might be shared with other peripherals so we must first
542 * check that are we RPM suspended or not. If we are we assume that
543 * the IRQ was not for us (we shouldn't be RPM suspended when the
544 * interrupt is enabled).
546 if (pm_runtime_suspended(&drv_data
->pdev
->dev
))
549 sccr1_reg
= read_SSCR1(reg
);
550 status
= read_SSSR(reg
);
552 /* Ignore possible writes if we don't need to write */
553 if (!(sccr1_reg
& SSCR1_TIE
))
556 if (!(status
& mask
))
559 if (!drv_data
->cur_msg
) {
561 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
562 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
563 if (!pxa25x_ssp_comp(drv_data
))
565 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
567 dev_err(&drv_data
->pdev
->dev
, "bad message state "
568 "in interrupt handler\n");
574 return drv_data
->transfer_handler(drv_data
);
577 static unsigned int ssp_get_clk_div(struct driver_data
*drv_data
, int rate
)
579 unsigned long ssp_clk
= drv_data
->max_clk_rate
;
580 const struct ssp_device
*ssp
= drv_data
->ssp
;
582 rate
= min_t(int, ssp_clk
, rate
);
584 if (ssp
->type
== PXA25x_SSP
|| ssp
->type
== CE4100_SSP
)
585 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
587 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
590 static void pump_transfers(unsigned long data
)
592 struct driver_data
*drv_data
= (struct driver_data
*)data
;
593 struct spi_message
*message
= NULL
;
594 struct spi_transfer
*transfer
= NULL
;
595 struct spi_transfer
*previous
= NULL
;
596 struct chip_data
*chip
= NULL
;
597 void __iomem
*reg
= drv_data
->ioaddr
;
603 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
604 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
606 /* Get current state information */
607 message
= drv_data
->cur_msg
;
608 transfer
= drv_data
->cur_transfer
;
609 chip
= drv_data
->cur_chip
;
611 /* Handle for abort */
612 if (message
->state
== ERROR_STATE
) {
613 message
->status
= -EIO
;
618 /* Handle end of message */
619 if (message
->state
== DONE_STATE
) {
625 /* Delay if requested at end of transfer before CS change */
626 if (message
->state
== RUNNING_STATE
) {
627 previous
= list_entry(transfer
->transfer_list
.prev
,
630 if (previous
->delay_usecs
)
631 udelay(previous
->delay_usecs
);
633 /* Drop chip select only if cs_change is requested */
634 if (previous
->cs_change
)
635 cs_deassert(drv_data
);
638 /* Check if we can DMA this transfer */
639 if (!pxa2xx_spi_dma_is_possible(transfer
->len
) && chip
->enable_dma
) {
641 /* reject already-mapped transfers; PIO won't always work */
642 if (message
->is_dma_mapped
643 || transfer
->rx_dma
|| transfer
->tx_dma
) {
644 dev_err(&drv_data
->pdev
->dev
,
645 "pump_transfers: mapped transfer length "
646 "of %u is greater than %d\n",
647 transfer
->len
, MAX_DMA_LEN
);
648 message
->status
= -EINVAL
;
653 /* warn ... we force this to PIO mode */
654 if (printk_ratelimit())
655 dev_warn(&message
->spi
->dev
, "pump_transfers: "
656 "DMA disabled for transfer length %ld "
658 (long)drv_data
->len
, MAX_DMA_LEN
);
661 /* Setup the transfer state based on the type of transfer */
662 if (pxa2xx_spi_flush(drv_data
) == 0) {
663 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
664 message
->status
= -EIO
;
668 drv_data
->n_bytes
= chip
->n_bytes
;
669 drv_data
->tx
= (void *)transfer
->tx_buf
;
670 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
671 drv_data
->rx
= transfer
->rx_buf
;
672 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
673 drv_data
->rx_dma
= transfer
->rx_dma
;
674 drv_data
->tx_dma
= transfer
->tx_dma
;
675 drv_data
->len
= transfer
->len
;
676 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
677 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
679 /* Change speed and bit per word on a per transfer */
681 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
683 bits
= chip
->bits_per_word
;
684 speed
= chip
->speed_hz
;
686 if (transfer
->speed_hz
)
687 speed
= transfer
->speed_hz
;
689 if (transfer
->bits_per_word
)
690 bits
= transfer
->bits_per_word
;
692 clk_div
= ssp_get_clk_div(drv_data
, speed
);
695 drv_data
->n_bytes
= 1;
696 drv_data
->read
= drv_data
->read
!= null_reader
?
697 u8_reader
: null_reader
;
698 drv_data
->write
= drv_data
->write
!= null_writer
?
699 u8_writer
: null_writer
;
700 } else if (bits
<= 16) {
701 drv_data
->n_bytes
= 2;
702 drv_data
->read
= drv_data
->read
!= null_reader
?
703 u16_reader
: null_reader
;
704 drv_data
->write
= drv_data
->write
!= null_writer
?
705 u16_writer
: null_writer
;
706 } else if (bits
<= 32) {
707 drv_data
->n_bytes
= 4;
708 drv_data
->read
= drv_data
->read
!= null_reader
?
709 u32_reader
: null_reader
;
710 drv_data
->write
= drv_data
->write
!= null_writer
?
711 u32_writer
: null_writer
;
713 /* if bits/word is changed in dma mode, then must check the
714 * thresholds and burst also */
715 if (chip
->enable_dma
) {
716 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
,
720 if (printk_ratelimit())
721 dev_warn(&message
->spi
->dev
,
723 "DMA burst size reduced to "
724 "match bits_per_word\n");
729 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
731 | (bits
> 16 ? SSCR0_EDSS
: 0);
734 message
->state
= RUNNING_STATE
;
736 drv_data
->dma_mapped
= 0;
737 if (pxa2xx_spi_dma_is_possible(drv_data
->len
))
738 drv_data
->dma_mapped
= pxa2xx_spi_map_dma_buffers(drv_data
);
739 if (drv_data
->dma_mapped
) {
741 /* Ensure we have the correct interrupt handler */
742 drv_data
->transfer_handler
= pxa2xx_spi_dma_transfer
;
744 pxa2xx_spi_dma_prepare(drv_data
, dma_burst
);
746 /* Clear status and start DMA engine */
747 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
748 write_SSSR(drv_data
->clear_sr
, reg
);
750 pxa2xx_spi_dma_start(drv_data
);
752 /* Ensure we have the correct interrupt handler */
753 drv_data
->transfer_handler
= interrupt_transfer
;
756 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
757 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
760 if (is_lpss_ssp(drv_data
)) {
761 if ((read_SSIRF(reg
) & 0xff) != chip
->lpss_rx_threshold
)
762 write_SSIRF(chip
->lpss_rx_threshold
, reg
);
763 if ((read_SSITF(reg
) & 0xffff) != chip
->lpss_tx_threshold
)
764 write_SSITF(chip
->lpss_tx_threshold
, reg
);
767 /* see if we need to reload the config registers */
768 if ((read_SSCR0(reg
) != cr0
)
769 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
770 (cr1
& SSCR1_CHANGE_MASK
)) {
772 /* stop the SSP, and update the other bits */
773 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
774 if (!pxa25x_ssp_comp(drv_data
))
775 write_SSTO(chip
->timeout
, reg
);
776 /* first set CR1 without interrupt and service enables */
777 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
778 /* restart the SSP */
779 write_SSCR0(cr0
, reg
);
782 if (!pxa25x_ssp_comp(drv_data
))
783 write_SSTO(chip
->timeout
, reg
);
788 /* after chip select, release the data by enabling service
789 * requests and interrupts, without changing any mode bits */
790 write_SSCR1(cr1
, reg
);
793 static int pxa2xx_spi_transfer_one_message(struct spi_master
*master
,
794 struct spi_message
*msg
)
796 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
798 drv_data
->cur_msg
= msg
;
799 /* Initial message state*/
800 drv_data
->cur_msg
->state
= START_STATE
;
801 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
805 /* prepare to setup the SSP, in pump_transfers, using the per
806 * chip configuration */
807 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
809 /* Mark as busy and launch transfers */
810 tasklet_schedule(&drv_data
->pump_transfers
);
814 static int pxa2xx_spi_unprepare_transfer(struct spi_master
*master
)
816 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
818 /* Disable the SSP now */
819 write_SSCR0(read_SSCR0(drv_data
->ioaddr
) & ~SSCR0_SSE
,
825 static int setup_cs(struct spi_device
*spi
, struct chip_data
*chip
,
826 struct pxa2xx_spi_chip
*chip_info
)
830 if (chip
== NULL
|| chip_info
== NULL
)
833 /* NOTE: setup() can be called multiple times, possibly with
834 * different chip_info, release previously requested GPIO
836 if (gpio_is_valid(chip
->gpio_cs
))
837 gpio_free(chip
->gpio_cs
);
839 /* If (*cs_control) is provided, ignore GPIO chip select */
840 if (chip_info
->cs_control
) {
841 chip
->cs_control
= chip_info
->cs_control
;
845 if (gpio_is_valid(chip_info
->gpio_cs
)) {
846 err
= gpio_request(chip_info
->gpio_cs
, "SPI_CS");
848 dev_err(&spi
->dev
, "failed to request chip select "
849 "GPIO%d\n", chip_info
->gpio_cs
);
853 chip
->gpio_cs
= chip_info
->gpio_cs
;
854 chip
->gpio_cs_inverted
= spi
->mode
& SPI_CS_HIGH
;
856 err
= gpio_direction_output(chip
->gpio_cs
,
857 !chip
->gpio_cs_inverted
);
863 static int setup(struct spi_device
*spi
)
865 struct pxa2xx_spi_chip
*chip_info
= NULL
;
866 struct chip_data
*chip
;
867 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
868 unsigned int clk_div
;
869 uint tx_thres
, tx_hi_thres
, rx_thres
;
871 if (is_lpss_ssp(drv_data
)) {
872 tx_thres
= LPSS_TX_LOTHRESH_DFLT
;
873 tx_hi_thres
= LPSS_TX_HITHRESH_DFLT
;
874 rx_thres
= LPSS_RX_THRESH_DFLT
;
876 tx_thres
= TX_THRESH_DFLT
;
878 rx_thres
= RX_THRESH_DFLT
;
881 /* Only alloc on first setup */
882 chip
= spi_get_ctldata(spi
);
884 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
887 "failed setup: can't allocate chip data\n");
891 if (drv_data
->ssp_type
== CE4100_SSP
) {
892 if (spi
->chip_select
> 4) {
893 dev_err(&spi
->dev
, "failed setup: "
894 "cs number must not be > 4.\n");
899 chip
->frm
= spi
->chip_select
;
902 chip
->enable_dma
= 0;
903 chip
->timeout
= TIMOUT_DFLT
;
906 /* protocol drivers may change the chip settings, so...
907 * if chip_info exists, use it */
908 chip_info
= spi
->controller_data
;
910 /* chip_info isn't always needed */
913 if (chip_info
->timeout
)
914 chip
->timeout
= chip_info
->timeout
;
915 if (chip_info
->tx_threshold
)
916 tx_thres
= chip_info
->tx_threshold
;
917 if (chip_info
->tx_hi_threshold
)
918 tx_hi_thres
= chip_info
->tx_hi_threshold
;
919 if (chip_info
->rx_threshold
)
920 rx_thres
= chip_info
->rx_threshold
;
921 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
922 chip
->dma_threshold
= 0;
923 if (chip_info
->enable_loopback
)
924 chip
->cr1
= SSCR1_LBM
;
925 } else if (ACPI_HANDLE(&spi
->dev
)) {
927 * Slave devices enumerated from ACPI namespace don't
928 * usually have chip_info but we still might want to use
931 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
934 chip
->threshold
= (SSCR1_RxTresh(rx_thres
) & SSCR1_RFT
) |
935 (SSCR1_TxTresh(tx_thres
) & SSCR1_TFT
);
937 chip
->lpss_rx_threshold
= SSIRF_RxThresh(rx_thres
);
938 chip
->lpss_tx_threshold
= SSITF_TxLoThresh(tx_thres
)
939 | SSITF_TxHiThresh(tx_hi_thres
);
941 /* set dma burst and threshold outside of chip_info path so that if
942 * chip_info goes away after setting chip->enable_dma, the
943 * burst and threshold can still respond to changes in bits_per_word */
944 if (chip
->enable_dma
) {
945 /* set up legal burst and threshold for dma */
946 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
, spi
,
948 &chip
->dma_burst_size
,
949 &chip
->dma_threshold
)) {
950 dev_warn(&spi
->dev
, "in setup: DMA burst size reduced "
951 "to match bits_per_word\n");
955 clk_div
= ssp_get_clk_div(drv_data
, spi
->max_speed_hz
);
956 chip
->speed_hz
= spi
->max_speed_hz
;
960 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
961 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
963 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
964 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
965 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
966 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
968 if (spi
->mode
& SPI_LOOP
)
969 chip
->cr1
|= SSCR1_LBM
;
971 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
972 if (!pxa25x_ssp_comp(drv_data
))
973 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
974 drv_data
->max_clk_rate
975 / (1 + ((chip
->cr0
& SSCR0_SCR(0xfff)) >> 8)),
976 chip
->enable_dma
? "DMA" : "PIO");
978 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
979 drv_data
->max_clk_rate
/ 2
980 / (1 + ((chip
->cr0
& SSCR0_SCR(0x0ff)) >> 8)),
981 chip
->enable_dma
? "DMA" : "PIO");
983 if (spi
->bits_per_word
<= 8) {
985 chip
->read
= u8_reader
;
986 chip
->write
= u8_writer
;
987 } else if (spi
->bits_per_word
<= 16) {
989 chip
->read
= u16_reader
;
990 chip
->write
= u16_writer
;
991 } else if (spi
->bits_per_word
<= 32) {
992 chip
->cr0
|= SSCR0_EDSS
;
994 chip
->read
= u32_reader
;
995 chip
->write
= u32_writer
;
997 chip
->bits_per_word
= spi
->bits_per_word
;
999 spi_set_ctldata(spi
, chip
);
1001 if (drv_data
->ssp_type
== CE4100_SSP
)
1004 return setup_cs(spi
, chip
, chip_info
);
1007 static void cleanup(struct spi_device
*spi
)
1009 struct chip_data
*chip
= spi_get_ctldata(spi
);
1010 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1015 if (drv_data
->ssp_type
!= CE4100_SSP
&& gpio_is_valid(chip
->gpio_cs
))
1016 gpio_free(chip
->gpio_cs
);
1022 static struct pxa2xx_spi_master
*
1023 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1025 struct pxa2xx_spi_master
*pdata
;
1026 struct acpi_device
*adev
;
1027 struct ssp_device
*ssp
;
1028 struct resource
*res
;
1031 if (!ACPI_HANDLE(&pdev
->dev
) ||
1032 acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
1035 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1038 "failed to allocate memory for platform data\n");
1042 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1048 ssp
->phys_base
= res
->start
;
1049 ssp
->mmio_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1050 if (IS_ERR(ssp
->mmio_base
))
1053 ssp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1054 ssp
->irq
= platform_get_irq(pdev
, 0);
1055 ssp
->type
= LPSS_SSP
;
1059 if (adev
->pnp
.unique_id
&& !kstrtoint(adev
->pnp
.unique_id
, 0, &devid
))
1060 ssp
->port_id
= devid
;
1062 pdata
->num_chipselect
= 1;
1063 pdata
->enable_dma
= true;
1068 static struct acpi_device_id pxa2xx_spi_acpi_match
[] = {
1074 MODULE_DEVICE_TABLE(acpi
, pxa2xx_spi_acpi_match
);
1076 static inline struct pxa2xx_spi_master
*
1077 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1083 static int pxa2xx_spi_probe(struct platform_device
*pdev
)
1085 struct device
*dev
= &pdev
->dev
;
1086 struct pxa2xx_spi_master
*platform_info
;
1087 struct spi_master
*master
;
1088 struct driver_data
*drv_data
;
1089 struct ssp_device
*ssp
;
1092 platform_info
= dev_get_platdata(dev
);
1093 if (!platform_info
) {
1094 platform_info
= pxa2xx_spi_acpi_get_pdata(pdev
);
1095 if (!platform_info
) {
1096 dev_err(&pdev
->dev
, "missing platform data\n");
1101 ssp
= pxa_ssp_request(pdev
->id
, pdev
->name
);
1103 ssp
= &platform_info
->ssp
;
1105 if (!ssp
->mmio_base
) {
1106 dev_err(&pdev
->dev
, "failed to get ssp\n");
1110 /* Allocate master with space for drv_data and null dma buffer */
1111 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1113 dev_err(&pdev
->dev
, "cannot alloc spi_master\n");
1117 drv_data
= spi_master_get_devdata(master
);
1118 drv_data
->master
= master
;
1119 drv_data
->master_info
= platform_info
;
1120 drv_data
->pdev
= pdev
;
1121 drv_data
->ssp
= ssp
;
1123 master
->dev
.parent
= &pdev
->dev
;
1124 master
->dev
.of_node
= pdev
->dev
.of_node
;
1125 /* the spi->mode bits understood by this driver: */
1126 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
1128 master
->bus_num
= ssp
->port_id
;
1129 master
->num_chipselect
= platform_info
->num_chipselect
;
1130 master
->dma_alignment
= DMA_ALIGNMENT
;
1131 master
->cleanup
= cleanup
;
1132 master
->setup
= setup
;
1133 master
->transfer_one_message
= pxa2xx_spi_transfer_one_message
;
1134 master
->unprepare_transfer_hardware
= pxa2xx_spi_unprepare_transfer
;
1135 master
->auto_runtime_pm
= true;
1137 drv_data
->ssp_type
= ssp
->type
;
1138 drv_data
->null_dma_buf
= (u32
*)PTR_ALIGN(&drv_data
[1], DMA_ALIGNMENT
);
1140 drv_data
->ioaddr
= ssp
->mmio_base
;
1141 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1142 if (pxa25x_ssp_comp(drv_data
)) {
1143 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 16);
1144 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1145 drv_data
->dma_cr1
= 0;
1146 drv_data
->clear_sr
= SSSR_ROR
;
1147 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1149 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1150 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1151 drv_data
->dma_cr1
= DEFAULT_DMA_CR1
;
1152 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1153 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1156 status
= request_irq(ssp
->irq
, ssp_int
, IRQF_SHARED
, dev_name(dev
),
1159 dev_err(&pdev
->dev
, "cannot get IRQ %d\n", ssp
->irq
);
1160 goto out_error_master_alloc
;
1163 /* Setup DMA if requested */
1164 drv_data
->tx_channel
= -1;
1165 drv_data
->rx_channel
= -1;
1166 if (platform_info
->enable_dma
) {
1167 status
= pxa2xx_spi_dma_setup(drv_data
);
1169 dev_dbg(dev
, "no DMA channels available, using PIO\n");
1170 platform_info
->enable_dma
= false;
1174 /* Enable SOC clock */
1175 clk_prepare_enable(ssp
->clk
);
1177 drv_data
->max_clk_rate
= clk_get_rate(ssp
->clk
);
1179 /* Load default SSP configuration */
1180 write_SSCR0(0, drv_data
->ioaddr
);
1181 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT
) |
1182 SSCR1_TxTresh(TX_THRESH_DFLT
),
1184 write_SSCR0(SSCR0_SCR(2)
1186 | SSCR0_DataSize(8),
1188 if (!pxa25x_ssp_comp(drv_data
))
1189 write_SSTO(0, drv_data
->ioaddr
);
1190 write_SSPSP(0, drv_data
->ioaddr
);
1192 lpss_ssp_setup(drv_data
);
1194 tasklet_init(&drv_data
->pump_transfers
, pump_transfers
,
1195 (unsigned long)drv_data
);
1197 /* Register with the SPI framework */
1198 platform_set_drvdata(pdev
, drv_data
);
1199 status
= spi_register_master(master
);
1201 dev_err(&pdev
->dev
, "problem registering spi master\n");
1202 goto out_error_clock_enabled
;
1205 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
1206 pm_runtime_use_autosuspend(&pdev
->dev
);
1207 pm_runtime_set_active(&pdev
->dev
);
1208 pm_runtime_enable(&pdev
->dev
);
1212 out_error_clock_enabled
:
1213 clk_disable_unprepare(ssp
->clk
);
1214 pxa2xx_spi_dma_release(drv_data
);
1215 free_irq(ssp
->irq
, drv_data
);
1217 out_error_master_alloc
:
1218 spi_master_put(master
);
1223 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1225 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1226 struct ssp_device
*ssp
;
1230 ssp
= drv_data
->ssp
;
1232 pm_runtime_get_sync(&pdev
->dev
);
1234 /* Disable the SSP at the peripheral and SOC level */
1235 write_SSCR0(0, drv_data
->ioaddr
);
1236 clk_disable_unprepare(ssp
->clk
);
1239 if (drv_data
->master_info
->enable_dma
)
1240 pxa2xx_spi_dma_release(drv_data
);
1242 pm_runtime_put_noidle(&pdev
->dev
);
1243 pm_runtime_disable(&pdev
->dev
);
1246 free_irq(ssp
->irq
, drv_data
);
1251 /* Disconnect from the SPI framework */
1252 spi_unregister_master(drv_data
->master
);
1257 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1261 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1262 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1266 static int pxa2xx_spi_suspend(struct device
*dev
)
1268 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1269 struct ssp_device
*ssp
= drv_data
->ssp
;
1272 status
= spi_master_suspend(drv_data
->master
);
1275 write_SSCR0(0, drv_data
->ioaddr
);
1276 clk_disable_unprepare(ssp
->clk
);
1281 static int pxa2xx_spi_resume(struct device
*dev
)
1283 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1284 struct ssp_device
*ssp
= drv_data
->ssp
;
1287 pxa2xx_spi_dma_resume(drv_data
);
1289 /* Enable the SSP clock */
1290 clk_prepare_enable(ssp
->clk
);
1292 /* Start the queue running */
1293 status
= spi_master_resume(drv_data
->master
);
1295 dev_err(dev
, "problem starting queue (%d)\n", status
);
1303 #ifdef CONFIG_PM_RUNTIME
1304 static int pxa2xx_spi_runtime_suspend(struct device
*dev
)
1306 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1308 clk_disable_unprepare(drv_data
->ssp
->clk
);
1312 static int pxa2xx_spi_runtime_resume(struct device
*dev
)
1314 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1316 clk_prepare_enable(drv_data
->ssp
->clk
);
1321 static const struct dev_pm_ops pxa2xx_spi_pm_ops
= {
1322 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend
, pxa2xx_spi_resume
)
1323 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend
,
1324 pxa2xx_spi_runtime_resume
, NULL
)
1327 static struct platform_driver driver
= {
1329 .name
= "pxa2xx-spi",
1330 .owner
= THIS_MODULE
,
1331 .pm
= &pxa2xx_spi_pm_ops
,
1332 .acpi_match_table
= ACPI_PTR(pxa2xx_spi_acpi_match
),
1334 .probe
= pxa2xx_spi_probe
,
1335 .remove
= pxa2xx_spi_remove
,
1336 .shutdown
= pxa2xx_spi_shutdown
,
1339 static int __init
pxa2xx_spi_init(void)
1341 return platform_driver_register(&driver
);
1343 subsys_initcall(pxa2xx_spi_init
);
1345 static void __exit
pxa2xx_spi_exit(void)
1347 platform_driver_unregister(&driver
);
1349 module_exit(pxa2xx_spi_exit
);