2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/clk.h>
17 #include <linux/dmaengine.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/scatterlist.h>
25 #define DRIVER_NAME "rockchip-spi"
27 /* SPI register offsets */
28 #define ROCKCHIP_SPI_CTRLR0 0x0000
29 #define ROCKCHIP_SPI_CTRLR1 0x0004
30 #define ROCKCHIP_SPI_SSIENR 0x0008
31 #define ROCKCHIP_SPI_SER 0x000c
32 #define ROCKCHIP_SPI_BAUDR 0x0010
33 #define ROCKCHIP_SPI_TXFTLR 0x0014
34 #define ROCKCHIP_SPI_RXFTLR 0x0018
35 #define ROCKCHIP_SPI_TXFLR 0x001c
36 #define ROCKCHIP_SPI_RXFLR 0x0020
37 #define ROCKCHIP_SPI_SR 0x0024
38 #define ROCKCHIP_SPI_IPR 0x0028
39 #define ROCKCHIP_SPI_IMR 0x002c
40 #define ROCKCHIP_SPI_ISR 0x0030
41 #define ROCKCHIP_SPI_RISR 0x0034
42 #define ROCKCHIP_SPI_ICR 0x0038
43 #define ROCKCHIP_SPI_DMACR 0x003c
44 #define ROCKCHIP_SPI_DMATDLR 0x0040
45 #define ROCKCHIP_SPI_DMARDLR 0x0044
46 #define ROCKCHIP_SPI_TXDR 0x0400
47 #define ROCKCHIP_SPI_RXDR 0x0800
49 /* Bit fields in CTRLR0 */
50 #define CR0_DFS_OFFSET 0
52 #define CR0_CFS_OFFSET 2
54 #define CR0_SCPH_OFFSET 6
56 #define CR0_SCPOL_OFFSET 7
58 #define CR0_CSM_OFFSET 8
59 #define CR0_CSM_KEEP 0x0
60 /* ss_n be high for half sclk_out cycles */
61 #define CR0_CSM_HALF 0X1
62 /* ss_n be high for one sclk_out cycle */
63 #define CR0_CSM_ONE 0x2
65 /* ss_n to sclk_out delay */
66 #define CR0_SSD_OFFSET 10
68 * The period between ss_n active and
69 * sclk_out active is half sclk_out cycles
71 #define CR0_SSD_HALF 0x0
73 * The period between ss_n active and
74 * sclk_out active is one sclk_out cycle
76 #define CR0_SSD_ONE 0x1
78 #define CR0_EM_OFFSET 11
79 #define CR0_EM_LITTLE 0x0
80 #define CR0_EM_BIG 0x1
82 #define CR0_FBM_OFFSET 12
83 #define CR0_FBM_MSB 0x0
84 #define CR0_FBM_LSB 0x1
86 #define CR0_BHT_OFFSET 13
87 #define CR0_BHT_16BIT 0x0
88 #define CR0_BHT_8BIT 0x1
90 #define CR0_RSD_OFFSET 14
92 #define CR0_FRF_OFFSET 16
93 #define CR0_FRF_SPI 0x0
94 #define CR0_FRF_SSP 0x1
95 #define CR0_FRF_MICROWIRE 0x2
97 #define CR0_XFM_OFFSET 18
98 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
99 #define CR0_XFM_TR 0x0
100 #define CR0_XFM_TO 0x1
101 #define CR0_XFM_RO 0x2
103 #define CR0_OPM_OFFSET 20
104 #define CR0_OPM_MASTER 0x0
105 #define CR0_OPM_SLAVE 0x1
107 #define CR0_MTM_OFFSET 0x21
109 /* Bit fields in SER, 2bit */
112 /* Bit fields in SR, 5bit */
114 #define SR_BUSY (1 << 0)
115 #define SR_TF_FULL (1 << 1)
116 #define SR_TF_EMPTY (1 << 2)
117 #define SR_RF_EMPTY (1 << 3)
118 #define SR_RF_FULL (1 << 4)
120 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
121 #define INT_MASK 0x1f
122 #define INT_TF_EMPTY (1 << 0)
123 #define INT_TF_OVERFLOW (1 << 1)
124 #define INT_RF_UNDERFLOW (1 << 2)
125 #define INT_RF_OVERFLOW (1 << 3)
126 #define INT_RF_FULL (1 << 4)
128 /* Bit fields in ICR, 4bit */
129 #define ICR_MASK 0x0f
130 #define ICR_ALL (1 << 0)
131 #define ICR_RF_UNDERFLOW (1 << 1)
132 #define ICR_RF_OVERFLOW (1 << 2)
133 #define ICR_TF_OVERFLOW (1 << 3)
135 /* Bit fields in DMACR */
136 #define RF_DMA_EN (1 << 0)
137 #define TF_DMA_EN (1 << 1)
139 #define RXBUSY (1 << 0)
140 #define TXBUSY (1 << 1)
142 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
143 #define MAX_SCLK_OUT 50000000
145 enum rockchip_ssi_type
{
151 struct rockchip_spi_dma_data
{
153 enum dma_transfer_direction direction
;
157 struct rockchip_spi
{
159 struct spi_master
*master
;
162 struct clk
*apb_pclk
;
165 /*depth of the FIFO buffer */
167 /* max bus freq supported */
169 /* supported slave numbers */
170 enum rockchip_ssi_type type
;
190 struct sg_table tx_sg
;
191 struct sg_table rx_sg
;
192 struct rockchip_spi_dma_data dma_rx
;
193 struct rockchip_spi_dma_data dma_tx
;
196 static inline void spi_enable_chip(struct rockchip_spi
*rs
, int enable
)
198 writel_relaxed((enable
? 1 : 0), rs
->regs
+ ROCKCHIP_SPI_SSIENR
);
201 static inline void spi_set_clk(struct rockchip_spi
*rs
, u16 div
)
203 writel_relaxed(div
, rs
->regs
+ ROCKCHIP_SPI_BAUDR
);
206 static inline void flush_fifo(struct rockchip_spi
*rs
)
208 while (readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXFLR
))
209 readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXDR
);
212 static inline void wait_for_idle(struct rockchip_spi
*rs
)
214 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5);
217 if (!(readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SR
) & SR_BUSY
))
219 } while (!time_after(jiffies
, timeout
));
221 dev_warn(rs
->dev
, "spi controller is in busy state!\n");
224 static u32
get_fifo_len(struct rockchip_spi
*rs
)
228 for (fifo
= 2; fifo
< 32; fifo
++) {
229 writel_relaxed(fifo
, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
230 if (fifo
!= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_TXFTLR
))
234 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
236 return (fifo
== 31) ? 0 : fifo
;
239 static inline u32
tx_max(struct rockchip_spi
*rs
)
241 u32 tx_left
, tx_room
;
243 tx_left
= (rs
->tx_end
- rs
->tx
) / rs
->n_bytes
;
244 tx_room
= rs
->fifo_len
- readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_TXFLR
);
246 return min(tx_left
, tx_room
);
249 static inline u32
rx_max(struct rockchip_spi
*rs
)
251 u32 rx_left
= (rs
->rx_end
- rs
->rx
) / rs
->n_bytes
;
252 u32 rx_room
= (u32
)readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXFLR
);
254 return min(rx_left
, rx_room
);
257 static void rockchip_spi_set_cs(struct spi_device
*spi
, bool enable
)
260 struct spi_master
*master
= spi
->master
;
261 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
263 pm_runtime_get_sync(rs
->dev
);
265 ser
= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SER
) & SER_MASK
;
269 * static void spi_set_cs(struct spi_device *spi, bool enable)
271 * if (spi->mode & SPI_CS_HIGH)
274 * if (spi->cs_gpio >= 0)
275 * gpio_set_value(spi->cs_gpio, !enable);
276 * else if (spi->master->set_cs)
277 * spi->master->set_cs(spi, !enable);
280 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
283 ser
|= 1 << spi
->chip_select
;
285 ser
&= ~(1 << spi
->chip_select
);
287 writel_relaxed(ser
, rs
->regs
+ ROCKCHIP_SPI_SER
);
289 pm_runtime_put_sync(rs
->dev
);
292 static int rockchip_spi_prepare_message(struct spi_master
*master
,
293 struct spi_message
*msg
)
295 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
296 struct spi_device
*spi
= msg
->spi
;
298 rs
->mode
= spi
->mode
;
303 static void rockchip_spi_handle_err(struct spi_master
*master
,
304 struct spi_message
*msg
)
307 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
309 spin_lock_irqsave(&rs
->lock
, flags
);
312 * For DMA mode, we need terminate DMA channel and flush
313 * fifo for the next transfer if DMA thansfer timeout.
314 * handle_err() was called by core if transfer failed.
315 * Maybe it is reasonable for error handling here.
318 if (rs
->state
& RXBUSY
) {
319 dmaengine_terminate_async(rs
->dma_rx
.ch
);
323 if (rs
->state
& TXBUSY
)
324 dmaengine_terminate_async(rs
->dma_tx
.ch
);
327 spin_unlock_irqrestore(&rs
->lock
, flags
);
330 static int rockchip_spi_unprepare_message(struct spi_master
*master
,
331 struct spi_message
*msg
)
333 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
335 spi_enable_chip(rs
, 0);
340 static void rockchip_spi_pio_writer(struct rockchip_spi
*rs
)
342 u32 max
= tx_max(rs
);
346 if (rs
->n_bytes
== 1)
347 txw
= *(u8
*)(rs
->tx
);
349 txw
= *(u16
*)(rs
->tx
);
351 writel_relaxed(txw
, rs
->regs
+ ROCKCHIP_SPI_TXDR
);
352 rs
->tx
+= rs
->n_bytes
;
356 static void rockchip_spi_pio_reader(struct rockchip_spi
*rs
)
358 u32 max
= rx_max(rs
);
362 rxw
= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXDR
);
363 if (rs
->n_bytes
== 1)
364 *(u8
*)(rs
->rx
) = (u8
)rxw
;
366 *(u16
*)(rs
->rx
) = (u16
)rxw
;
367 rs
->rx
+= rs
->n_bytes
;
371 static int rockchip_spi_pio_transfer(struct rockchip_spi
*rs
)
377 remain
= rs
->tx_end
- rs
->tx
;
378 rockchip_spi_pio_writer(rs
);
382 remain
= rs
->rx_end
- rs
->rx
;
383 rockchip_spi_pio_reader(rs
);
389 /* If tx, wait until the FIFO data completely. */
393 spi_enable_chip(rs
, 0);
398 static void rockchip_spi_dma_rxcb(void *data
)
401 struct rockchip_spi
*rs
= data
;
403 spin_lock_irqsave(&rs
->lock
, flags
);
405 rs
->state
&= ~RXBUSY
;
406 if (!(rs
->state
& TXBUSY
)) {
407 spi_enable_chip(rs
, 0);
408 spi_finalize_current_transfer(rs
->master
);
411 spin_unlock_irqrestore(&rs
->lock
, flags
);
414 static void rockchip_spi_dma_txcb(void *data
)
417 struct rockchip_spi
*rs
= data
;
419 /* Wait until the FIFO data completely. */
422 spin_lock_irqsave(&rs
->lock
, flags
);
424 rs
->state
&= ~TXBUSY
;
425 if (!(rs
->state
& RXBUSY
)) {
426 spi_enable_chip(rs
, 0);
427 spi_finalize_current_transfer(rs
->master
);
430 spin_unlock_irqrestore(&rs
->lock
, flags
);
433 static int rockchip_spi_prepare_dma(struct rockchip_spi
*rs
)
436 struct dma_slave_config rxconf
, txconf
;
437 struct dma_async_tx_descriptor
*rxdesc
, *txdesc
;
439 spin_lock_irqsave(&rs
->lock
, flags
);
440 rs
->state
&= ~RXBUSY
;
441 rs
->state
&= ~TXBUSY
;
442 spin_unlock_irqrestore(&rs
->lock
, flags
);
446 rxconf
.direction
= rs
->dma_rx
.direction
;
447 rxconf
.src_addr
= rs
->dma_rx
.addr
;
448 rxconf
.src_addr_width
= rs
->n_bytes
;
449 rxconf
.src_maxburst
= rs
->n_bytes
;
450 dmaengine_slave_config(rs
->dma_rx
.ch
, &rxconf
);
452 rxdesc
= dmaengine_prep_slave_sg(
454 rs
->rx_sg
.sgl
, rs
->rx_sg
.nents
,
455 rs
->dma_rx
.direction
, DMA_PREP_INTERRUPT
);
459 rxdesc
->callback
= rockchip_spi_dma_rxcb
;
460 rxdesc
->callback_param
= rs
;
465 txconf
.direction
= rs
->dma_tx
.direction
;
466 txconf
.dst_addr
= rs
->dma_tx
.addr
;
467 txconf
.dst_addr_width
= rs
->n_bytes
;
468 txconf
.dst_maxburst
= rs
->n_bytes
;
469 dmaengine_slave_config(rs
->dma_tx
.ch
, &txconf
);
471 txdesc
= dmaengine_prep_slave_sg(
473 rs
->tx_sg
.sgl
, rs
->tx_sg
.nents
,
474 rs
->dma_tx
.direction
, DMA_PREP_INTERRUPT
);
477 dmaengine_terminate_sync(rs
->dma_rx
.ch
);
481 txdesc
->callback
= rockchip_spi_dma_txcb
;
482 txdesc
->callback_param
= rs
;
485 /* rx must be started before tx due to spi instinct */
487 spin_lock_irqsave(&rs
->lock
, flags
);
489 spin_unlock_irqrestore(&rs
->lock
, flags
);
490 dmaengine_submit(rxdesc
);
491 dma_async_issue_pending(rs
->dma_rx
.ch
);
495 spin_lock_irqsave(&rs
->lock
, flags
);
497 spin_unlock_irqrestore(&rs
->lock
, flags
);
498 dmaengine_submit(txdesc
);
499 dma_async_issue_pending(rs
->dma_tx
.ch
);
505 static void rockchip_spi_config(struct rockchip_spi
*rs
)
511 u32 cr0
= (CR0_BHT_8BIT
<< CR0_BHT_OFFSET
)
512 | (CR0_SSD_ONE
<< CR0_SSD_OFFSET
)
513 | (CR0_EM_BIG
<< CR0_EM_OFFSET
);
515 cr0
|= (rs
->n_bytes
<< CR0_DFS_OFFSET
);
516 cr0
|= ((rs
->mode
& 0x3) << CR0_SCPH_OFFSET
);
517 cr0
|= (rs
->tmode
<< CR0_XFM_OFFSET
);
518 cr0
|= (rs
->type
<< CR0_FRF_OFFSET
);
527 if (WARN_ON(rs
->speed
> MAX_SCLK_OUT
))
528 rs
->speed
= MAX_SCLK_OUT
;
530 /* the minimum divsor is 2 */
531 if (rs
->max_freq
< 2 * rs
->speed
) {
532 clk_set_rate(rs
->spiclk
, 2 * rs
->speed
);
533 rs
->max_freq
= clk_get_rate(rs
->spiclk
);
536 /* div doesn't support odd number */
537 div
= DIV_ROUND_UP(rs
->max_freq
, rs
->speed
);
538 div
= (div
+ 1) & 0xfffe;
540 /* Rx sample delay is expressed in parent clock cycles (max 3) */
541 rsd
= DIV_ROUND_CLOSEST(rs
->rsd_nsecs
* (rs
->max_freq
>> 8),
543 if (!rsd
&& rs
->rsd_nsecs
) {
544 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
545 rs
->max_freq
, rs
->rsd_nsecs
);
546 } else if (rsd
> 3) {
548 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
549 rs
->max_freq
, rs
->rsd_nsecs
,
550 rsd
* 1000000000U / rs
->max_freq
);
552 cr0
|= rsd
<< CR0_RSD_OFFSET
;
554 writel_relaxed(cr0
, rs
->regs
+ ROCKCHIP_SPI_CTRLR0
);
556 writel_relaxed(rs
->len
- 1, rs
->regs
+ ROCKCHIP_SPI_CTRLR1
);
557 writel_relaxed(rs
->fifo_len
/ 2 - 1, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
558 writel_relaxed(rs
->fifo_len
/ 2 - 1, rs
->regs
+ ROCKCHIP_SPI_RXFTLR
);
560 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_DMATDLR
);
561 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_DMARDLR
);
562 writel_relaxed(dmacr
, rs
->regs
+ ROCKCHIP_SPI_DMACR
);
564 spi_set_clk(rs
, div
);
566 dev_dbg(rs
->dev
, "cr0 0x%x, div %d\n", cr0
, div
);
569 static int rockchip_spi_transfer_one(
570 struct spi_master
*master
,
571 struct spi_device
*spi
,
572 struct spi_transfer
*xfer
)
575 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
577 WARN_ON(readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SSIENR
) &&
578 (readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SR
) & SR_BUSY
));
580 if (!xfer
->tx_buf
&& !xfer
->rx_buf
) {
581 dev_err(rs
->dev
, "No buffer for transfer\n");
585 rs
->speed
= xfer
->speed_hz
;
586 rs
->bpw
= xfer
->bits_per_word
;
587 rs
->n_bytes
= rs
->bpw
>> 3;
589 rs
->tx
= xfer
->tx_buf
;
590 rs
->tx_end
= rs
->tx
+ xfer
->len
;
591 rs
->rx
= xfer
->rx_buf
;
592 rs
->rx_end
= rs
->rx
+ xfer
->len
;
595 rs
->tx_sg
= xfer
->tx_sg
;
596 rs
->rx_sg
= xfer
->rx_sg
;
598 if (rs
->tx
&& rs
->rx
)
599 rs
->tmode
= CR0_XFM_TR
;
601 rs
->tmode
= CR0_XFM_TO
;
603 rs
->tmode
= CR0_XFM_RO
;
605 /* we need prepare dma before spi was enabled */
606 if (master
->can_dma
&& master
->can_dma(master
, spi
, xfer
))
611 rockchip_spi_config(rs
);
614 if (rs
->tmode
== CR0_XFM_RO
) {
615 /* rx: dma must be prepared first */
616 ret
= rockchip_spi_prepare_dma(rs
);
617 spi_enable_chip(rs
, 1);
619 /* tx or tr: spi must be enabled first */
620 spi_enable_chip(rs
, 1);
621 ret
= rockchip_spi_prepare_dma(rs
);
624 spi_enable_chip(rs
, 1);
625 ret
= rockchip_spi_pio_transfer(rs
);
631 static bool rockchip_spi_can_dma(struct spi_master
*master
,
632 struct spi_device
*spi
,
633 struct spi_transfer
*xfer
)
635 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
637 return (xfer
->len
> rs
->fifo_len
);
640 static int rockchip_spi_probe(struct platform_device
*pdev
)
643 struct rockchip_spi
*rs
;
644 struct spi_master
*master
;
645 struct resource
*mem
;
648 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct rockchip_spi
));
652 platform_set_drvdata(pdev
, master
);
654 rs
= spi_master_get_devdata(master
);
656 /* Get basic io resource and map it */
657 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
658 rs
->regs
= devm_ioremap_resource(&pdev
->dev
, mem
);
659 if (IS_ERR(rs
->regs
)) {
660 ret
= PTR_ERR(rs
->regs
);
661 goto err_ioremap_resource
;
664 rs
->apb_pclk
= devm_clk_get(&pdev
->dev
, "apb_pclk");
665 if (IS_ERR(rs
->apb_pclk
)) {
666 dev_err(&pdev
->dev
, "Failed to get apb_pclk\n");
667 ret
= PTR_ERR(rs
->apb_pclk
);
668 goto err_ioremap_resource
;
671 rs
->spiclk
= devm_clk_get(&pdev
->dev
, "spiclk");
672 if (IS_ERR(rs
->spiclk
)) {
673 dev_err(&pdev
->dev
, "Failed to get spi_pclk\n");
674 ret
= PTR_ERR(rs
->spiclk
);
675 goto err_ioremap_resource
;
678 ret
= clk_prepare_enable(rs
->apb_pclk
);
680 dev_err(&pdev
->dev
, "Failed to enable apb_pclk\n");
681 goto err_ioremap_resource
;
684 ret
= clk_prepare_enable(rs
->spiclk
);
686 dev_err(&pdev
->dev
, "Failed to enable spi_clk\n");
687 goto err_spiclk_enable
;
690 spi_enable_chip(rs
, 0);
692 rs
->type
= SSI_MOTO_SPI
;
694 rs
->dev
= &pdev
->dev
;
695 rs
->max_freq
= clk_get_rate(rs
->spiclk
);
697 if (!of_property_read_u32(pdev
->dev
.of_node
, "rx-sample-delay-ns",
699 rs
->rsd_nsecs
= rsd_nsecs
;
701 rs
->fifo_len
= get_fifo_len(rs
);
703 dev_err(&pdev
->dev
, "Failed to get fifo length\n");
705 goto err_get_fifo_len
;
708 spin_lock_init(&rs
->lock
);
710 pm_runtime_set_active(&pdev
->dev
);
711 pm_runtime_enable(&pdev
->dev
);
713 master
->auto_runtime_pm
= true;
714 master
->bus_num
= pdev
->id
;
715 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LOOP
;
716 master
->num_chipselect
= 2;
717 master
->dev
.of_node
= pdev
->dev
.of_node
;
718 master
->bits_per_word_mask
= SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
720 master
->set_cs
= rockchip_spi_set_cs
;
721 master
->prepare_message
= rockchip_spi_prepare_message
;
722 master
->unprepare_message
= rockchip_spi_unprepare_message
;
723 master
->transfer_one
= rockchip_spi_transfer_one
;
724 master
->handle_err
= rockchip_spi_handle_err
;
726 rs
->dma_tx
.ch
= dma_request_slave_channel(rs
->dev
, "tx");
727 if (IS_ERR_OR_NULL(rs
->dma_tx
.ch
)) {
728 /* Check tx to see if we need defer probing driver */
729 if (PTR_ERR(rs
->dma_tx
.ch
) == -EPROBE_DEFER
) {
731 goto err_get_fifo_len
;
733 dev_warn(rs
->dev
, "Failed to request TX DMA channel\n");
736 rs
->dma_rx
.ch
= dma_request_slave_channel(rs
->dev
, "rx");
737 if (!rs
->dma_rx
.ch
) {
739 dma_release_channel(rs
->dma_tx
.ch
);
740 rs
->dma_tx
.ch
= NULL
;
742 dev_warn(rs
->dev
, "Failed to request RX DMA channel\n");
745 if (rs
->dma_tx
.ch
&& rs
->dma_rx
.ch
) {
746 rs
->dma_tx
.addr
= (dma_addr_t
)(mem
->start
+ ROCKCHIP_SPI_TXDR
);
747 rs
->dma_rx
.addr
= (dma_addr_t
)(mem
->start
+ ROCKCHIP_SPI_RXDR
);
748 rs
->dma_tx
.direction
= DMA_MEM_TO_DEV
;
749 rs
->dma_rx
.direction
= DMA_DEV_TO_MEM
;
751 master
->can_dma
= rockchip_spi_can_dma
;
752 master
->dma_tx
= rs
->dma_tx
.ch
;
753 master
->dma_rx
= rs
->dma_rx
.ch
;
756 ret
= devm_spi_register_master(&pdev
->dev
, master
);
758 dev_err(&pdev
->dev
, "Failed to register master\n");
759 goto err_register_master
;
765 pm_runtime_disable(&pdev
->dev
);
767 dma_release_channel(rs
->dma_tx
.ch
);
769 dma_release_channel(rs
->dma_rx
.ch
);
771 clk_disable_unprepare(rs
->spiclk
);
773 clk_disable_unprepare(rs
->apb_pclk
);
774 err_ioremap_resource
:
775 spi_master_put(master
);
780 static int rockchip_spi_remove(struct platform_device
*pdev
)
782 struct spi_master
*master
= spi_master_get(platform_get_drvdata(pdev
));
783 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
785 pm_runtime_disable(&pdev
->dev
);
787 clk_disable_unprepare(rs
->spiclk
);
788 clk_disable_unprepare(rs
->apb_pclk
);
791 dma_release_channel(rs
->dma_tx
.ch
);
793 dma_release_channel(rs
->dma_rx
.ch
);
795 spi_master_put(master
);
800 #ifdef CONFIG_PM_SLEEP
801 static int rockchip_spi_suspend(struct device
*dev
)
804 struct spi_master
*master
= dev_get_drvdata(dev
);
805 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
807 ret
= spi_master_suspend(rs
->master
);
811 if (!pm_runtime_suspended(dev
)) {
812 clk_disable_unprepare(rs
->spiclk
);
813 clk_disable_unprepare(rs
->apb_pclk
);
819 static int rockchip_spi_resume(struct device
*dev
)
822 struct spi_master
*master
= dev_get_drvdata(dev
);
823 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
825 if (!pm_runtime_suspended(dev
)) {
826 ret
= clk_prepare_enable(rs
->apb_pclk
);
830 ret
= clk_prepare_enable(rs
->spiclk
);
832 clk_disable_unprepare(rs
->apb_pclk
);
837 ret
= spi_master_resume(rs
->master
);
839 clk_disable_unprepare(rs
->spiclk
);
840 clk_disable_unprepare(rs
->apb_pclk
);
845 #endif /* CONFIG_PM_SLEEP */
848 static int rockchip_spi_runtime_suspend(struct device
*dev
)
850 struct spi_master
*master
= dev_get_drvdata(dev
);
851 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
853 clk_disable_unprepare(rs
->spiclk
);
854 clk_disable_unprepare(rs
->apb_pclk
);
859 static int rockchip_spi_runtime_resume(struct device
*dev
)
862 struct spi_master
*master
= dev_get_drvdata(dev
);
863 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
865 ret
= clk_prepare_enable(rs
->apb_pclk
);
869 ret
= clk_prepare_enable(rs
->spiclk
);
871 clk_disable_unprepare(rs
->apb_pclk
);
875 #endif /* CONFIG_PM */
877 static const struct dev_pm_ops rockchip_spi_pm
= {
878 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend
, rockchip_spi_resume
)
879 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend
,
880 rockchip_spi_runtime_resume
, NULL
)
883 static const struct of_device_id rockchip_spi_dt_match
[] = {
884 { .compatible
= "rockchip,rk3066-spi", },
885 { .compatible
= "rockchip,rk3188-spi", },
886 { .compatible
= "rockchip,rk3288-spi", },
887 { .compatible
= "rockchip,rk3399-spi", },
890 MODULE_DEVICE_TABLE(of
, rockchip_spi_dt_match
);
892 static struct platform_driver rockchip_spi_driver
= {
895 .pm
= &rockchip_spi_pm
,
896 .of_match_table
= of_match_ptr(rockchip_spi_dt_match
),
898 .probe
= rockchip_spi_probe
,
899 .remove
= rockchip_spi_remove
,
902 module_platform_driver(rockchip_spi_driver
);
904 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
905 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
906 MODULE_LICENSE("GPL v2");