2 * SuperH HSPI bus driver
4 * Copyright (C) 2011 Kuninori Morimoto
7 * Based on pxa2xx_spi.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <linux/clk.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/timer.h>
30 #include <linux/delay.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/sh_hspi.h>
51 struct spi_master
*master
;
59 static void hspi_write(struct hspi_priv
*hspi
, int reg
, u32 val
)
61 iowrite32(val
, hspi
->addr
+ reg
);
64 static u32
hspi_read(struct hspi_priv
*hspi
, int reg
)
66 return ioread32(hspi
->addr
+ reg
);
69 static void hspi_bit_set(struct hspi_priv
*hspi
, int reg
, u32 mask
, u32 set
)
71 u32 val
= hspi_read(hspi
, reg
);
76 hspi_write(hspi
, reg
, val
);
82 static int hspi_status_check_timeout(struct hspi_priv
*hspi
, u32 mask
, u32 val
)
87 if ((mask
& hspi_read(hspi
, SPSR
)) == val
)
93 dev_err(hspi
->dev
, "timeout\n");
101 #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
102 #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
103 static void hspi_hw_cs_ctrl(struct hspi_priv
*hspi
, int hi
)
105 hspi_bit_set(hspi
, SPSCR
, (1 << 6), (hi
) << 6);
108 static void hspi_hw_setup(struct hspi_priv
*hspi
,
109 struct spi_message
*msg
,
110 struct spi_transfer
*t
)
112 struct spi_device
*spi
= msg
->spi
;
113 struct device
*dev
= hspi
->dev
;
115 u32 rate
, best_rate
, min
, tmp
;
118 * find best IDIV/CLKCx settings
123 for (idiv_clk
= 0x00; idiv_clk
<= 0x3F; idiv_clk
++) {
124 rate
= clk_get_rate(hspi
->clk
);
126 /* IDIV calculation */
127 if (idiv_clk
& (1 << 5))
132 /* CLKCx calculation */
133 rate
/= (((idiv_clk
& 0x1F) + 1) * 2);
135 /* save best settings */
136 tmp
= abs(t
->speed_hz
- rate
);
144 if (spi
->mode
& SPI_CPHA
)
146 if (spi
->mode
& SPI_CPOL
)
149 dev_dbg(dev
, "speed %d/%d\n", t
->speed_hz
, best_rate
);
151 hspi_write(hspi
, SPCR
, spcr
);
152 hspi_write(hspi
, SPSR
, 0x0);
153 hspi_write(hspi
, SPSCR
, 0x21); /* master mode / CS control */
156 static int hspi_transfer_one_message(struct spi_master
*master
,
157 struct spi_message
*msg
)
159 struct hspi_priv
*hspi
= spi_master_get_devdata(master
);
160 struct spi_transfer
*t
;
164 unsigned int cs_change
;
165 const int nsecs
= 50;
167 dev_dbg(hspi
->dev
, "%s\n", __func__
);
171 list_for_each_entry(t
, &msg
->transfers
, transfer_list
) {
174 hspi_hw_setup(hspi
, msg
, t
);
175 hspi_hw_cs_enable(hspi
);
178 cs_change
= t
->cs_change
;
180 for (i
= 0; i
< t
->len
; i
++) {
183 ret
= hspi_status_check_timeout(hspi
, 0x1, 0);
189 tx
= (u32
)((u8
*)t
->tx_buf
)[i
];
191 hspi_write(hspi
, SPTBR
, tx
);
194 ret
= hspi_status_check_timeout(hspi
, 0x4, 0x4);
198 rx
= hspi_read(hspi
, SPRBR
);
200 ((u8
*)t
->rx_buf
)[i
] = (u8
)rx
;
204 msg
->actual_length
+= t
->len
;
207 udelay(t
->delay_usecs
);
211 hspi_hw_cs_disable(hspi
);
219 hspi_hw_cs_disable(hspi
);
221 spi_finalize_current_message(master
);
226 static int hspi_probe(struct platform_device
*pdev
)
228 struct resource
*res
;
229 struct spi_master
*master
;
230 struct hspi_priv
*hspi
;
235 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
237 dev_err(&pdev
->dev
, "invalid resource\n");
241 master
= spi_alloc_master(&pdev
->dev
, sizeof(*hspi
));
243 dev_err(&pdev
->dev
, "spi_alloc_master error.\n");
247 clk
= clk_get(&pdev
->dev
, NULL
);
249 dev_err(&pdev
->dev
, "couldn't get clock\n");
254 hspi
= spi_master_get_devdata(master
);
255 platform_set_drvdata(pdev
, hspi
);
258 hspi
->master
= master
;
259 hspi
->dev
= &pdev
->dev
;
261 hspi
->addr
= devm_ioremap(hspi
->dev
,
262 res
->start
, resource_size(res
));
264 dev_err(&pdev
->dev
, "ioremap error.\n");
269 pm_runtime_enable(&pdev
->dev
);
271 master
->bus_num
= pdev
->id
;
272 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
;
273 master
->dev
.of_node
= pdev
->dev
.of_node
;
274 master
->auto_runtime_pm
= true;
275 master
->transfer_one_message
= hspi_transfer_one_message
;
276 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
278 ret
= devm_spi_register_master(&pdev
->dev
, master
);
280 dev_err(&pdev
->dev
, "spi_register_master error.\n");
287 pm_runtime_disable(&pdev
->dev
);
291 spi_master_put(master
);
296 static int hspi_remove(struct platform_device
*pdev
)
298 struct hspi_priv
*hspi
= platform_get_drvdata(pdev
);
300 pm_runtime_disable(&pdev
->dev
);
307 static struct of_device_id hspi_of_match
[] = {
308 { .compatible
= "renesas,hspi", },
311 MODULE_DEVICE_TABLE(of
, hspi_of_match
);
313 static struct platform_driver hspi_driver
= {
315 .remove
= hspi_remove
,
318 .owner
= THIS_MODULE
,
319 .of_match_table
= hspi_of_match
,
322 module_platform_driver(hspi_driver
);
324 MODULE_DESCRIPTION("SuperH HSPI bus driver");
325 MODULE_LICENSE("GPL");
326 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
327 MODULE_ALIAS("platform:sh-hspi");