2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/clk/tegra.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dmaengine.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmapool.h>
26 #include <linux/err.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
30 #include <linux/kernel.h>
31 #include <linux/kthread.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
37 #include <linux/spi/spi.h>
39 #define SPI_COMMAND1 0x000
40 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
41 #define SPI_PACKED (1 << 5)
42 #define SPI_TX_EN (1 << 11)
43 #define SPI_RX_EN (1 << 12)
44 #define SPI_BOTH_EN_BYTE (1 << 13)
45 #define SPI_BOTH_EN_BIT (1 << 14)
46 #define SPI_LSBYTE_FE (1 << 15)
47 #define SPI_LSBIT_FE (1 << 16)
48 #define SPI_BIDIROE (1 << 17)
49 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
50 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
51 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
52 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
53 #define SPI_IDLE_SDA_MASK (3 << 18)
54 #define SPI_CS_SS_VAL (1 << 20)
55 #define SPI_CS_SW_HW (1 << 21)
56 /* SPI_CS_POL_INACTIVE bits are default high */
57 #define SPI_CS_POL_INACTIVE 22
58 #define SPI_CS_POL_INACTIVE_0 (1 << 22)
59 #define SPI_CS_POL_INACTIVE_1 (1 << 23)
60 #define SPI_CS_POL_INACTIVE_2 (1 << 24)
61 #define SPI_CS_POL_INACTIVE_3 (1 << 25)
62 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
64 #define SPI_CS_SEL_0 (0 << 26)
65 #define SPI_CS_SEL_1 (1 << 26)
66 #define SPI_CS_SEL_2 (2 << 26)
67 #define SPI_CS_SEL_3 (3 << 26)
68 #define SPI_CS_SEL_MASK (3 << 26)
69 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
70 #define SPI_CONTROL_MODE_0 (0 << 28)
71 #define SPI_CONTROL_MODE_1 (1 << 28)
72 #define SPI_CONTROL_MODE_2 (2 << 28)
73 #define SPI_CONTROL_MODE_3 (3 << 28)
74 #define SPI_CONTROL_MODE_MASK (3 << 28)
75 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
76 #define SPI_M_S (1 << 30)
77 #define SPI_PIO (1 << 31)
79 #define SPI_COMMAND2 0x004
80 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
81 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
83 #define SPI_CS_TIMING1 0x008
84 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
85 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
86 ((((val) & 0xFFu) << ((cs) * 8)) | \
87 ((reg) & ~(0xFFu << ((cs) * 8))))
89 #define SPI_CS_TIMING2 0x00C
90 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
91 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
92 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
93 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
94 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
95 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
96 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
97 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
98 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
99 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
100 ((reg) & ~(1 << ((cs) * 8 + 5))))
101 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
102 (reg = (((val) & 0xF) << ((cs) * 8)) | \
103 ((reg) & ~(0xF << ((cs) * 8))))
105 #define SPI_TRANS_STATUS 0x010
106 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
107 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
108 #define SPI_RDY (1 << 30)
110 #define SPI_FIFO_STATUS 0x014
111 #define SPI_RX_FIFO_EMPTY (1 << 0)
112 #define SPI_RX_FIFO_FULL (1 << 1)
113 #define SPI_TX_FIFO_EMPTY (1 << 2)
114 #define SPI_TX_FIFO_FULL (1 << 3)
115 #define SPI_RX_FIFO_UNF (1 << 4)
116 #define SPI_RX_FIFO_OVF (1 << 5)
117 #define SPI_TX_FIFO_UNF (1 << 6)
118 #define SPI_TX_FIFO_OVF (1 << 7)
119 #define SPI_ERR (1 << 8)
120 #define SPI_TX_FIFO_FLUSH (1 << 14)
121 #define SPI_RX_FIFO_FLUSH (1 << 15)
122 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
123 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
124 #define SPI_FRAME_END (1 << 30)
125 #define SPI_CS_INACTIVE (1 << 31)
127 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
128 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
129 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
131 #define SPI_TX_DATA 0x018
132 #define SPI_RX_DATA 0x01C
134 #define SPI_DMA_CTL 0x020
135 #define SPI_TX_TRIG_1 (0 << 15)
136 #define SPI_TX_TRIG_4 (1 << 15)
137 #define SPI_TX_TRIG_8 (2 << 15)
138 #define SPI_TX_TRIG_16 (3 << 15)
139 #define SPI_TX_TRIG_MASK (3 << 15)
140 #define SPI_RX_TRIG_1 (0 << 19)
141 #define SPI_RX_TRIG_4 (1 << 19)
142 #define SPI_RX_TRIG_8 (2 << 19)
143 #define SPI_RX_TRIG_16 (3 << 19)
144 #define SPI_RX_TRIG_MASK (3 << 19)
145 #define SPI_IE_TX (1 << 28)
146 #define SPI_IE_RX (1 << 29)
147 #define SPI_CONT (1 << 30)
148 #define SPI_DMA (1 << 31)
149 #define SPI_DMA_EN SPI_DMA
151 #define SPI_DMA_BLK 0x024
152 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
154 #define SPI_TX_FIFO 0x108
155 #define SPI_RX_FIFO 0x188
156 #define MAX_CHIP_SELECT 4
157 #define SPI_FIFO_DEPTH 64
158 #define DATA_DIR_TX (1 << 0)
159 #define DATA_DIR_RX (1 << 1)
161 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
162 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
163 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
164 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
165 #define MAX_HOLD_CYCLES 16
166 #define SPI_DEFAULT_SPEED 25000000
168 #define MAX_CHIP_SELECT 4
169 #define SPI_FIFO_DEPTH 64
171 struct tegra_spi_data
{
173 struct spi_master
*master
;
181 u32 spi_max_frequency
;
184 struct spi_device
*cur_spi
;
185 struct spi_device
*cs_control
;
188 unsigned words_per_32bit
;
189 unsigned bytes_per_word
;
190 unsigned curr_dma_words
;
191 unsigned cur_direction
;
196 unsigned dma_buf_size
;
197 unsigned max_buf_size
;
198 bool is_curr_dma_xfer
;
200 struct completion rx_dma_complete
;
201 struct completion tx_dma_complete
;
207 unsigned long packed_size
;
211 u32 def_command1_reg
;
214 struct completion xfer_completion
;
215 struct spi_transfer
*curr_xfer
;
216 struct dma_chan
*rx_dma_chan
;
218 dma_addr_t rx_dma_phys
;
219 struct dma_async_tx_descriptor
*rx_dma_desc
;
221 struct dma_chan
*tx_dma_chan
;
223 dma_addr_t tx_dma_phys
;
224 struct dma_async_tx_descriptor
*tx_dma_desc
;
227 static int tegra_spi_runtime_suspend(struct device
*dev
);
228 static int tegra_spi_runtime_resume(struct device
*dev
);
230 static inline unsigned long tegra_spi_readl(struct tegra_spi_data
*tspi
,
233 return readl(tspi
->base
+ reg
);
236 static inline void tegra_spi_writel(struct tegra_spi_data
*tspi
,
237 unsigned long val
, unsigned long reg
)
239 writel(val
, tspi
->base
+ reg
);
241 /* Read back register to make sure that register writes completed */
242 if (reg
!= SPI_TX_FIFO
)
243 readl(tspi
->base
+ SPI_COMMAND1
);
246 static void tegra_spi_clear_status(struct tegra_spi_data
*tspi
)
250 /* Write 1 to clear status register */
251 val
= tegra_spi_readl(tspi
, SPI_TRANS_STATUS
);
252 tegra_spi_writel(tspi
, val
, SPI_TRANS_STATUS
);
254 /* Clear fifo status error if any */
255 val
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
257 tegra_spi_writel(tspi
, SPI_ERR
| SPI_FIFO_ERROR
,
261 static unsigned tegra_spi_calculate_curr_xfer_param(
262 struct spi_device
*spi
, struct tegra_spi_data
*tspi
,
263 struct spi_transfer
*t
)
265 unsigned remain_len
= t
->len
- tspi
->cur_pos
;
267 unsigned bits_per_word
= t
->bits_per_word
;
269 unsigned total_fifo_words
;
271 tspi
->bytes_per_word
= DIV_ROUND_UP(bits_per_word
, 8);
273 if (bits_per_word
== 8 || bits_per_word
== 16) {
275 tspi
->words_per_32bit
= 32/bits_per_word
;
278 tspi
->words_per_32bit
= 1;
281 if (tspi
->is_packed
) {
282 max_len
= min(remain_len
, tspi
->max_buf_size
);
283 tspi
->curr_dma_words
= max_len
/tspi
->bytes_per_word
;
284 total_fifo_words
= (max_len
+ 3) / 4;
286 max_word
= (remain_len
- 1) / tspi
->bytes_per_word
+ 1;
287 max_word
= min(max_word
, tspi
->max_buf_size
/4);
288 tspi
->curr_dma_words
= max_word
;
289 total_fifo_words
= max_word
;
291 return total_fifo_words
;
294 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
295 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
298 unsigned tx_empty_count
;
299 unsigned long fifo_status
;
300 unsigned max_n_32bit
;
303 unsigned int written_words
;
304 unsigned fifo_words_left
;
305 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
307 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
308 tx_empty_count
= SPI_TX_FIFO_EMPTY_COUNT(fifo_status
);
310 if (tspi
->is_packed
) {
311 fifo_words_left
= tx_empty_count
* tspi
->words_per_32bit
;
312 written_words
= min(fifo_words_left
, tspi
->curr_dma_words
);
313 nbytes
= written_words
* tspi
->bytes_per_word
;
314 max_n_32bit
= DIV_ROUND_UP(nbytes
, 4);
315 for (count
= 0; count
< max_n_32bit
; count
++) {
317 for (i
= 0; (i
< 4) && nbytes
; i
++, nbytes
--)
318 x
|= (*tx_buf
++) << (i
*8);
319 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
322 max_n_32bit
= min(tspi
->curr_dma_words
, tx_empty_count
);
323 written_words
= max_n_32bit
;
324 nbytes
= written_words
* tspi
->bytes_per_word
;
325 for (count
= 0; count
< max_n_32bit
; count
++) {
327 for (i
= 0; nbytes
&& (i
< tspi
->bytes_per_word
);
329 x
|= ((*tx_buf
++) << i
*8);
330 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
333 tspi
->cur_tx_pos
+= written_words
* tspi
->bytes_per_word
;
334 return written_words
;
337 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
338 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
340 unsigned rx_full_count
;
341 unsigned long fifo_status
;
344 unsigned int read_words
= 0;
346 u8
*rx_buf
= (u8
*)t
->rx_buf
+ tspi
->cur_rx_pos
;
348 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
349 rx_full_count
= SPI_RX_FIFO_FULL_COUNT(fifo_status
);
350 if (tspi
->is_packed
) {
351 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
352 for (count
= 0; count
< rx_full_count
; count
++) {
353 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
);
354 for (i
= 0; len
&& (i
< 4); i
++, len
--)
355 *rx_buf
++ = (x
>> i
*8) & 0xFF;
357 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
358 read_words
+= tspi
->curr_dma_words
;
360 unsigned int rx_mask
;
361 unsigned int bits_per_word
= t
->bits_per_word
;
363 rx_mask
= (1 << bits_per_word
) - 1;
364 for (count
= 0; count
< rx_full_count
; count
++) {
365 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
);
367 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
368 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
370 tspi
->cur_rx_pos
+= rx_full_count
* tspi
->bytes_per_word
;
371 read_words
+= rx_full_count
;
376 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
377 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
381 /* Make the dma buffer to read by cpu */
382 dma_sync_single_for_cpu(tspi
->dev
, tspi
->tx_dma_phys
,
383 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
385 if (tspi
->is_packed
) {
386 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
387 memcpy(tspi
->tx_dma_buf
, t
->tx_buf
+ tspi
->cur_pos
, len
);
391 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
392 unsigned consume
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
395 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
397 for (i
= 0; consume
&& (i
< tspi
->bytes_per_word
);
399 x
|= ((*tx_buf
++) << i
* 8);
400 tspi
->tx_dma_buf
[count
] = x
;
403 tspi
->cur_tx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
405 /* Make the dma buffer to read by dma */
406 dma_sync_single_for_device(tspi
->dev
, tspi
->tx_dma_phys
,
407 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
410 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
411 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
415 /* Make the dma buffer to read by cpu */
416 dma_sync_single_for_cpu(tspi
->dev
, tspi
->rx_dma_phys
,
417 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
419 if (tspi
->is_packed
) {
420 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
421 memcpy(t
->rx_buf
+ tspi
->cur_rx_pos
, tspi
->rx_dma_buf
, len
);
425 unsigned char *rx_buf
= t
->rx_buf
+ tspi
->cur_rx_pos
;
427 unsigned int rx_mask
;
428 unsigned int bits_per_word
= t
->bits_per_word
;
430 rx_mask
= (1 << bits_per_word
) - 1;
431 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
432 x
= tspi
->rx_dma_buf
[count
];
434 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
435 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
438 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
440 /* Make the dma buffer to read by dma */
441 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
442 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
445 static void tegra_spi_dma_complete(void *args
)
447 struct completion
*dma_complete
= args
;
449 complete(dma_complete
);
452 static int tegra_spi_start_tx_dma(struct tegra_spi_data
*tspi
, int len
)
454 reinit_completion(&tspi
->tx_dma_complete
);
455 tspi
->tx_dma_desc
= dmaengine_prep_slave_single(tspi
->tx_dma_chan
,
456 tspi
->tx_dma_phys
, len
, DMA_MEM_TO_DEV
,
457 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
458 if (!tspi
->tx_dma_desc
) {
459 dev_err(tspi
->dev
, "Not able to get desc for Tx\n");
463 tspi
->tx_dma_desc
->callback
= tegra_spi_dma_complete
;
464 tspi
->tx_dma_desc
->callback_param
= &tspi
->tx_dma_complete
;
466 dmaengine_submit(tspi
->tx_dma_desc
);
467 dma_async_issue_pending(tspi
->tx_dma_chan
);
471 static int tegra_spi_start_rx_dma(struct tegra_spi_data
*tspi
, int len
)
473 reinit_completion(&tspi
->rx_dma_complete
);
474 tspi
->rx_dma_desc
= dmaengine_prep_slave_single(tspi
->rx_dma_chan
,
475 tspi
->rx_dma_phys
, len
, DMA_DEV_TO_MEM
,
476 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
477 if (!tspi
->rx_dma_desc
) {
478 dev_err(tspi
->dev
, "Not able to get desc for Rx\n");
482 tspi
->rx_dma_desc
->callback
= tegra_spi_dma_complete
;
483 tspi
->rx_dma_desc
->callback_param
= &tspi
->rx_dma_complete
;
485 dmaengine_submit(tspi
->rx_dma_desc
);
486 dma_async_issue_pending(tspi
->rx_dma_chan
);
490 static int tegra_spi_start_dma_based_transfer(
491 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
496 unsigned long status
;
498 /* Make sure that Rx and Tx fifo are empty */
499 status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
500 if ((status
& SPI_FIFO_EMPTY
) != SPI_FIFO_EMPTY
) {
502 "Rx/Tx fifo are not empty status 0x%08lx\n", status
);
506 val
= SPI_DMA_BLK_SET(tspi
->curr_dma_words
- 1);
507 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
510 len
= DIV_ROUND_UP(tspi
->curr_dma_words
* tspi
->bytes_per_word
,
513 len
= tspi
->curr_dma_words
* 4;
515 /* Set attention level based on length of transfer */
517 val
|= SPI_TX_TRIG_1
| SPI_RX_TRIG_1
;
518 else if (((len
) >> 4) & 0x1)
519 val
|= SPI_TX_TRIG_4
| SPI_RX_TRIG_4
;
521 val
|= SPI_TX_TRIG_8
| SPI_RX_TRIG_8
;
523 if (tspi
->cur_direction
& DATA_DIR_TX
)
526 if (tspi
->cur_direction
& DATA_DIR_RX
)
529 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
530 tspi
->dma_control_reg
= val
;
532 if (tspi
->cur_direction
& DATA_DIR_TX
) {
533 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi
, t
);
534 ret
= tegra_spi_start_tx_dma(tspi
, len
);
537 "Starting tx dma failed, err %d\n", ret
);
542 if (tspi
->cur_direction
& DATA_DIR_RX
) {
543 /* Make the dma buffer to read by dma */
544 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
545 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
547 ret
= tegra_spi_start_rx_dma(tspi
, len
);
550 "Starting rx dma failed, err %d\n", ret
);
551 if (tspi
->cur_direction
& DATA_DIR_TX
)
552 dmaengine_terminate_all(tspi
->tx_dma_chan
);
556 tspi
->is_curr_dma_xfer
= true;
557 tspi
->dma_control_reg
= val
;
560 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
564 static int tegra_spi_start_cpu_based_transfer(
565 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
570 if (tspi
->cur_direction
& DATA_DIR_TX
)
571 cur_words
= tegra_spi_fill_tx_fifo_from_client_txbuf(tspi
, t
);
573 cur_words
= tspi
->curr_dma_words
;
575 val
= SPI_DMA_BLK_SET(cur_words
- 1);
576 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
579 if (tspi
->cur_direction
& DATA_DIR_TX
)
582 if (tspi
->cur_direction
& DATA_DIR_RX
)
585 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
586 tspi
->dma_control_reg
= val
;
588 tspi
->is_curr_dma_xfer
= false;
591 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
595 static int tegra_spi_init_dma_param(struct tegra_spi_data
*tspi
,
598 struct dma_chan
*dma_chan
;
602 struct dma_slave_config dma_sconfig
;
606 dma_cap_set(DMA_SLAVE
, mask
);
607 dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
610 "Dma channel is not available, will try later\n");
611 return -EPROBE_DEFER
;
614 dma_buf
= dma_alloc_coherent(tspi
->dev
, tspi
->dma_buf_size
,
615 &dma_phys
, GFP_KERNEL
);
617 dev_err(tspi
->dev
, " Not able to allocate the dma buffer\n");
618 dma_release_channel(dma_chan
);
622 dma_sconfig
.slave_id
= tspi
->dma_req_sel
;
624 dma_sconfig
.src_addr
= tspi
->phys
+ SPI_RX_FIFO
;
625 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
626 dma_sconfig
.src_maxburst
= 0;
628 dma_sconfig
.dst_addr
= tspi
->phys
+ SPI_TX_FIFO
;
629 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
630 dma_sconfig
.dst_maxburst
= 0;
633 ret
= dmaengine_slave_config(dma_chan
, &dma_sconfig
);
637 tspi
->rx_dma_chan
= dma_chan
;
638 tspi
->rx_dma_buf
= dma_buf
;
639 tspi
->rx_dma_phys
= dma_phys
;
641 tspi
->tx_dma_chan
= dma_chan
;
642 tspi
->tx_dma_buf
= dma_buf
;
643 tspi
->tx_dma_phys
= dma_phys
;
648 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
649 dma_release_channel(dma_chan
);
653 static void tegra_spi_deinit_dma_param(struct tegra_spi_data
*tspi
,
658 struct dma_chan
*dma_chan
;
661 dma_buf
= tspi
->rx_dma_buf
;
662 dma_chan
= tspi
->rx_dma_chan
;
663 dma_phys
= tspi
->rx_dma_phys
;
664 tspi
->rx_dma_chan
= NULL
;
665 tspi
->rx_dma_buf
= NULL
;
667 dma_buf
= tspi
->tx_dma_buf
;
668 dma_chan
= tspi
->tx_dma_chan
;
669 dma_phys
= tspi
->tx_dma_phys
;
670 tspi
->tx_dma_buf
= NULL
;
671 tspi
->tx_dma_chan
= NULL
;
676 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
677 dma_release_channel(dma_chan
);
680 static unsigned long tegra_spi_setup_transfer_one(struct spi_device
*spi
,
681 struct spi_transfer
*t
, bool is_first_of_msg
)
683 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
684 u32 speed
= t
->speed_hz
;
685 u8 bits_per_word
= t
->bits_per_word
;
686 unsigned long command1
;
689 if (speed
!= tspi
->cur_speed
) {
690 clk_set_rate(tspi
->clk
, speed
);
691 tspi
->cur_speed
= speed
;
696 tspi
->cur_rx_pos
= 0;
697 tspi
->cur_tx_pos
= 0;
700 if (is_first_of_msg
) {
701 tegra_spi_clear_status(tspi
);
703 command1
= tspi
->def_command1_reg
;
704 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
706 command1
&= ~SPI_CONTROL_MODE_MASK
;
707 req_mode
= spi
->mode
& 0x3;
708 if (req_mode
== SPI_MODE_0
)
709 command1
|= SPI_CONTROL_MODE_0
;
710 else if (req_mode
== SPI_MODE_1
)
711 command1
|= SPI_CONTROL_MODE_1
;
712 else if (req_mode
== SPI_MODE_2
)
713 command1
|= SPI_CONTROL_MODE_2
;
714 else if (req_mode
== SPI_MODE_3
)
715 command1
|= SPI_CONTROL_MODE_3
;
717 if (tspi
->cs_control
) {
718 if (tspi
->cs_control
!= spi
)
719 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
720 tspi
->cs_control
= NULL
;
722 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
724 command1
|= SPI_CS_SW_HW
;
725 if (spi
->mode
& SPI_CS_HIGH
)
726 command1
|= SPI_CS_SS_VAL
;
728 command1
&= ~SPI_CS_SS_VAL
;
730 tegra_spi_writel(tspi
, 0, SPI_COMMAND2
);
732 command1
= tspi
->command1_reg
;
733 command1
&= ~SPI_BIT_LENGTH(~0);
734 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
740 static int tegra_spi_start_transfer_one(struct spi_device
*spi
,
741 struct spi_transfer
*t
, unsigned long command1
)
743 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
744 unsigned total_fifo_words
;
747 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(spi
, tspi
, t
);
750 command1
|= SPI_PACKED
;
752 command1
&= ~(SPI_CS_SEL_MASK
| SPI_TX_EN
| SPI_RX_EN
);
753 tspi
->cur_direction
= 0;
755 command1
|= SPI_RX_EN
;
756 tspi
->cur_direction
|= DATA_DIR_RX
;
759 command1
|= SPI_TX_EN
;
760 tspi
->cur_direction
|= DATA_DIR_TX
;
762 command1
|= SPI_CS_SEL(spi
->chip_select
);
763 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
764 tspi
->command1_reg
= command1
;
766 dev_dbg(tspi
->dev
, "The def 0x%x and written 0x%lx\n",
767 tspi
->def_command1_reg
, command1
);
769 if (total_fifo_words
> SPI_FIFO_DEPTH
)
770 ret
= tegra_spi_start_dma_based_transfer(tspi
, t
);
772 ret
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
776 static int tegra_spi_setup(struct spi_device
*spi
)
778 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
782 unsigned int cs_pol_bit
[MAX_CHIP_SELECT
] = {
783 SPI_CS_POL_INACTIVE_0
,
784 SPI_CS_POL_INACTIVE_1
,
785 SPI_CS_POL_INACTIVE_2
,
786 SPI_CS_POL_INACTIVE_3
,
789 dev_dbg(&spi
->dev
, "setup %d bpw, %scpol, %scpha, %dHz\n",
791 spi
->mode
& SPI_CPOL
? "" : "~",
792 spi
->mode
& SPI_CPHA
? "" : "~",
795 BUG_ON(spi
->chip_select
>= MAX_CHIP_SELECT
);
797 /* Set speed to the spi max fequency if spi device has not set */
798 spi
->max_speed_hz
= spi
->max_speed_hz
? : tspi
->spi_max_frequency
;
800 ret
= pm_runtime_get_sync(tspi
->dev
);
802 dev_err(tspi
->dev
, "pm runtime failed, e = %d\n", ret
);
806 spin_lock_irqsave(&tspi
->lock
, flags
);
807 val
= tspi
->def_command1_reg
;
808 if (spi
->mode
& SPI_CS_HIGH
)
809 val
&= ~cs_pol_bit
[spi
->chip_select
];
811 val
|= cs_pol_bit
[spi
->chip_select
];
812 tspi
->def_command1_reg
= val
;
813 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
814 spin_unlock_irqrestore(&tspi
->lock
, flags
);
816 pm_runtime_put(tspi
->dev
);
820 static void tegra_spi_transfer_delay(int delay
)
826 mdelay(delay
/ 1000);
828 udelay(delay
% 1000);
831 static int tegra_spi_transfer_one_message(struct spi_master
*master
,
832 struct spi_message
*msg
)
834 bool is_first_msg
= true;
835 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
836 struct spi_transfer
*xfer
;
837 struct spi_device
*spi
= msg
->spi
;
842 msg
->actual_length
= 0;
844 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
847 reinit_completion(&tspi
->xfer_completion
);
849 cmd1
= tegra_spi_setup_transfer_one(spi
, xfer
, is_first_msg
);
857 ret
= tegra_spi_start_transfer_one(spi
, xfer
, cmd1
);
860 "spi can not start transfer, err %d\n", ret
);
864 is_first_msg
= false;
865 ret
= wait_for_completion_timeout(&tspi
->xfer_completion
,
867 if (WARN_ON(ret
== 0)) {
869 "spi trasfer timeout, err %d\n", ret
);
874 if (tspi
->tx_status
|| tspi
->rx_status
) {
875 dev_err(tspi
->dev
, "Error in Transfer\n");
879 msg
->actual_length
+= xfer
->len
;
882 if (ret
< 0 || skip
) {
883 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
885 tegra_spi_transfer_delay(xfer
->delay_usecs
);
887 } else if (msg
->transfers
.prev
== &xfer
->transfer_list
) {
888 /* This is the last transfer in message */
890 tspi
->cs_control
= spi
;
892 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
894 tegra_spi_transfer_delay(xfer
->delay_usecs
);
896 } else if (xfer
->cs_change
) {
897 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
899 tegra_spi_transfer_delay(xfer
->delay_usecs
);
906 spi_finalize_current_message(master
);
910 static irqreturn_t
handle_cpu_based_xfer(struct tegra_spi_data
*tspi
)
912 struct spi_transfer
*t
= tspi
->curr_xfer
;
915 spin_lock_irqsave(&tspi
->lock
, flags
);
916 if (tspi
->tx_status
|| tspi
->rx_status
) {
917 dev_err(tspi
->dev
, "CpuXfer ERROR bit set 0x%x\n",
919 dev_err(tspi
->dev
, "CpuXfer 0x%08x:0x%08x\n",
920 tspi
->command1_reg
, tspi
->dma_control_reg
);
921 tegra_periph_reset_assert(tspi
->clk
);
923 tegra_periph_reset_deassert(tspi
->clk
);
924 complete(&tspi
->xfer_completion
);
928 if (tspi
->cur_direction
& DATA_DIR_RX
)
929 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi
, t
);
931 if (tspi
->cur_direction
& DATA_DIR_TX
)
932 tspi
->cur_pos
= tspi
->cur_tx_pos
;
934 tspi
->cur_pos
= tspi
->cur_rx_pos
;
936 if (tspi
->cur_pos
== t
->len
) {
937 complete(&tspi
->xfer_completion
);
941 tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
, tspi
, t
);
942 tegra_spi_start_cpu_based_transfer(tspi
, t
);
944 spin_unlock_irqrestore(&tspi
->lock
, flags
);
948 static irqreturn_t
handle_dma_based_xfer(struct tegra_spi_data
*tspi
)
950 struct spi_transfer
*t
= tspi
->curr_xfer
;
953 unsigned total_fifo_words
;
956 /* Abort dmas if any error */
957 if (tspi
->cur_direction
& DATA_DIR_TX
) {
958 if (tspi
->tx_status
) {
959 dmaengine_terminate_all(tspi
->tx_dma_chan
);
962 wait_status
= wait_for_completion_interruptible_timeout(
963 &tspi
->tx_dma_complete
, SPI_DMA_TIMEOUT
);
964 if (wait_status
<= 0) {
965 dmaengine_terminate_all(tspi
->tx_dma_chan
);
966 dev_err(tspi
->dev
, "TxDma Xfer failed\n");
972 if (tspi
->cur_direction
& DATA_DIR_RX
) {
973 if (tspi
->rx_status
) {
974 dmaengine_terminate_all(tspi
->rx_dma_chan
);
977 wait_status
= wait_for_completion_interruptible_timeout(
978 &tspi
->rx_dma_complete
, SPI_DMA_TIMEOUT
);
979 if (wait_status
<= 0) {
980 dmaengine_terminate_all(tspi
->rx_dma_chan
);
981 dev_err(tspi
->dev
, "RxDma Xfer failed\n");
987 spin_lock_irqsave(&tspi
->lock
, flags
);
989 dev_err(tspi
->dev
, "DmaXfer: ERROR bit set 0x%x\n",
991 dev_err(tspi
->dev
, "DmaXfer 0x%08x:0x%08x\n",
992 tspi
->command1_reg
, tspi
->dma_control_reg
);
993 tegra_periph_reset_assert(tspi
->clk
);
995 tegra_periph_reset_deassert(tspi
->clk
);
996 complete(&tspi
->xfer_completion
);
997 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1001 if (tspi
->cur_direction
& DATA_DIR_RX
)
1002 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi
, t
);
1004 if (tspi
->cur_direction
& DATA_DIR_TX
)
1005 tspi
->cur_pos
= tspi
->cur_tx_pos
;
1007 tspi
->cur_pos
= tspi
->cur_rx_pos
;
1009 if (tspi
->cur_pos
== t
->len
) {
1010 complete(&tspi
->xfer_completion
);
1014 /* Continue transfer in current message */
1015 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
,
1017 if (total_fifo_words
> SPI_FIFO_DEPTH
)
1018 err
= tegra_spi_start_dma_based_transfer(tspi
, t
);
1020 err
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
1023 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1027 static irqreturn_t
tegra_spi_isr_thread(int irq
, void *context_data
)
1029 struct tegra_spi_data
*tspi
= context_data
;
1031 if (!tspi
->is_curr_dma_xfer
)
1032 return handle_cpu_based_xfer(tspi
);
1033 return handle_dma_based_xfer(tspi
);
1036 static irqreturn_t
tegra_spi_isr(int irq
, void *context_data
)
1038 struct tegra_spi_data
*tspi
= context_data
;
1040 tspi
->status_reg
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
1041 if (tspi
->cur_direction
& DATA_DIR_TX
)
1042 tspi
->tx_status
= tspi
->status_reg
&
1043 (SPI_TX_FIFO_UNF
| SPI_TX_FIFO_OVF
);
1045 if (tspi
->cur_direction
& DATA_DIR_RX
)
1046 tspi
->rx_status
= tspi
->status_reg
&
1047 (SPI_RX_FIFO_OVF
| SPI_RX_FIFO_UNF
);
1048 tegra_spi_clear_status(tspi
);
1050 return IRQ_WAKE_THREAD
;
1053 static void tegra_spi_parse_dt(struct platform_device
*pdev
,
1054 struct tegra_spi_data
*tspi
)
1056 struct device_node
*np
= pdev
->dev
.of_node
;
1059 if (of_property_read_u32_array(np
, "nvidia,dma-request-selector",
1061 tspi
->dma_req_sel
= of_dma
[1];
1063 if (of_property_read_u32(np
, "spi-max-frequency",
1064 &tspi
->spi_max_frequency
))
1065 tspi
->spi_max_frequency
= 25000000; /* 25MHz */
1068 static struct of_device_id tegra_spi_of_match
[] = {
1069 { .compatible
= "nvidia,tegra114-spi", },
1072 MODULE_DEVICE_TABLE(of
, tegra_spi_of_match
);
1074 static int tegra_spi_probe(struct platform_device
*pdev
)
1076 struct spi_master
*master
;
1077 struct tegra_spi_data
*tspi
;
1081 master
= spi_alloc_master(&pdev
->dev
, sizeof(*tspi
));
1083 dev_err(&pdev
->dev
, "master allocation failed\n");
1086 platform_set_drvdata(pdev
, master
);
1087 tspi
= spi_master_get_devdata(master
);
1090 tegra_spi_parse_dt(pdev
, tspi
);
1092 /* the spi->mode bits understood by this driver: */
1093 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1094 master
->setup
= tegra_spi_setup
;
1095 master
->transfer_one_message
= tegra_spi_transfer_one_message
;
1096 master
->num_chipselect
= MAX_CHIP_SELECT
;
1097 master
->bus_num
= -1;
1098 master
->auto_runtime_pm
= true;
1100 tspi
->master
= master
;
1101 tspi
->dev
= &pdev
->dev
;
1102 spin_lock_init(&tspi
->lock
);
1104 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1105 tspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1106 if (IS_ERR(tspi
->base
)) {
1107 ret
= PTR_ERR(tspi
->base
);
1108 goto exit_free_master
;
1110 tspi
->phys
= r
->start
;
1112 spi_irq
= platform_get_irq(pdev
, 0);
1113 tspi
->irq
= spi_irq
;
1114 ret
= request_threaded_irq(tspi
->irq
, tegra_spi_isr
,
1115 tegra_spi_isr_thread
, IRQF_ONESHOT
,
1116 dev_name(&pdev
->dev
), tspi
);
1118 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
1120 goto exit_free_master
;
1123 tspi
->clk
= devm_clk_get(&pdev
->dev
, "spi");
1124 if (IS_ERR(tspi
->clk
)) {
1125 dev_err(&pdev
->dev
, "can not get clock\n");
1126 ret
= PTR_ERR(tspi
->clk
);
1130 tspi
->max_buf_size
= SPI_FIFO_DEPTH
<< 2;
1131 tspi
->dma_buf_size
= DEFAULT_SPI_DMA_BUF_LEN
;
1133 if (tspi
->dma_req_sel
) {
1134 ret
= tegra_spi_init_dma_param(tspi
, true);
1136 dev_err(&pdev
->dev
, "RxDma Init failed, err %d\n", ret
);
1140 ret
= tegra_spi_init_dma_param(tspi
, false);
1142 dev_err(&pdev
->dev
, "TxDma Init failed, err %d\n", ret
);
1143 goto exit_rx_dma_free
;
1145 tspi
->max_buf_size
= tspi
->dma_buf_size
;
1146 init_completion(&tspi
->tx_dma_complete
);
1147 init_completion(&tspi
->rx_dma_complete
);
1150 init_completion(&tspi
->xfer_completion
);
1152 pm_runtime_enable(&pdev
->dev
);
1153 if (!pm_runtime_enabled(&pdev
->dev
)) {
1154 ret
= tegra_spi_runtime_resume(&pdev
->dev
);
1156 goto exit_pm_disable
;
1159 ret
= pm_runtime_get_sync(&pdev
->dev
);
1161 dev_err(&pdev
->dev
, "pm runtime get failed, e = %d\n", ret
);
1162 goto exit_pm_disable
;
1164 tspi
->def_command1_reg
= SPI_M_S
;
1165 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
1166 pm_runtime_put(&pdev
->dev
);
1168 master
->dev
.of_node
= pdev
->dev
.of_node
;
1169 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1171 dev_err(&pdev
->dev
, "can not register to master err %d\n", ret
);
1172 goto exit_pm_disable
;
1177 pm_runtime_disable(&pdev
->dev
);
1178 if (!pm_runtime_status_suspended(&pdev
->dev
))
1179 tegra_spi_runtime_suspend(&pdev
->dev
);
1180 tegra_spi_deinit_dma_param(tspi
, false);
1182 tegra_spi_deinit_dma_param(tspi
, true);
1184 free_irq(spi_irq
, tspi
);
1186 spi_master_put(master
);
1190 static int tegra_spi_remove(struct platform_device
*pdev
)
1192 struct spi_master
*master
= platform_get_drvdata(pdev
);
1193 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1195 free_irq(tspi
->irq
, tspi
);
1197 if (tspi
->tx_dma_chan
)
1198 tegra_spi_deinit_dma_param(tspi
, false);
1200 if (tspi
->rx_dma_chan
)
1201 tegra_spi_deinit_dma_param(tspi
, true);
1203 pm_runtime_disable(&pdev
->dev
);
1204 if (!pm_runtime_status_suspended(&pdev
->dev
))
1205 tegra_spi_runtime_suspend(&pdev
->dev
);
1210 #ifdef CONFIG_PM_SLEEP
1211 static int tegra_spi_suspend(struct device
*dev
)
1213 struct spi_master
*master
= dev_get_drvdata(dev
);
1215 return spi_master_suspend(master
);
1218 static int tegra_spi_resume(struct device
*dev
)
1220 struct spi_master
*master
= dev_get_drvdata(dev
);
1221 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1224 ret
= pm_runtime_get_sync(dev
);
1226 dev_err(dev
, "pm runtime failed, e = %d\n", ret
);
1229 tegra_spi_writel(tspi
, tspi
->command1_reg
, SPI_COMMAND1
);
1230 pm_runtime_put(dev
);
1232 return spi_master_resume(master
);
1236 static int tegra_spi_runtime_suspend(struct device
*dev
)
1238 struct spi_master
*master
= dev_get_drvdata(dev
);
1239 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1241 /* Flush all write which are in PPSB queue by reading back */
1242 tegra_spi_readl(tspi
, SPI_COMMAND1
);
1244 clk_disable_unprepare(tspi
->clk
);
1248 static int tegra_spi_runtime_resume(struct device
*dev
)
1250 struct spi_master
*master
= dev_get_drvdata(dev
);
1251 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1254 ret
= clk_prepare_enable(tspi
->clk
);
1256 dev_err(tspi
->dev
, "clk_prepare failed: %d\n", ret
);
1262 static const struct dev_pm_ops tegra_spi_pm_ops
= {
1263 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend
,
1264 tegra_spi_runtime_resume
, NULL
)
1265 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend
, tegra_spi_resume
)
1267 static struct platform_driver tegra_spi_driver
= {
1269 .name
= "spi-tegra114",
1270 .owner
= THIS_MODULE
,
1271 .pm
= &tegra_spi_pm_ops
,
1272 .of_match_table
= tegra_spi_of_match
,
1274 .probe
= tegra_spi_probe
,
1275 .remove
= tegra_spi_remove
,
1277 module_platform_driver(tegra_spi_driver
);
1279 MODULE_ALIAS("platform:spi-tegra114");
1280 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1281 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1282 MODULE_LICENSE("GPL v2");