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spi/xilinx: Support for spi mode LSB_FIRST
[deliverable/linux.git] / drivers / spi / spi-xilinx.c
1 /*
2 * Xilinx SPI controller driver (master mode only)
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
10
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/spi/xilinx_spi.h>
23 #include <linux/io.h>
24
25 #define XILINX_SPI_NAME "xilinx_spi"
26
27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
29 */
30 #define XSPI_CR_OFFSET 0x60 /* Control Register */
31
32 #define XSPI_CR_LOOP 0x01
33 #define XSPI_CR_ENABLE 0x02
34 #define XSPI_CR_MASTER_MODE 0x04
35 #define XSPI_CR_CPOL 0x08
36 #define XSPI_CR_CPHA 0x10
37 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
38 XSPI_CR_LSB_FIRST)
39 #define XSPI_CR_TXFIFO_RESET 0x20
40 #define XSPI_CR_RXFIFO_RESET 0x40
41 #define XSPI_CR_MANUAL_SSELECT 0x80
42 #define XSPI_CR_TRANS_INHIBIT 0x100
43 #define XSPI_CR_LSB_FIRST 0x200
44
45 #define XSPI_SR_OFFSET 0x64 /* Status Register */
46
47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
52
53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
55
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
57
58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59 * IPIF registers are 32 bit
60 */
61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
63
64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
66
67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
69 * disabled */
70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
75
76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
78
79 struct xilinx_spi {
80 /* bitbang has to be first */
81 struct spi_bitbang bitbang;
82 struct completion done;
83 void __iomem *regs; /* virt. address of the control registers */
84
85 int irq;
86
87 u8 *rx_ptr; /* pointer in the Tx buffer */
88 const u8 *tx_ptr; /* pointer in the Rx buffer */
89 int remaining_bytes; /* the number of bytes left to transfer */
90 u8 bits_per_word;
91 unsigned int (*read_fn)(void __iomem *);
92 void (*write_fn)(u32, void __iomem *);
93 void (*tx_fn)(struct xilinx_spi *);
94 void (*rx_fn)(struct xilinx_spi *);
95 };
96
97 static void xspi_write32(u32 val, void __iomem *addr)
98 {
99 iowrite32(val, addr);
100 }
101
102 static unsigned int xspi_read32(void __iomem *addr)
103 {
104 return ioread32(addr);
105 }
106
107 static void xspi_write32_be(u32 val, void __iomem *addr)
108 {
109 iowrite32be(val, addr);
110 }
111
112 static unsigned int xspi_read32_be(void __iomem *addr)
113 {
114 return ioread32be(addr);
115 }
116
117 static void xspi_tx8(struct xilinx_spi *xspi)
118 {
119 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
120 xspi->tx_ptr++;
121 }
122
123 static void xspi_tx16(struct xilinx_spi *xspi)
124 {
125 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
126 xspi->tx_ptr += 2;
127 }
128
129 static void xspi_tx32(struct xilinx_spi *xspi)
130 {
131 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
132 xspi->tx_ptr += 4;
133 }
134
135 static void xspi_rx8(struct xilinx_spi *xspi)
136 {
137 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
138 if (xspi->rx_ptr) {
139 *xspi->rx_ptr = data & 0xff;
140 xspi->rx_ptr++;
141 }
142 }
143
144 static void xspi_rx16(struct xilinx_spi *xspi)
145 {
146 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
147 if (xspi->rx_ptr) {
148 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
149 xspi->rx_ptr += 2;
150 }
151 }
152
153 static void xspi_rx32(struct xilinx_spi *xspi)
154 {
155 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
156 if (xspi->rx_ptr) {
157 *(u32 *)(xspi->rx_ptr) = data;
158 xspi->rx_ptr += 4;
159 }
160 }
161
162 static void xspi_init_hw(struct xilinx_spi *xspi)
163 {
164 void __iomem *regs_base = xspi->regs;
165
166 /* Reset the SPI device */
167 xspi->write_fn(XIPIF_V123B_RESET_MASK,
168 regs_base + XIPIF_V123B_RESETR_OFFSET);
169 /* Disable all the interrupts just in case */
170 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
171 /* Enable the global IPIF interrupt */
172 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
173 regs_base + XIPIF_V123B_DGIER_OFFSET);
174 /* Deselect the slave on the SPI bus */
175 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
176 /* Disable the transmitter, enable Manual Slave Select Assertion,
177 * put SPI controller into master mode, and enable it */
178 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
179 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
180 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
181 }
182
183 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
184 {
185 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
186
187 if (is_on == BITBANG_CS_INACTIVE) {
188 /* Deselect the slave on the SPI bus */
189 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
190 } else if (is_on == BITBANG_CS_ACTIVE) {
191 /* Set the SPI clock phase and polarity */
192 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
193 & ~XSPI_CR_MODE_MASK;
194 if (spi->mode & SPI_CPHA)
195 cr |= XSPI_CR_CPHA;
196 if (spi->mode & SPI_CPOL)
197 cr |= XSPI_CR_CPOL;
198 if (spi->mode & SPI_LSB_FIRST)
199 cr |= XSPI_CR_LSB_FIRST;
200 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
201
202 /* We do not check spi->max_speed_hz here as the SPI clock
203 * frequency is not software programmable (the IP block design
204 * parameter)
205 */
206
207 /* Activate the chip select */
208 xspi->write_fn(~(0x0001 << spi->chip_select),
209 xspi->regs + XSPI_SSR_OFFSET);
210 }
211 }
212
213 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
214 * custom txrx_bufs().
215 */
216 static int xilinx_spi_setup_transfer(struct spi_device *spi,
217 struct spi_transfer *t)
218 {
219 return 0;
220 }
221
222 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
223 {
224 u8 sr;
225
226 /* Fill the Tx FIFO with as many bytes as possible */
227 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
228 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
229 if (xspi->tx_ptr)
230 xspi->tx_fn(xspi);
231 else
232 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
233 xspi->remaining_bytes -= xspi->bits_per_word / 8;
234 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
235 }
236 }
237
238 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
239 {
240 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
241 u32 ipif_ier;
242
243 /* We get here with transmitter inhibited */
244
245 xspi->tx_ptr = t->tx_buf;
246 xspi->rx_ptr = t->rx_buf;
247 xspi->remaining_bytes = t->len;
248 reinit_completion(&xspi->done);
249
250
251 /* Enable the transmit empty interrupt, which we use to determine
252 * progress on the transmission.
253 */
254 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
255 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
256 xspi->regs + XIPIF_V123B_IIER_OFFSET);
257
258 for (;;) {
259 u16 cr;
260 u8 sr;
261
262 xilinx_spi_fill_tx_fifo(xspi);
263
264 /* Start the transfer by not inhibiting the transmitter any
265 * longer
266 */
267 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
268 ~XSPI_CR_TRANS_INHIBIT;
269 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
270
271 wait_for_completion(&xspi->done);
272
273 /* A transmit has just completed. Process received data and
274 * check for more data to transmit. Always inhibit the
275 * transmitter while the Isr refills the transmit register/FIFO,
276 * or make sure it is stopped if we're done.
277 */
278 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
279 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
280 xspi->regs + XSPI_CR_OFFSET);
281
282 /* Read out all the data from the Rx FIFO */
283 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
284 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
285 xspi->rx_fn(xspi);
286 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
287 }
288
289 /* See if there is more data to send */
290 if (xspi->remaining_bytes <= 0)
291 break;
292 }
293
294 /* Disable the transmit empty interrupt */
295 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
296
297 return t->len - xspi->remaining_bytes;
298 }
299
300
301 /* This driver supports single master mode only. Hence Tx FIFO Empty
302 * is the only interrupt we care about.
303 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
304 * Fault are not to happen.
305 */
306 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
307 {
308 struct xilinx_spi *xspi = dev_id;
309 u32 ipif_isr;
310
311 /* Get the IPIF interrupts, and clear them immediately */
312 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
313 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
314
315 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
316 complete(&xspi->done);
317 }
318
319 return IRQ_HANDLED;
320 }
321
322 static const struct of_device_id xilinx_spi_of_match[] = {
323 { .compatible = "xlnx,xps-spi-2.00.a", },
324 { .compatible = "xlnx,xps-spi-2.00.b", },
325 {}
326 };
327 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
328
329 static int xilinx_spi_probe(struct platform_device *pdev)
330 {
331 struct xilinx_spi *xspi;
332 struct xspi_platform_data *pdata;
333 struct resource *res;
334 int ret, num_cs = 0, bits_per_word = 8;
335 struct spi_master *master;
336 u32 tmp;
337 u8 i;
338
339 pdata = dev_get_platdata(&pdev->dev);
340 if (pdata) {
341 num_cs = pdata->num_chipselect;
342 bits_per_word = pdata->bits_per_word;
343 } else {
344 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
345 &num_cs);
346 }
347
348 if (!num_cs) {
349 dev_err(&pdev->dev,
350 "Missing slave select configuration data\n");
351 return -EINVAL;
352 }
353
354 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
355 if (!master)
356 return -ENODEV;
357
358 /* the spi->mode bits understood by this driver: */
359 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
360
361 xspi = spi_master_get_devdata(master);
362 xspi->bitbang.master = master;
363 xspi->bitbang.chipselect = xilinx_spi_chipselect;
364 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
365 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
366 init_completion(&xspi->done);
367
368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
370 if (IS_ERR(xspi->regs)) {
371 ret = PTR_ERR(xspi->regs);
372 goto put_master;
373 }
374
375 master->bus_num = pdev->id;
376 master->num_chipselect = num_cs;
377 master->dev.of_node = pdev->dev.of_node;
378
379 /*
380 * Detect endianess on the IP via loop bit in CR. Detection
381 * must be done before reset is sent because incorrect reset
382 * value generates error interrupt.
383 * Setup little endian helper functions first and try to use them
384 * and check if bit was correctly setup or not.
385 */
386 xspi->read_fn = xspi_read32;
387 xspi->write_fn = xspi_write32;
388
389 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
390 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
391 tmp &= XSPI_CR_LOOP;
392 if (tmp != XSPI_CR_LOOP) {
393 xspi->read_fn = xspi_read32_be;
394 xspi->write_fn = xspi_write32_be;
395 }
396
397 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
398 xspi->bits_per_word = bits_per_word;
399 if (xspi->bits_per_word == 8) {
400 xspi->tx_fn = xspi_tx8;
401 xspi->rx_fn = xspi_rx8;
402 } else if (xspi->bits_per_word == 16) {
403 xspi->tx_fn = xspi_tx16;
404 xspi->rx_fn = xspi_rx16;
405 } else if (xspi->bits_per_word == 32) {
406 xspi->tx_fn = xspi_tx32;
407 xspi->rx_fn = xspi_rx32;
408 } else {
409 ret = -EINVAL;
410 goto put_master;
411 }
412
413 /* SPI controller initializations */
414 xspi_init_hw(xspi);
415
416 xspi->irq = platform_get_irq(pdev, 0);
417 if (xspi->irq < 0) {
418 ret = xspi->irq;
419 goto put_master;
420 }
421
422 /* Register for SPI Interrupt */
423 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
424 dev_name(&pdev->dev), xspi);
425 if (ret)
426 goto put_master;
427
428 ret = spi_bitbang_start(&xspi->bitbang);
429 if (ret) {
430 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
431 goto put_master;
432 }
433
434 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
435 (unsigned long long)res->start, xspi->regs, xspi->irq);
436
437 if (pdata) {
438 for (i = 0; i < pdata->num_devices; i++)
439 spi_new_device(master, pdata->devices + i);
440 }
441
442 platform_set_drvdata(pdev, master);
443 return 0;
444
445 put_master:
446 spi_master_put(master);
447
448 return ret;
449 }
450
451 static int xilinx_spi_remove(struct platform_device *pdev)
452 {
453 struct spi_master *master = platform_get_drvdata(pdev);
454 struct xilinx_spi *xspi = spi_master_get_devdata(master);
455 void __iomem *regs_base = xspi->regs;
456
457 spi_bitbang_stop(&xspi->bitbang);
458
459 /* Disable all the interrupts just in case */
460 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
461 /* Disable the global IPIF interrupt */
462 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
463
464 spi_master_put(xspi->bitbang.master);
465
466 return 0;
467 }
468
469 /* work with hotplug and coldplug */
470 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
471
472 static struct platform_driver xilinx_spi_driver = {
473 .probe = xilinx_spi_probe,
474 .remove = xilinx_spi_remove,
475 .driver = {
476 .name = XILINX_SPI_NAME,
477 .of_match_table = xilinx_spi_of_match,
478 },
479 };
480 module_platform_driver(xilinx_spi_driver);
481
482 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
483 MODULE_DESCRIPTION("Xilinx SPI driver");
484 MODULE_LICENSE("GPL");
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