2 * Sonics Silicon Backplane
3 * Broadcom MIPS core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
13 #include <linux/serial.h>
14 #include <linux/serial_core.h>
15 #include <linux/serial_reg.h>
16 #include <linux/time.h>
18 #include "ssb_private.h"
21 static inline u32
mips_read32(struct ssb_mipscore
*mcore
,
24 return ssb_read32(mcore
->dev
, offset
);
27 static inline void mips_write32(struct ssb_mipscore
*mcore
,
31 ssb_write32(mcore
->dev
, offset
, value
);
34 static const u32 ipsflag_irq_mask
[] = {
42 static const u32 ipsflag_irq_shift
[] = {
44 SSB_IPSFLAG_IRQ1_SHIFT
,
45 SSB_IPSFLAG_IRQ2_SHIFT
,
46 SSB_IPSFLAG_IRQ3_SHIFT
,
47 SSB_IPSFLAG_IRQ4_SHIFT
,
50 static inline u32
ssb_irqflag(struct ssb_device
*dev
)
52 return ssb_read32(dev
, SSB_TPSFLAG
) & SSB_TPSFLAG_BPFLAG
;
55 /* Get the MIPS IRQ assignment for a specified device.
56 * If unassigned, 0 is returned.
58 unsigned int ssb_mips_irq(struct ssb_device
*dev
)
60 struct ssb_bus
*bus
= dev
->bus
;
66 irqflag
= ssb_irqflag(dev
);
67 ipsflag
= ssb_read32(bus
->mipscore
.dev
, SSB_IPSFLAG
);
68 for (irq
= 1; irq
<= 4; irq
++) {
69 tmp
= ((ipsflag
& ipsflag_irq_mask
[irq
]) >> ipsflag_irq_shift
[irq
]);
79 static void clear_irq(struct ssb_bus
*bus
, unsigned int irq
)
81 struct ssb_device
*dev
= bus
->mipscore
.dev
;
83 /* Clear the IRQ in the MIPScore backplane registers */
85 ssb_write32(dev
, SSB_INTVEC
, 0);
87 ssb_write32(dev
, SSB_IPSFLAG
,
88 ssb_read32(dev
, SSB_IPSFLAG
) |
89 ipsflag_irq_mask
[irq
]);
93 static void set_irq(struct ssb_device
*dev
, unsigned int irq
)
95 unsigned int oldirq
= ssb_mips_irq(dev
);
96 struct ssb_bus
*bus
= dev
->bus
;
97 struct ssb_device
*mdev
= bus
->mipscore
.dev
;
98 u32 irqflag
= ssb_irqflag(dev
);
102 ssb_dprintk(KERN_INFO PFX
103 "set_irq: core 0x%04x, irq %d => %d\n",
104 dev
->id
.coreid
, oldirq
, irq
);
105 /* clear the old irq */
107 ssb_write32(mdev
, SSB_INTVEC
, (~(1 << irqflag
) & ssb_read32(mdev
, SSB_INTVEC
)));
109 clear_irq(bus
, oldirq
);
111 /* assign the new one */
113 ssb_write32(mdev
, SSB_INTVEC
, ((1 << irqflag
) | ssb_read32(mdev
, SSB_INTVEC
)));
115 irqflag
<<= ipsflag_irq_shift
[irq
];
116 irqflag
|= (ssb_read32(mdev
, SSB_IPSFLAG
) & ~ipsflag_irq_mask
[irq
]);
117 ssb_write32(mdev
, SSB_IPSFLAG
, irqflag
);
121 static void ssb_mips_serial_init(struct ssb_mipscore
*mcore
)
123 struct ssb_bus
*bus
= mcore
->dev
->bus
;
126 mcore
->nr_serial_ports
= ssb_extif_serial_init(&bus
->extif
, mcore
->serial_ports
);
127 else if (bus
->chipco
.dev
)
128 mcore
->nr_serial_ports
= ssb_chipco_serial_init(&bus
->chipco
, mcore
->serial_ports
);
130 mcore
->nr_serial_ports
= 0;
133 static void ssb_mips_flash_detect(struct ssb_mipscore
*mcore
)
135 struct ssb_bus
*bus
= mcore
->dev
->bus
;
137 mcore
->flash_buswidth
= 2;
138 if (bus
->chipco
.dev
) {
139 mcore
->flash_window
= 0x1c000000;
140 mcore
->flash_window_size
= 0x02000000;
141 if ((ssb_read32(bus
->chipco
.dev
, SSB_CHIPCO_FLASH_CFG
)
142 & SSB_CHIPCO_CFG_DS16
) == 0)
143 mcore
->flash_buswidth
= 1;
145 mcore
->flash_window
= 0x1fc00000;
146 mcore
->flash_window_size
= 0x00400000;
150 u32
ssb_cpu_clock(struct ssb_mipscore
*mcore
)
152 struct ssb_bus
*bus
= mcore
->dev
->bus
;
153 u32 pll_type
, n
, m
, rate
= 0;
155 if (bus
->extif
.dev
) {
156 ssb_extif_get_clockcontrol(&bus
->extif
, &pll_type
, &n
, &m
);
157 } else if (bus
->chipco
.dev
) {
158 ssb_chipco_get_clockcpu(&bus
->chipco
, &pll_type
, &n
, &m
);
162 if ((pll_type
== SSB_PLLTYPE_5
) || (bus
->chip_id
== 0x5365)) {
165 rate
= ssb_calc_clock_rate(pll_type
, n
, m
);
168 if (pll_type
== SSB_PLLTYPE_6
) {
175 void ssb_mipscore_init(struct ssb_mipscore
*mcore
)
178 struct ssb_device
*dev
;
179 unsigned long hz
, ns
;
183 return; /* We don't have a MIPS core */
185 ssb_dprintk(KERN_INFO PFX
"Initializing MIPS core...\n");
187 bus
= mcore
->dev
->bus
;
188 hz
= ssb_clockspeed(bus
);
191 ns
= 1000000000 / hz
;
194 ssb_extif_timing_init(&bus
->extif
, ns
);
195 else if (bus
->chipco
.dev
)
196 ssb_chipco_timing_init(&bus
->chipco
, ns
);
198 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
199 for (irq
= 2, i
= 0; i
< bus
->nr_devices
; i
++) {
200 dev
= &(bus
->devices
[i
]);
201 dev
->irq
= ssb_mips_irq(dev
) + 2;
202 switch (dev
->id
.coreid
) {
203 case SSB_DEV_USB11_HOST
:
204 /* shouldn't need a separate irq line for non-4710, most of them have a proper
205 * external usb controller on the pci */
206 if ((bus
->chip_id
== 0x4710) && (irq
<= 4)) {
212 case SSB_DEV_ETHERNET
:
213 case SSB_DEV_ETHERNET_GBIT
:
215 case SSB_DEV_USB20_HOST
:
216 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
224 ssb_mips_serial_init(mcore
);
225 ssb_mips_flash_detect(mcore
);
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