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staging: brcm80211: remove usage of printf (macro) from driver
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <bcmdefs.h>
19 #include <linux/netdevice.h>
20 #include <osl.h>
21 #include <bcmsdh.h>
22
23 #ifdef BCMEMBEDIMAGE
24 #include BCMEMBEDIMAGE
25 #endif /* BCMEMBEDIMAGE */
26
27 #include <bcmdefs.h>
28 #include <bcmutils.h>
29 #include <bcmendian.h>
30 #include <bcmdevs.h>
31
32 #include <siutils.h>
33 #include <hndpmu.h>
34 #include <hndsoc.h>
35 #ifdef DHD_DEBUG
36 #include <hndrte_armtrap.h>
37 #include <hndrte_cons.h>
38 #endif /* DHD_DEBUG */
39 #include <sbchipc.h>
40 #include <sbhnddma.h>
41
42 #include <sdio.h>
43 #include <sbsdio.h>
44 #include <sbsdpcmdev.h>
45 #include <bcmsdpcm.h>
46
47 #include <proto/802.1d.h>
48 #include <proto/802.11.h>
49
50 #include <dngl_stats.h>
51 #include <dhd.h>
52 #include <dhd_bus.h>
53 #include <dhd_proto.h>
54 #include <dhd_dbg.h>
55 #include <dhdioctl.h>
56 #include <sdiovar.h>
57 #include <siutils_priv.h>
58
59 #ifndef DHDSDIO_MEM_DUMP_FNAME
60 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
61 #endif
62
63 #define QLEN 256 /* bulk rx and tx queue lengths */
64 #define FCHI (QLEN - 10)
65 #define FCLOW (FCHI / 2)
66 #define PRIOMASK 7
67
68 #define TXRETRIES 2 /* # of retries for tx frames */
69
70 #if defined(CONFIG_MACH_SANDGATE2G)
71 #define DHD_RXBOUND 250 /* Default for max rx frames in
72 one scheduling */
73 #else
74 #define DHD_RXBOUND 50 /* Default for max rx frames in
75 one scheduling */
76 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
77
78 #define DHD_TXBOUND 20 /* Default for max tx frames in
79 one scheduling */
80
81 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
82
83 #define MEMBLOCK 2048 /* Block size used for downloading
84 of dongle image */
85 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
86 biggest possible glom */
87
88 /* Packet alignment for most efficient SDIO (can change based on platform) */
89 #ifndef DHD_SDALIGN
90 #define DHD_SDALIGN 32
91 #endif
92 #if !ISPOWEROF2(DHD_SDALIGN)
93 #error DHD_SDALIGN is not a power of 2!
94 #endif
95
96 #ifndef DHD_FIRSTREAD
97 #define DHD_FIRSTREAD 32
98 #endif
99 #if !ISPOWEROF2(DHD_FIRSTREAD)
100 #error DHD_FIRSTREAD is not a power of 2!
101 #endif
102
103 /* Total length of frame header for dongle protocol */
104 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
105 #ifdef SDTEST
106 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
107 #else
108 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
109 #endif
110
111 /* Space for header read, limit for data packets */
112 #ifndef MAX_HDR_READ
113 #define MAX_HDR_READ 32
114 #endif
115 #if !ISPOWEROF2(MAX_HDR_READ)
116 #error MAX_HDR_READ is not a power of 2!
117 #endif
118
119 #define MAX_RX_DATASZ 2048
120
121 /* Maximum milliseconds to wait for F2 to come up */
122 #define DHD_WAIT_F2RDY 3000
123
124 /* Bump up limit on waiting for HT to account for first startup;
125 * if the image is doing a CRC calculation before programming the PMU
126 * for HT availability, it could take a couple hundred ms more, so
127 * max out at a 1 second (1000000us).
128 */
129 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
130 #undef PMU_MAX_TRANSITION_DLY
131 #define PMU_MAX_TRANSITION_DLY 1000000
132 #endif
133
134 /* Value for ChipClockCSR during initial setup */
135 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
136 SBSDIO_ALP_AVAIL_REQ)
137 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
138
139 /* Flags for SDH calls */
140 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
141
142 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
143 * bufpool was present for gspi bus.
144 */
145 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
146 pkt_buf_free_skb(bus->dhd->osh, pkt, false);
147 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
148 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
149 uint len);
150
151 #ifdef DHD_DEBUG
152 /* Device console log buffer state */
153 typedef struct dhd_console {
154 uint count; /* Poll interval msec counter */
155 uint log_addr; /* Log struct address (fixed) */
156 hndrte_log_t log; /* Log struct (host copy) */
157 uint bufsize; /* Size of log buffer */
158 u8 *buf; /* Log buffer (host copy) */
159 uint last; /* Last buffer read index */
160 } dhd_console_t;
161 #endif /* DHD_DEBUG */
162
163 /* Private data for SDIO bus interaction */
164 typedef struct dhd_bus {
165 dhd_pub_t *dhd;
166
167 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
168 si_t *sih; /* Handle for SI calls */
169 char *vars; /* Variables (from CIS and/or other) */
170 uint varsz; /* Size of variables buffer */
171 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
172
173 sdpcmd_regs_t *regs; /* Registers for SDIO core */
174 uint sdpcmrev; /* SDIO core revision */
175 uint armrev; /* CPU core revision */
176 uint ramrev; /* SOCRAM core revision */
177 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
178 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
179
180 u32 bus; /* gSPI or SDIO bus */
181 u32 hostintmask; /* Copy of Host Interrupt Mask */
182 u32 intstatus; /* Intstatus bits (events) pending */
183 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
184 bool fcstate; /* State of dongle flow-control */
185
186 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
187 char *fw_path; /* module_param: path to firmware image */
188 char *nv_path; /* module_param: path to nvram vars file */
189 const char *nvram_params; /* user specified nvram params. */
190
191 uint blocksize; /* Block size of SDIO transfers */
192 uint roundup; /* Max roundup limit */
193
194 struct pktq txq; /* Queue length used for flow-control */
195 u8 flowcontrol; /* per prio flow control bitmask */
196 u8 tx_seq; /* Transmit sequence number (next) */
197 u8 tx_max; /* Maximum transmit sequence allowed */
198
199 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
200 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
201 u16 nextlen; /* Next Read Len from last header */
202 u8 rx_seq; /* Receive sequence number (expected) */
203 bool rxskip; /* Skip receive (awaiting NAK ACK) */
204
205 struct sk_buff *glomd; /* Packet containing glomming descriptor */
206 struct sk_buff *glom; /* Packet chain for glommed superframe */
207 uint glomerr; /* Glom packet read errors */
208
209 u8 *rxbuf; /* Buffer for receiving control packets */
210 uint rxblen; /* Allocated length of rxbuf */
211 u8 *rxctl; /* Aligned pointer into rxbuf */
212 u8 *databuf; /* Buffer for receiving big glom packet */
213 u8 *dataptr; /* Aligned pointer into databuf */
214 uint rxlen; /* Length of valid data in buffer */
215
216 u8 sdpcm_ver; /* Bus protocol reported by dongle */
217
218 bool intr; /* Use interrupts */
219 bool poll; /* Use polling */
220 bool ipend; /* Device interrupt is pending */
221 bool intdis; /* Interrupts disabled by isr */
222 uint intrcount; /* Count of device interrupt callbacks */
223 uint lastintrs; /* Count as of last watchdog timer */
224 uint spurious; /* Count of spurious interrupts */
225 uint pollrate; /* Ticks between device polls */
226 uint polltick; /* Tick counter */
227 uint pollcnt; /* Count of active polls */
228
229 #ifdef DHD_DEBUG
230 dhd_console_t console; /* Console output polling support */
231 uint console_addr; /* Console address from shared struct */
232 #endif /* DHD_DEBUG */
233
234 uint regfails; /* Count of R_REG/W_REG failures */
235
236 uint clkstate; /* State of sd and backplane clock(s) */
237 bool activity; /* Activity flag for clock down */
238 s32 idletime; /* Control for activity timeout */
239 s32 idlecount; /* Activity timeout counter */
240 s32 idleclock; /* How to set bus driver when idle */
241 s32 sd_divisor; /* Speed control to bus driver */
242 s32 sd_mode; /* Mode control to bus driver */
243 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
244 bool use_rxchain; /* If dhd should use PKT chains */
245 bool sleeping; /* Is SDIO bus sleeping? */
246 bool rxflow_mode; /* Rx flow control mode */
247 bool rxflow; /* Is rx flow control on */
248 uint prev_rxlim_hit; /* Is prev rx limit exceeded
249 (per dpc schedule) */
250 bool alp_only; /* Don't use HT clock (ALP only) */
251 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
252 bool usebufpool;
253
254 #ifdef SDTEST
255 /* external loopback */
256 bool ext_loop;
257 u8 loopid;
258
259 /* pktgen configuration */
260 uint pktgen_freq; /* Ticks between bursts */
261 uint pktgen_count; /* Packets to send each burst */
262 uint pktgen_print; /* Bursts between count displays */
263 uint pktgen_total; /* Stop after this many */
264 uint pktgen_minlen; /* Minimum packet data len */
265 uint pktgen_maxlen; /* Maximum packet data len */
266 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
267 uint pktgen_stop; /* Number of tx failures causing stop */
268
269 /* active pktgen fields */
270 uint pktgen_tick; /* Tick counter for bursts */
271 uint pktgen_ptick; /* Burst counter for printing */
272 uint pktgen_sent; /* Number of test packets generated */
273 uint pktgen_rcvd; /* Number of test packets received */
274 uint pktgen_fail; /* Number of failed send attempts */
275 u16 pktgen_len; /* Length of next packet to send */
276 #endif /* SDTEST */
277
278 /* Some additional counters */
279 uint tx_sderrs; /* Count of tx attempts with sd errors */
280 uint fcqueued; /* Tx packets that got queued */
281 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
282 uint rx_toolong; /* Receive frames too long to receive */
283 uint rxc_errors; /* SDIO errors when reading control frames */
284 uint rx_hdrfail; /* SDIO errors on header reads */
285 uint rx_badhdr; /* Bad received headers (roosync?) */
286 uint rx_badseq; /* Mismatched rx sequence number */
287 uint fc_rcvd; /* Number of flow-control events received */
288 uint fc_xoff; /* Number which turned on flow-control */
289 uint fc_xon; /* Number which turned off flow-control */
290 uint rxglomfail; /* Failed deglom attempts */
291 uint rxglomframes; /* Number of glom frames (superframes) */
292 uint rxglompkts; /* Number of packets from glom frames */
293 uint f2rxhdrs; /* Number of header reads */
294 uint f2rxdata; /* Number of frame data reads */
295 uint f2txdata; /* Number of f2 frame writes */
296 uint f1regdata; /* Number of f1 register accesses */
297
298 u8 *ctrl_frame_buf;
299 u32 ctrl_frame_len;
300 bool ctrl_frame_stat;
301 } dhd_bus_t;
302
303 /* clkstate */
304 #define CLK_NONE 0
305 #define CLK_SDONLY 1
306 #define CLK_PENDING 2 /* Not used yet */
307 #define CLK_AVAIL 3
308
309 #define DHD_NOPMU(dhd) (false)
310
311 #ifdef DHD_DEBUG
312 static int qcount[NUMPRIO];
313 static int tx_packets[NUMPRIO];
314 #endif /* DHD_DEBUG */
315
316 /* Deferred transmit */
317 const uint dhd_deferred_tx = 1;
318
319 extern uint dhd_watchdog_ms;
320 extern void dhd_os_wd_timer(void *bus, uint wdtick);
321
322 /* Tx/Rx bounds */
323 uint dhd_txbound;
324 uint dhd_rxbound;
325 uint dhd_txminmax;
326
327 /* override the RAM size if possible */
328 #define DONGLE_MIN_MEMSIZE (128 * 1024)
329 int dhd_dongle_memsize;
330
331 static bool dhd_doflow;
332 static bool dhd_alignctl;
333
334 static bool sd1idle;
335
336 static bool retrydata;
337 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
338
339 static const uint watermark = 8;
340 static const uint firstread = DHD_FIRSTREAD;
341
342 #define HDATLEN (firstread - (SDPCM_HDRLEN))
343
344 /* Retry count for register access failures */
345 static const uint retry_limit = 2;
346
347 /* Force even SD lengths (some host controllers mess up on odd bytes) */
348 static bool forcealign;
349
350 #define ALIGNMENT 4
351
352 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
353 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
354 #endif
355
356 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
357 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
358 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
359 #define PKTALIGN(_osh, _p, _len, _align) \
360 do { \
361 uint datalign; \
362 datalign = (unsigned long)((_p)->data); \
363 datalign = roundup(datalign, (_align)) - datalign; \
364 ASSERT(datalign < (_align)); \
365 ASSERT((_p)->len >= ((_len) + datalign)); \
366 if (datalign) \
367 skb_pull((_p), datalign); \
368 __skb_trim((_p), (_len)); \
369 } while (0)
370
371 /* Limit on rounding up frames */
372 static const uint max_roundup = 512;
373
374 /* Try doing readahead */
375 static bool dhd_readahead;
376
377 /* To check if there's window offered */
378 #define DATAOK(bus) \
379 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
380 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
381
382 /* Macros to get register read/write status */
383 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
384 #define R_SDREG(regvar, regaddr, retryvar) \
385 do { \
386 retryvar = 0; \
387 do { \
388 regvar = R_REG(bus->dhd->osh, regaddr); \
389 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
390 if (retryvar) { \
391 bus->regfails += (retryvar-1); \
392 if (retryvar > retry_limit) { \
393 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
394 __func__, __LINE__)); \
395 regvar = 0; \
396 } \
397 } \
398 } while (0)
399
400 #define W_SDREG(regval, regaddr, retryvar) \
401 do { \
402 retryvar = 0; \
403 do { \
404 W_REG(bus->dhd->osh, regaddr, regval); \
405 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
406 if (retryvar) { \
407 bus->regfails += (retryvar-1); \
408 if (retryvar > retry_limit) \
409 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
410 __func__, __LINE__)); \
411 } \
412 } while (0)
413
414 #define DHD_BUS SDIO_BUS
415
416 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
417
418 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
419
420 #define GSPI_PR55150_BAILOUT
421
422 #ifdef SDTEST
423 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
424 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
425 #endif
426
427 #ifdef DHD_DEBUG
428 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
429 static int dhdsdio_mem_dump(dhd_bus_t *bus);
430 #endif /* DHD_DEBUG */
431 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
432
433 static void dhdsdio_release(dhd_bus_t *bus, struct osl_info *osh);
434 static void dhdsdio_release_malloc(dhd_bus_t *bus, struct osl_info *osh);
435 static void dhdsdio_disconnect(void *ptr);
436 static bool dhdsdio_chipmatch(u16 chipid);
437 static bool dhdsdio_probe_attach(dhd_bus_t *bus, struct osl_info *osh,
438 void *sdh, void *regsva, u16 devid);
439 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, struct osl_info *osh,
440 void *sdh);
441 static bool dhdsdio_probe_init(dhd_bus_t *bus, struct osl_info *osh, void *sdh);
442 static void dhdsdio_release_dongle(dhd_bus_t *bus, struct osl_info * osh);
443
444 static uint process_nvram_vars(char *varbuf, uint len);
445
446 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
447 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
448 uint flags, u8 *buf, uint nbytes,
449 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
450 void *handle);
451 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
452 uint flags, u8 *buf, uint nbytes,
453 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
454 void *handle);
455
456 static bool dhdsdio_download_firmware(struct dhd_bus *bus, struct osl_info *osh,
457 void *sdh);
458 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
459
460 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
461 static int dhdsdio_download_nvram(struct dhd_bus *bus);
462 #ifdef BCMEMBEDIMAGE
463 static int dhdsdio_download_code_array(struct dhd_bus *bus);
464 #endif
465
466 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
467 {
468 s32 min_size = DONGLE_MIN_MEMSIZE;
469 /* Restrict the memsize to user specified limit */
470 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
471 dhd_dongle_memsize, min_size));
472 if ((dhd_dongle_memsize > min_size) &&
473 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
474 bus->ramsize = dhd_dongle_memsize;
475 }
476
477 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
478 {
479 int err = 0;
480 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
481 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
482 if (!err)
483 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
484 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
485 if (!err)
486 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
487 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
488 &err);
489 return err;
490 }
491
492 /* Turn backplane clock on or off */
493 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
494 {
495 int err;
496 u8 clkctl, clkreq, devctl;
497 bcmsdh_info_t *sdh;
498
499 DHD_TRACE(("%s: Enter\n", __func__));
500
501 #if defined(OOB_INTR_ONLY)
502 pendok = false;
503 #endif
504 clkctl = 0;
505 sdh = bus->sdh;
506
507 if (on) {
508 /* Request HT Avail */
509 clkreq =
510 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
511
512 if ((bus->sih->chip == BCM4329_CHIP_ID)
513 && (bus->sih->chiprev == 0))
514 clkreq |= SBSDIO_FORCE_ALP;
515
516 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
517 clkreq, &err);
518 if (err) {
519 DHD_ERROR(("%s: HT Avail request error: %d\n",
520 __func__, err));
521 return BCME_ERROR;
522 }
523
524 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
525 && (bus->sih->buscorerev == 9))) {
526 u32 dummy, retries;
527 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
528 }
529
530 /* Check current status */
531 clkctl =
532 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
533 &err);
534 if (err) {
535 DHD_ERROR(("%s: HT Avail read error: %d\n",
536 __func__, err));
537 return BCME_ERROR;
538 }
539
540 /* Go to pending and await interrupt if appropriate */
541 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
542 /* Allow only clock-available interrupt */
543 devctl =
544 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
545 &err);
546 if (err) {
547 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
548 __func__, err));
549 return BCME_ERROR;
550 }
551
552 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
553 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
554 devctl, &err);
555 DHD_INFO(("CLKCTL: set PENDING\n"));
556 bus->clkstate = CLK_PENDING;
557
558 return BCME_OK;
559 } else if (bus->clkstate == CLK_PENDING) {
560 /* Cancel CA-only interrupt filter */
561 devctl =
562 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
563 &err);
564 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
565 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
566 devctl, &err);
567 }
568
569 /* Otherwise, wait here (polling) for HT Avail */
570 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
571 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
572 ((clkctl =
573 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
574 SBSDIO_FUNC1_CHIPCLKCSR,
575 &err)),
576 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
577 PMU_MAX_TRANSITION_DLY);
578 }
579 if (err) {
580 DHD_ERROR(("%s: HT Avail request error: %d\n",
581 __func__, err));
582 return BCME_ERROR;
583 }
584 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
585 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
586 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
587 return BCME_ERROR;
588 }
589
590 /* Mark clock available */
591 bus->clkstate = CLK_AVAIL;
592 DHD_INFO(("CLKCTL: turned ON\n"));
593
594 #if defined(DHD_DEBUG)
595 if (bus->alp_only == true) {
596 #if !defined(BCMLXSDMMC)
597 if (!SBSDIO_ALPONLY(clkctl)) {
598 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
599 __func__));
600 }
601 #endif /* !defined(BCMLXSDMMC) */
602 } else {
603 if (SBSDIO_ALPONLY(clkctl)) {
604 DHD_ERROR(("%s: HT Clock should be on.\n",
605 __func__));
606 }
607 }
608 #endif /* defined (DHD_DEBUG) */
609
610 bus->activity = true;
611 } else {
612 clkreq = 0;
613
614 if (bus->clkstate == CLK_PENDING) {
615 /* Cancel CA-only interrupt filter */
616 devctl =
617 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
618 &err);
619 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
620 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
621 devctl, &err);
622 }
623
624 bus->clkstate = CLK_SDONLY;
625 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
626 clkreq, &err);
627 DHD_INFO(("CLKCTL: turned OFF\n"));
628 if (err) {
629 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
630 __func__, err));
631 return BCME_ERROR;
632 }
633 }
634 return BCME_OK;
635 }
636
637 /* Change idle/active SD state */
638 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
639 {
640 int err;
641 s32 iovalue;
642
643 DHD_TRACE(("%s: Enter\n", __func__));
644
645 if (on) {
646 if (bus->idleclock == DHD_IDLE_STOP) {
647 /* Turn on clock and restore mode */
648 iovalue = 1;
649 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
650 &iovalue, sizeof(iovalue), true);
651 if (err) {
652 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
653 __func__, err));
654 return BCME_ERROR;
655 }
656
657 iovalue = bus->sd_mode;
658 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
659 &iovalue, sizeof(iovalue), true);
660 if (err) {
661 DHD_ERROR(("%s: error changing sd_mode: %d\n",
662 __func__, err));
663 return BCME_ERROR;
664 }
665 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
666 /* Restore clock speed */
667 iovalue = bus->sd_divisor;
668 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
669 &iovalue, sizeof(iovalue), true);
670 if (err) {
671 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
672 __func__, err));
673 return BCME_ERROR;
674 }
675 }
676 bus->clkstate = CLK_SDONLY;
677 } else {
678 /* Stop or slow the SD clock itself */
679 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
680 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
681 __func__, bus->sd_divisor, bus->sd_mode));
682 return BCME_ERROR;
683 }
684 if (bus->idleclock == DHD_IDLE_STOP) {
685 if (sd1idle) {
686 /* Change to SD1 mode and turn off clock */
687 iovalue = 1;
688 err =
689 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
690 0, &iovalue,
691 sizeof(iovalue), true);
692 if (err) {
693 DHD_ERROR(("%s: error changing sd_clock: %d\n",
694 __func__, err));
695 return BCME_ERROR;
696 }
697 }
698
699 iovalue = 0;
700 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
701 &iovalue, sizeof(iovalue), true);
702 if (err) {
703 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
704 __func__, err));
705 return BCME_ERROR;
706 }
707 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
708 /* Set divisor to idle value */
709 iovalue = bus->idleclock;
710 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
711 &iovalue, sizeof(iovalue), true);
712 if (err) {
713 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
714 __func__, err));
715 return BCME_ERROR;
716 }
717 }
718 bus->clkstate = CLK_NONE;
719 }
720
721 return BCME_OK;
722 }
723
724 /* Transition SD and backplane clock readiness */
725 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
726 {
727 #ifdef DHD_DEBUG
728 uint oldstate = bus->clkstate;
729 #endif /* DHD_DEBUG */
730
731 DHD_TRACE(("%s: Enter\n", __func__));
732
733 /* Early exit if we're already there */
734 if (bus->clkstate == target) {
735 if (target == CLK_AVAIL) {
736 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
737 bus->activity = true;
738 }
739 return BCME_OK;
740 }
741
742 switch (target) {
743 case CLK_AVAIL:
744 /* Make sure SD clock is available */
745 if (bus->clkstate == CLK_NONE)
746 dhdsdio_sdclk(bus, true);
747 /* Now request HT Avail on the backplane */
748 dhdsdio_htclk(bus, true, pendok);
749 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
750 bus->activity = true;
751 break;
752
753 case CLK_SDONLY:
754 /* Remove HT request, or bring up SD clock */
755 if (bus->clkstate == CLK_NONE)
756 dhdsdio_sdclk(bus, true);
757 else if (bus->clkstate == CLK_AVAIL)
758 dhdsdio_htclk(bus, false, false);
759 else
760 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
761 bus->clkstate, target));
762 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
763 break;
764
765 case CLK_NONE:
766 /* Make sure to remove HT request */
767 if (bus->clkstate == CLK_AVAIL)
768 dhdsdio_htclk(bus, false, false);
769 /* Now remove the SD clock */
770 dhdsdio_sdclk(bus, false);
771 dhd_os_wd_timer(bus->dhd, 0);
772 break;
773 }
774 #ifdef DHD_DEBUG
775 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
776 #endif /* DHD_DEBUG */
777
778 return BCME_OK;
779 }
780
781 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
782 {
783 bcmsdh_info_t *sdh = bus->sdh;
784 sdpcmd_regs_t *regs = bus->regs;
785 uint retries = 0;
786
787 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
788 (sleep ? "SLEEP" : "WAKE"),
789 (bus->sleeping ? "SLEEP" : "WAKE")));
790
791 /* Done if we're already in the requested state */
792 if (sleep == bus->sleeping)
793 return BCME_OK;
794
795 /* Going to sleep: set the alarm and turn off the lights... */
796 if (sleep) {
797 /* Don't sleep if something is pending */
798 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
799 return BCME_BUSY;
800
801 /* Disable SDIO interrupts (no longer interested) */
802 bcmsdh_intr_disable(bus->sdh);
803
804 /* Make sure the controller has the bus up */
805 dhdsdio_clkctl(bus, CLK_AVAIL, false);
806
807 /* Tell device to start using OOB wakeup */
808 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
809 if (retries > retry_limit)
810 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
811
812 /* Turn off our contribution to the HT clock request */
813 dhdsdio_clkctl(bus, CLK_SDONLY, false);
814
815 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
816 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
817
818 /* Isolate the bus */
819 if (bus->sih->chip != BCM4329_CHIP_ID
820 && bus->sih->chip != BCM4319_CHIP_ID) {
821 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
822 SBSDIO_DEVCTL_PADS_ISO, NULL);
823 }
824
825 /* Change state */
826 bus->sleeping = true;
827
828 } else {
829 /* Waking up: bus power up is ok, set local state */
830
831 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
832 0, NULL);
833
834 /* Force pad isolation off if possible
835 (in case power never toggled) */
836 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
837 && (bus->sih->buscorerev >= 10))
838 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
839 NULL);
840
841 /* Make sure the controller has the bus up */
842 dhdsdio_clkctl(bus, CLK_AVAIL, false);
843
844 /* Send misc interrupt to indicate OOB not needed */
845 W_SDREG(0, &regs->tosbmailboxdata, retries);
846 if (retries <= retry_limit)
847 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
848
849 if (retries > retry_limit)
850 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
851
852 /* Make sure we have SD bus access */
853 dhdsdio_clkctl(bus, CLK_SDONLY, false);
854
855 /* Change state */
856 bus->sleeping = false;
857
858 /* Enable interrupts again */
859 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
860 bus->intdis = false;
861 bcmsdh_intr_enable(bus->sdh);
862 }
863 }
864
865 return BCME_OK;
866 }
867
868 #if defined(OOB_INTR_ONLY)
869 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
870 {
871 #if defined(HW_OOB)
872 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
873 #else
874 sdpcmd_regs_t *regs = bus->regs;
875 uint retries = 0;
876
877 dhdsdio_clkctl(bus, CLK_AVAIL, false);
878 if (enable == true) {
879
880 /* Tell device to start using OOB wakeup */
881 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
882 if (retries > retry_limit)
883 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
884
885 } else {
886 /* Send misc interrupt to indicate OOB not needed */
887 W_SDREG(0, &regs->tosbmailboxdata, retries);
888 if (retries <= retry_limit)
889 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
890 }
891
892 /* Turn off our contribution to the HT clock request */
893 dhdsdio_clkctl(bus, CLK_SDONLY, false);
894 #endif /* !defined(HW_OOB) */
895 }
896 #endif /* defined(OOB_INTR_ONLY) */
897
898 #define BUS_WAKE(bus) \
899 do { \
900 if ((bus)->sleeping) \
901 dhdsdio_bussleep((bus), false); \
902 } while (0);
903
904 /* Writes a HW/SW header into the packet and sends it. */
905 /* Assumes: (a) header space already there, (b) caller holds lock */
906 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
907 bool free_pkt)
908 {
909 int ret;
910 struct osl_info *osh;
911 u8 *frame;
912 u16 len, pad = 0;
913 u32 swheader;
914 uint retries = 0;
915 bcmsdh_info_t *sdh;
916 struct sk_buff *new;
917 int i;
918
919 DHD_TRACE(("%s: Enter\n", __func__));
920
921 sdh = bus->sdh;
922 osh = bus->dhd->osh;
923
924 if (bus->dhd->dongle_reset) {
925 ret = BCME_NOTREADY;
926 goto done;
927 }
928
929 frame = (u8 *) (pkt->data);
930
931 /* Add alignment padding, allocate new packet if needed */
932 pad = ((unsigned long)frame % DHD_SDALIGN);
933 if (pad) {
934 if (skb_headroom(pkt) < pad) {
935 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
936 __func__, skb_headroom(pkt), pad));
937 bus->dhd->tx_realloc++;
938 new = pkt_buf_get_skb(osh, (pkt->len + DHD_SDALIGN));
939 if (!new) {
940 DHD_ERROR(("%s: couldn't allocate new %d-byte "
941 "packet\n",
942 __func__, pkt->len + DHD_SDALIGN));
943 ret = BCME_NOMEM;
944 goto done;
945 }
946
947 PKTALIGN(osh, new, pkt->len, DHD_SDALIGN);
948 bcopy(pkt->data, new->data, pkt->len);
949 if (free_pkt)
950 pkt_buf_free_skb(osh, pkt, true);
951 /* free the pkt if canned one is not used */
952 free_pkt = true;
953 pkt = new;
954 frame = (u8 *) (pkt->data);
955 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
956 pad = 0;
957 } else {
958 skb_push(pkt, pad);
959 frame = (u8 *) (pkt->data);
960
961 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
962 memset(frame, 0, pad + SDPCM_HDRLEN);
963 }
964 }
965 ASSERT(pad < DHD_SDALIGN);
966
967 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
968 len = (u16) (pkt->len);
969 *(u16 *) frame = htol16(len);
970 *(((u16 *) frame) + 1) = htol16(~len);
971
972 /* Software tag: channel, sequence number, data offset */
973 swheader =
974 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
975 (((pad +
976 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
977 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
978 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
979
980 #ifdef DHD_DEBUG
981 tx_packets[pkt->priority]++;
982 if (DHD_BYTES_ON() &&
983 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
984 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
985 prhex("Tx Frame", frame, len);
986 } else if (DHD_HDRS_ON()) {
987 prhex("TxHdr", frame, min_t(u16, len, 16));
988 }
989 #endif
990
991 /* Raise len to next SDIO block to eliminate tail command */
992 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
993 u16 pad = bus->blocksize - (len % bus->blocksize);
994 if ((pad <= bus->roundup) && (pad < bus->blocksize))
995 #ifdef NOTUSED
996 if (pad <= skb_tailroom(pkt))
997 #endif /* NOTUSED */
998 len += pad;
999 } else if (len % DHD_SDALIGN) {
1000 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1001 }
1002
1003 /* Some controllers have trouble with odd bytes -- round to even */
1004 if (forcealign && (len & (ALIGNMENT - 1))) {
1005 #ifdef NOTUSED
1006 if (skb_tailroom(pkt))
1007 #endif
1008 len = roundup(len, ALIGNMENT);
1009 #ifdef NOTUSED
1010 else
1011 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1012 __func__, len));
1013 #endif
1014 }
1015
1016 do {
1017 ret =
1018 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1019 F2SYNC, frame, len, pkt, NULL, NULL);
1020 bus->f2txdata++;
1021 ASSERT(ret != BCME_PENDING);
1022
1023 if (ret < 0) {
1024 /* On failure, abort the command
1025 and terminate the frame */
1026 DHD_INFO(("%s: sdio error %d, abort command and "
1027 "terminate frame.\n", __func__, ret));
1028 bus->tx_sderrs++;
1029
1030 bcmsdh_abort(sdh, SDIO_FUNC_2);
1031 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1032 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1033 NULL);
1034 bus->f1regdata++;
1035
1036 for (i = 0; i < 3; i++) {
1037 u8 hi, lo;
1038 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1039 SBSDIO_FUNC1_WFRAMEBCHI,
1040 NULL);
1041 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1042 SBSDIO_FUNC1_WFRAMEBCLO,
1043 NULL);
1044 bus->f1regdata += 2;
1045 if ((hi == 0) && (lo == 0))
1046 break;
1047 }
1048
1049 }
1050 if (ret == 0)
1051 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1052
1053 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1054
1055 done:
1056 /* restore pkt buffer pointer before calling tx complete routine */
1057 skb_pull(pkt, SDPCM_HDRLEN + pad);
1058 dhd_os_sdunlock(bus->dhd);
1059 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1060 dhd_os_sdlock(bus->dhd);
1061
1062 if (free_pkt)
1063 pkt_buf_free_skb(osh, pkt, true);
1064
1065 return ret;
1066 }
1067
1068 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1069 {
1070 int ret = BCME_ERROR;
1071 struct osl_info *osh;
1072 uint datalen, prec;
1073
1074 DHD_TRACE(("%s: Enter\n", __func__));
1075
1076 osh = bus->dhd->osh;
1077 datalen = pkt->len;
1078
1079 #ifdef SDTEST
1080 /* Push the test header if doing loopback */
1081 if (bus->ext_loop) {
1082 u8 *data;
1083 skb_push(pkt, SDPCM_TEST_HDRLEN);
1084 data = pkt->data;
1085 *data++ = SDPCM_TEST_ECHOREQ;
1086 *data++ = (u8) bus->loopid++;
1087 *data++ = (datalen >> 0);
1088 *data++ = (datalen >> 8);
1089 datalen += SDPCM_TEST_HDRLEN;
1090 }
1091 #endif /* SDTEST */
1092
1093 /* Add space for the header */
1094 skb_push(pkt, SDPCM_HDRLEN);
1095 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1096
1097 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1098
1099 /* Check for existing queue, current flow-control,
1100 pending event, or pending clock */
1101 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1102 || bus->dpc_sched || (!DATAOK(bus))
1103 || (bus->flowcontrol & NBITVAL(prec))
1104 || (bus->clkstate != CLK_AVAIL)) {
1105 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1106 pktq_len(&bus->txq)));
1107 bus->fcqueued++;
1108
1109 /* Priority based enq */
1110 dhd_os_sdlock_txq(bus->dhd);
1111 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1112 skb_pull(pkt, SDPCM_HDRLEN);
1113 dhd_txcomplete(bus->dhd, pkt, false);
1114 pkt_buf_free_skb(osh, pkt, true);
1115 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1116 ret = BCME_NORESOURCE;
1117 } else {
1118 ret = BCME_OK;
1119 }
1120 dhd_os_sdunlock_txq(bus->dhd);
1121
1122 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1123 dhd_txflowcontrol(bus->dhd, 0, ON);
1124
1125 #ifdef DHD_DEBUG
1126 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1127 qcount[prec] = pktq_plen(&bus->txq, prec);
1128 #endif
1129 /* Schedule DPC if needed to send queued packet(s) */
1130 if (dhd_deferred_tx && !bus->dpc_sched) {
1131 bus->dpc_sched = true;
1132 dhd_sched_dpc(bus->dhd);
1133 }
1134 } else {
1135 /* Lock: we're about to use shared data/code (and SDIO) */
1136 dhd_os_sdlock(bus->dhd);
1137
1138 /* Otherwise, send it now */
1139 BUS_WAKE(bus);
1140 /* Make sure back plane ht clk is on, no pending allowed */
1141 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1142
1143 #ifndef SDTEST
1144 DHD_TRACE(("%s: calling txpkt\n", __func__));
1145 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1146 #else
1147 ret = dhdsdio_txpkt(bus, pkt,
1148 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1149 SDPCM_DATA_CHANNEL), true);
1150 #endif
1151 if (ret)
1152 bus->dhd->tx_errors++;
1153 else
1154 bus->dhd->dstats.tx_bytes += datalen;
1155
1156 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1157 bus->activity = false;
1158 dhdsdio_clkctl(bus, CLK_NONE, true);
1159 }
1160
1161 dhd_os_sdunlock(bus->dhd);
1162 }
1163
1164 return ret;
1165 }
1166
1167 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1168 {
1169 struct sk_buff *pkt;
1170 u32 intstatus = 0;
1171 uint retries = 0;
1172 int ret = 0, prec_out;
1173 uint cnt = 0;
1174 uint datalen;
1175 u8 tx_prec_map;
1176
1177 dhd_pub_t *dhd = bus->dhd;
1178 sdpcmd_regs_t *regs = bus->regs;
1179
1180 DHD_TRACE(("%s: Enter\n", __func__));
1181
1182 tx_prec_map = ~bus->flowcontrol;
1183
1184 /* Send frames until the limit or some other event */
1185 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1186 dhd_os_sdlock_txq(bus->dhd);
1187 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1188 if (pkt == NULL) {
1189 dhd_os_sdunlock_txq(bus->dhd);
1190 break;
1191 }
1192 dhd_os_sdunlock_txq(bus->dhd);
1193 datalen = pkt->len - SDPCM_HDRLEN;
1194
1195 #ifndef SDTEST
1196 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1197 #else
1198 ret = dhdsdio_txpkt(bus, pkt,
1199 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1200 SDPCM_DATA_CHANNEL), true);
1201 #endif
1202 if (ret)
1203 bus->dhd->tx_errors++;
1204 else
1205 bus->dhd->dstats.tx_bytes += datalen;
1206
1207 /* In poll mode, need to check for other events */
1208 if (!bus->intr && cnt) {
1209 /* Check device status, signal pending interrupt */
1210 R_SDREG(intstatus, &regs->intstatus, retries);
1211 bus->f2txdata++;
1212 if (bcmsdh_regfail(bus->sdh))
1213 break;
1214 if (intstatus & bus->hostintmask)
1215 bus->ipend = true;
1216 }
1217 }
1218
1219 /* Deflow-control stack if needed */
1220 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1221 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1222 dhd_txflowcontrol(dhd, 0, OFF);
1223
1224 return cnt;
1225 }
1226
1227 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1228 {
1229 u8 *frame;
1230 u16 len;
1231 u32 swheader;
1232 uint retries = 0;
1233 bcmsdh_info_t *sdh = bus->sdh;
1234 u8 doff = 0;
1235 int ret = -1;
1236 int i;
1237
1238 DHD_TRACE(("%s: Enter\n", __func__));
1239
1240 if (bus->dhd->dongle_reset)
1241 return -EIO;
1242
1243 /* Back the pointer to make a room for bus header */
1244 frame = msg - SDPCM_HDRLEN;
1245 len = (msglen += SDPCM_HDRLEN);
1246
1247 /* Add alignment padding (optional for ctl frames) */
1248 if (dhd_alignctl) {
1249 doff = ((unsigned long)frame % DHD_SDALIGN);
1250 if (doff) {
1251 frame -= doff;
1252 len += doff;
1253 msglen += doff;
1254 memset(frame, 0, doff + SDPCM_HDRLEN);
1255 }
1256 ASSERT(doff < DHD_SDALIGN);
1257 }
1258 doff += SDPCM_HDRLEN;
1259
1260 /* Round send length to next SDIO block */
1261 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1262 u16 pad = bus->blocksize - (len % bus->blocksize);
1263 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1264 len += pad;
1265 } else if (len % DHD_SDALIGN) {
1266 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1267 }
1268
1269 /* Satisfy length-alignment requirements */
1270 if (forcealign && (len & (ALIGNMENT - 1)))
1271 len = roundup(len, ALIGNMENT);
1272
1273 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1274
1275 /* Need to lock here to protect txseq and SDIO tx calls */
1276 dhd_os_sdlock(bus->dhd);
1277
1278 BUS_WAKE(bus);
1279
1280 /* Make sure backplane clock is on */
1281 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1282
1283 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1284 *(u16 *) frame = htol16((u16) msglen);
1285 *(((u16 *) frame) + 1) = htol16(~msglen);
1286
1287 /* Software tag: channel, sequence number, data offset */
1288 swheader =
1289 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1290 SDPCM_CHANNEL_MASK)
1291 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1292 SDPCM_DOFFSET_MASK);
1293 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1294 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1295
1296 if (!DATAOK(bus)) {
1297 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1298 __func__, bus->tx_max, bus->tx_seq));
1299 bus->ctrl_frame_stat = true;
1300 /* Send from dpc */
1301 bus->ctrl_frame_buf = frame;
1302 bus->ctrl_frame_len = len;
1303
1304 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1305
1306 if (bus->ctrl_frame_stat == false) {
1307 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1308 ret = 0;
1309 } else {
1310 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1311 ret = -1;
1312 }
1313 }
1314
1315 if (ret == -1) {
1316 #ifdef DHD_DEBUG
1317 if (DHD_BYTES_ON() && DHD_CTL_ON())
1318 prhex("Tx Frame", frame, len);
1319 else if (DHD_HDRS_ON())
1320 prhex("TxHdr", frame, min_t(u16, len, 16));
1321 #endif
1322
1323 do {
1324 bus->ctrl_frame_stat = false;
1325 ret =
1326 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1327 SDIO_FUNC_2, F2SYNC, frame, len,
1328 NULL, NULL, NULL);
1329
1330 ASSERT(ret != BCME_PENDING);
1331
1332 if (ret < 0) {
1333 /* On failure, abort the command and
1334 terminate the frame */
1335 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1336 __func__, ret));
1337 bus->tx_sderrs++;
1338
1339 bcmsdh_abort(sdh, SDIO_FUNC_2);
1340
1341 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1342 SBSDIO_FUNC1_FRAMECTRL,
1343 SFC_WF_TERM, NULL);
1344 bus->f1regdata++;
1345
1346 for (i = 0; i < 3; i++) {
1347 u8 hi, lo;
1348 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1349 SBSDIO_FUNC1_WFRAMEBCHI,
1350 NULL);
1351 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1352 SBSDIO_FUNC1_WFRAMEBCLO,
1353 NULL);
1354 bus->f1regdata += 2;
1355 if ((hi == 0) && (lo == 0))
1356 break;
1357 }
1358
1359 }
1360 if (ret == 0) {
1361 bus->tx_seq =
1362 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1363 }
1364 } while ((ret < 0) && retries++ < TXRETRIES);
1365 }
1366
1367 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1368 bus->activity = false;
1369 dhdsdio_clkctl(bus, CLK_NONE, true);
1370 }
1371
1372 dhd_os_sdunlock(bus->dhd);
1373
1374 if (ret)
1375 bus->dhd->tx_ctlerrs++;
1376 else
1377 bus->dhd->tx_ctlpkts++;
1378
1379 return ret ? -EIO : 0;
1380 }
1381
1382 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1383 {
1384 int timeleft;
1385 uint rxlen = 0;
1386 bool pending;
1387
1388 DHD_TRACE(("%s: Enter\n", __func__));
1389
1390 if (bus->dhd->dongle_reset)
1391 return -EIO;
1392
1393 /* Wait until control frame is available */
1394 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1395
1396 dhd_os_sdlock(bus->dhd);
1397 rxlen = bus->rxlen;
1398 bcopy(bus->rxctl, msg, min(msglen, rxlen));
1399 bus->rxlen = 0;
1400 dhd_os_sdunlock(bus->dhd);
1401
1402 if (rxlen) {
1403 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1404 __func__, rxlen, msglen));
1405 } else if (timeleft == 0) {
1406 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1407 #ifdef DHD_DEBUG
1408 dhd_os_sdlock(bus->dhd);
1409 dhdsdio_checkdied(bus, NULL, 0);
1410 dhd_os_sdunlock(bus->dhd);
1411 #endif /* DHD_DEBUG */
1412 } else if (pending == true) {
1413 DHD_CTL(("%s: cancelled\n", __func__));
1414 return -ERESTARTSYS;
1415 } else {
1416 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1417 #ifdef DHD_DEBUG
1418 dhd_os_sdlock(bus->dhd);
1419 dhdsdio_checkdied(bus, NULL, 0);
1420 dhd_os_sdunlock(bus->dhd);
1421 #endif /* DHD_DEBUG */
1422 }
1423
1424 if (rxlen)
1425 bus->dhd->rx_ctlpkts++;
1426 else
1427 bus->dhd->rx_ctlerrs++;
1428
1429 return rxlen ? (int)rxlen : -ETIMEDOUT;
1430 }
1431
1432 /* IOVar table */
1433 enum {
1434 IOV_INTR = 1,
1435 IOV_POLLRATE,
1436 IOV_SDREG,
1437 IOV_SBREG,
1438 IOV_SDCIS,
1439 IOV_MEMBYTES,
1440 IOV_MEMSIZE,
1441 #ifdef DHD_DEBUG
1442 IOV_CHECKDIED,
1443 #endif
1444 IOV_DOWNLOAD,
1445 IOV_FORCEEVEN,
1446 IOV_SDIOD_DRIVE,
1447 IOV_READAHEAD,
1448 IOV_SDRXCHAIN,
1449 IOV_ALIGNCTL,
1450 IOV_SDALIGN,
1451 IOV_DEVRESET,
1452 IOV_CPU,
1453 #ifdef SDTEST
1454 IOV_PKTGEN,
1455 IOV_EXTLOOP,
1456 #endif /* SDTEST */
1457 IOV_SPROM,
1458 IOV_TXBOUND,
1459 IOV_RXBOUND,
1460 IOV_TXMINMAX,
1461 IOV_IDLETIME,
1462 IOV_IDLECLOCK,
1463 IOV_SD1IDLE,
1464 IOV_SLEEP,
1465 IOV_VARS
1466 };
1467
1468 const bcm_iovar_t dhdsdio_iovars[] = {
1469 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1470 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1471 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1472 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1473 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1474 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1475 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1476 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1477 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1478 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1479 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1480 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1481 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1482 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1483 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1484 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1485 #ifdef DHD_DEBUG
1486 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1487 ,
1488 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1489 ,
1490 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1491 ,
1492 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1493 ,
1494 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1495 ,
1496 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1497 ,
1498 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1499 ,
1500 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1501 ,
1502 #ifdef DHD_DEBUG
1503 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1504 ,
1505 #endif /* DHD_DEBUG */
1506 #endif /* DHD_DEBUG */
1507 #ifdef SDTEST
1508 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1509 ,
1510 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1511 ,
1512 #endif /* SDTEST */
1513
1514 {NULL, 0, 0, 0, 0}
1515 };
1516
1517 static void
1518 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1519 {
1520 uint q1, q2;
1521
1522 if (!div) {
1523 bcm_bprintf(strbuf, "%s N/A", desc);
1524 } else {
1525 q1 = num / div;
1526 q2 = (100 * (num - (q1 * div))) / div;
1527 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1528 }
1529 }
1530
1531 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1532 {
1533 dhd_bus_t *bus = dhdp->bus;
1534
1535 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1536 bcm_bprintf(strbuf,
1537 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1538 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1539 bcm_bprintf(strbuf,
1540 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1541 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1542 bus->rxskip, bus->rxlen, bus->rx_seq);
1543 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1544 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1545 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1546 bus->pollrate, bus->pollcnt, bus->regfails);
1547
1548 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1549 bcm_bprintf(strbuf,
1550 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1551 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1552 bus->rxc_errors);
1553 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1554 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1555 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1556 bus->fc_xoff, bus->fc_xon);
1557 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1558 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1559 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1560 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1561 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1562 {
1563 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1564 (bus->f2rxhdrs + bus->f2rxdata));
1565 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1566 bus->f1regdata);
1567 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1568 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1569 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1570 bus->intrcount);
1571 bcm_bprintf(strbuf, "\n");
1572
1573 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1574 bus->dhd->rx_packets);
1575 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1576 bus->rxglomframes);
1577 bcm_bprintf(strbuf, "\n");
1578
1579 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1580 bus->f2txdata);
1581 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1582 bus->f1regdata);
1583 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1584 (bus->f2txdata + bus->f1regdata));
1585 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1586 bus->intrcount);
1587 bcm_bprintf(strbuf, "\n");
1588
1589 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1590 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1591 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1592 dhd_dump_pct(strbuf, ", pkts/f1sd",
1593 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1594 bus->f1regdata);
1595 dhd_dump_pct(strbuf, ", pkts/sd",
1596 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1597 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1598 bus->f1regdata));
1599 dhd_dump_pct(strbuf, ", pkts/int",
1600 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1601 bus->intrcount);
1602 bcm_bprintf(strbuf, "\n\n");
1603 }
1604
1605 #ifdef SDTEST
1606 if (bus->pktgen_count) {
1607 bcm_bprintf(strbuf, "pktgen config and count:\n");
1608 bcm_bprintf(strbuf,
1609 "freq %d count %d print %d total %d min %d len %d\n",
1610 bus->pktgen_freq, bus->pktgen_count,
1611 bus->pktgen_print, bus->pktgen_total,
1612 bus->pktgen_minlen, bus->pktgen_maxlen);
1613 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1614 bus->pktgen_sent, bus->pktgen_rcvd,
1615 bus->pktgen_fail);
1616 }
1617 #endif /* SDTEST */
1618 #ifdef DHD_DEBUG
1619 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1620 bus->dpc_sched,
1621 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1622 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1623 bus->roundup);
1624 #endif /* DHD_DEBUG */
1625 bcm_bprintf(strbuf,
1626 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1627 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1628 bus->sleeping);
1629 }
1630
1631 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1632 {
1633 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1634
1635 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1636 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1637 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1638 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1639 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1640 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1641 }
1642
1643 #ifdef SDTEST
1644 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1645 {
1646 dhd_pktgen_t pktgen;
1647
1648 pktgen.version = DHD_PKTGEN_VERSION;
1649 pktgen.freq = bus->pktgen_freq;
1650 pktgen.count = bus->pktgen_count;
1651 pktgen.print = bus->pktgen_print;
1652 pktgen.total = bus->pktgen_total;
1653 pktgen.minlen = bus->pktgen_minlen;
1654 pktgen.maxlen = bus->pktgen_maxlen;
1655 pktgen.numsent = bus->pktgen_sent;
1656 pktgen.numrcvd = bus->pktgen_rcvd;
1657 pktgen.numfail = bus->pktgen_fail;
1658 pktgen.mode = bus->pktgen_mode;
1659 pktgen.stop = bus->pktgen_stop;
1660
1661 bcopy(&pktgen, arg, sizeof(pktgen));
1662
1663 return 0;
1664 }
1665
1666 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1667 {
1668 dhd_pktgen_t pktgen;
1669 uint oldcnt, oldmode;
1670
1671 bcopy(arg, &pktgen, sizeof(pktgen));
1672 if (pktgen.version != DHD_PKTGEN_VERSION)
1673 return BCME_BADARG;
1674
1675 oldcnt = bus->pktgen_count;
1676 oldmode = bus->pktgen_mode;
1677
1678 bus->pktgen_freq = pktgen.freq;
1679 bus->pktgen_count = pktgen.count;
1680 bus->pktgen_print = pktgen.print;
1681 bus->pktgen_total = pktgen.total;
1682 bus->pktgen_minlen = pktgen.minlen;
1683 bus->pktgen_maxlen = pktgen.maxlen;
1684 bus->pktgen_mode = pktgen.mode;
1685 bus->pktgen_stop = pktgen.stop;
1686
1687 bus->pktgen_tick = bus->pktgen_ptick = 0;
1688 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1689 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1690
1691 /* Clear counts for a new pktgen (mode change, or was stopped) */
1692 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1693 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1694
1695 return 0;
1696 }
1697 #endif /* SDTEST */
1698
1699 static int
1700 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1701 uint size)
1702 {
1703 int bcmerror = 0;
1704 u32 sdaddr;
1705 uint dsize;
1706
1707 /* Determine initial transfer parameters */
1708 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1709 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1710 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1711 else
1712 dsize = size;
1713
1714 /* Set the backplane window to include the start address */
1715 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1716 if (bcmerror) {
1717 DHD_ERROR(("%s: window change failed\n", __func__));
1718 goto xfer_done;
1719 }
1720
1721 /* Do the transfer(s) */
1722 while (size) {
1723 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1724 __func__, (write ? "write" : "read"), dsize,
1725 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1726 bcmerror =
1727 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1728 if (bcmerror) {
1729 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1730 break;
1731 }
1732
1733 /* Adjust for next transfer (if any) */
1734 size -= dsize;
1735 if (size) {
1736 data += dsize;
1737 address += dsize;
1738 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1739 if (bcmerror) {
1740 DHD_ERROR(("%s: window change failed\n",
1741 __func__));
1742 break;
1743 }
1744 sdaddr = 0;
1745 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1746 }
1747 }
1748
1749 xfer_done:
1750 /* Return the window to backplane enumeration space for core access */
1751 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1752 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1753 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1754 }
1755
1756 return bcmerror;
1757 }
1758
1759 #ifdef DHD_DEBUG
1760 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1761 {
1762 u32 addr;
1763 int rv;
1764
1765 /* Read last word in memory to determine address of
1766 sdpcm_shared structure */
1767 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1768 if (rv < 0)
1769 return rv;
1770
1771 addr = ltoh32(addr);
1772
1773 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1774
1775 /*
1776 * Check if addr is valid.
1777 * NVRAM length at the end of memory should have been overwritten.
1778 */
1779 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1780 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1781 __func__, addr));
1782 return BCME_ERROR;
1783 }
1784
1785 /* Read hndrte_shared structure */
1786 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1787 sizeof(sdpcm_shared_t));
1788 if (rv < 0)
1789 return rv;
1790
1791 /* Endianness */
1792 sh->flags = ltoh32(sh->flags);
1793 sh->trap_addr = ltoh32(sh->trap_addr);
1794 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1795 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1796 sh->assert_line = ltoh32(sh->assert_line);
1797 sh->console_addr = ltoh32(sh->console_addr);
1798 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1799
1800 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1801 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1802 "is different than sdpcm_shared version %d in dongle\n",
1803 __func__, SDPCM_SHARED_VERSION,
1804 sh->flags & SDPCM_SHARED_VERSION_MASK));
1805 return BCME_ERROR;
1806 }
1807
1808 return BCME_OK;
1809 }
1810
1811 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1812 {
1813 int bcmerror = 0;
1814 uint msize = 512;
1815 char *mbuffer = NULL;
1816 uint maxstrlen = 256;
1817 char *str = NULL;
1818 trap_t tr;
1819 sdpcm_shared_t sdpcm_shared;
1820 struct bcmstrbuf strbuf;
1821
1822 DHD_TRACE(("%s: Enter\n", __func__));
1823
1824 if (data == NULL) {
1825 /*
1826 * Called after a rx ctrl timeout. "data" is NULL.
1827 * allocate memory to trace the trap or assert.
1828 */
1829 size = msize;
1830 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1831 if (mbuffer == NULL) {
1832 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1833 msize));
1834 bcmerror = BCME_NOMEM;
1835 goto done;
1836 }
1837 }
1838
1839 str = kmalloc(maxstrlen, GFP_ATOMIC);
1840 if (str == NULL) {
1841 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1842 bcmerror = BCME_NOMEM;
1843 goto done;
1844 }
1845
1846 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1847 if (bcmerror < 0)
1848 goto done;
1849
1850 bcm_binit(&strbuf, data, size);
1851
1852 bcm_bprintf(&strbuf,
1853 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1854 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1855
1856 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1857 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1858 * (Avoids conflict with real asserts for programmatic
1859 * parsing of output.)
1860 */
1861 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1862 }
1863
1864 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1865 0) {
1866 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1867 * (Avoids conflict with real asserts for programmatic
1868 * parsing of output.)
1869 */
1870 bcm_bprintf(&strbuf, "No trap%s in dongle",
1871 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1872 ? "/assrt" : "");
1873 } else {
1874 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1875 /* Download assert */
1876 bcm_bprintf(&strbuf, "Dongle assert");
1877 if (sdpcm_shared.assert_exp_addr != 0) {
1878 str[0] = '\0';
1879 bcmerror = dhdsdio_membytes(bus, false,
1880 sdpcm_shared.assert_exp_addr,
1881 (u8 *) str, maxstrlen);
1882 if (bcmerror < 0)
1883 goto done;
1884
1885 str[maxstrlen - 1] = '\0';
1886 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1887 }
1888
1889 if (sdpcm_shared.assert_file_addr != 0) {
1890 str[0] = '\0';
1891 bcmerror = dhdsdio_membytes(bus, false,
1892 sdpcm_shared.assert_file_addr,
1893 (u8 *) str, maxstrlen);
1894 if (bcmerror < 0)
1895 goto done;
1896
1897 str[maxstrlen - 1] = '\0';
1898 bcm_bprintf(&strbuf, " file \"%s\"", str);
1899 }
1900
1901 bcm_bprintf(&strbuf, " line %d ",
1902 sdpcm_shared.assert_line);
1903 }
1904
1905 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1906 bcmerror = dhdsdio_membytes(bus, false,
1907 sdpcm_shared.trap_addr, (u8 *)&tr,
1908 sizeof(trap_t));
1909 if (bcmerror < 0)
1910 goto done;
1911
1912 bcm_bprintf(&strbuf,
1913 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1914 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1915 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1916 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1917 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1918 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1919 tr.r6, tr.r7);
1920 }
1921 }
1922
1923 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1924 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1925
1926 #ifdef DHD_DEBUG
1927 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1928 /* Mem dump to a file on device */
1929 dhdsdio_mem_dump(bus);
1930 }
1931 #endif /* DHD_DEBUG */
1932
1933 done:
1934 if (mbuffer)
1935 kfree(mbuffer);
1936 if (str)
1937 kfree(str);
1938
1939 return bcmerror;
1940 }
1941
1942 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1943 {
1944 int ret = 0;
1945 int size; /* Full mem size */
1946 int start = 0; /* Start address */
1947 int read_size = 0; /* Read size of each iteration */
1948 u8 *buf = NULL, *databuf = NULL;
1949
1950 /* Get full mem size */
1951 size = bus->ramsize;
1952 buf = kmalloc(size, GFP_ATOMIC);
1953 if (!buf) {
1954 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
1955 return -1;
1956 }
1957
1958 /* Read mem content */
1959 printk(KERN_DEBUG "Dump dongle memory");
1960 databuf = buf;
1961 while (size) {
1962 read_size = min(MEMBLOCK, size);
1963 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1964 if (ret) {
1965 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
1966 if (buf)
1967 kfree(buf);
1968 return -1;
1969 }
1970 printk(".");
1971
1972 /* Decrement size and increment start address */
1973 size -= read_size;
1974 start += read_size;
1975 databuf += read_size;
1976 }
1977 printk(KERN_DEBUG "Done\n");
1978
1979 /* free buf before return !!! */
1980 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1981 DHD_ERROR(("%s: Error writing to files\n", __func__));
1982 return -1;
1983 }
1984
1985 /* buf free handled in write_to_file, not here */
1986 return 0;
1987 }
1988
1989 #define CONSOLE_LINE_MAX 192
1990
1991 static int dhdsdio_readconsole(dhd_bus_t *bus)
1992 {
1993 dhd_console_t *c = &bus->console;
1994 u8 line[CONSOLE_LINE_MAX], ch;
1995 u32 n, idx, addr;
1996 int rv;
1997
1998 /* Don't do anything until FWREADY updates console address */
1999 if (bus->console_addr == 0)
2000 return 0;
2001
2002 /* Read console log struct */
2003 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
2004 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2005 sizeof(c->log));
2006 if (rv < 0)
2007 return rv;
2008
2009 /* Allocate console buffer (one time only) */
2010 if (c->buf == NULL) {
2011 c->bufsize = ltoh32(c->log.buf_size);
2012 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2013 if (c->buf == NULL)
2014 return BCME_NOMEM;
2015 }
2016
2017 idx = ltoh32(c->log.idx);
2018
2019 /* Protect against corrupt value */
2020 if (idx > c->bufsize)
2021 return BCME_ERROR;
2022
2023 /* Skip reading the console buffer if the index pointer
2024 has not moved */
2025 if (idx == c->last)
2026 return BCME_OK;
2027
2028 /* Read the console buffer */
2029 addr = ltoh32(c->log.buf);
2030 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2031 if (rv < 0)
2032 return rv;
2033
2034 while (c->last != idx) {
2035 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2036 if (c->last == idx) {
2037 /* This would output a partial line.
2038 * Instead, back up
2039 * the buffer pointer and output this
2040 * line next time around.
2041 */
2042 if (c->last >= n)
2043 c->last -= n;
2044 else
2045 c->last = c->bufsize - n;
2046 goto break2;
2047 }
2048 ch = c->buf[c->last];
2049 c->last = (c->last + 1) % c->bufsize;
2050 if (ch == '\n')
2051 break;
2052 line[n] = ch;
2053 }
2054
2055 if (n > 0) {
2056 if (line[n - 1] == '\r')
2057 n--;
2058 line[n] = 0;
2059 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2060 }
2061 }
2062 break2:
2063
2064 return BCME_OK;
2065 }
2066 #endif /* DHD_DEBUG */
2067
2068 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2069 {
2070 int bcmerror = BCME_OK;
2071
2072 DHD_TRACE(("%s: Enter\n", __func__));
2073
2074 /* Basic sanity checks */
2075 if (bus->dhd->up) {
2076 bcmerror = BCME_NOTDOWN;
2077 goto err;
2078 }
2079 if (!len) {
2080 bcmerror = BCME_BUFTOOSHORT;
2081 goto err;
2082 }
2083
2084 /* Free the old ones and replace with passed variables */
2085 if (bus->vars)
2086 kfree(bus->vars);
2087
2088 bus->vars = kmalloc(len, GFP_ATOMIC);
2089 bus->varsz = bus->vars ? len : 0;
2090 if (bus->vars == NULL) {
2091 bcmerror = BCME_NOMEM;
2092 goto err;
2093 }
2094
2095 /* Copy the passed variables, which should include the
2096 terminating double-null */
2097 bcopy(arg, bus->vars, bus->varsz);
2098 err:
2099 return bcmerror;
2100 }
2101
2102 static int
2103 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2104 const char *name, void *params, int plen, void *arg, int len,
2105 int val_size)
2106 {
2107 int bcmerror = 0;
2108 s32 int_val = 0;
2109 bool bool_val = 0;
2110
2111 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2112 "len %d val_size %d\n",
2113 __func__, actionid, name, params, plen, arg, len, val_size));
2114
2115 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2116 if (bcmerror != 0)
2117 goto exit;
2118
2119 if (plen >= (int)sizeof(int_val))
2120 bcopy(params, &int_val, sizeof(int_val));
2121
2122 bool_val = (int_val != 0) ? true : false;
2123
2124 /* Some ioctls use the bus */
2125 dhd_os_sdlock(bus->dhd);
2126
2127 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2128 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2129 actionid == IOV_GVAL(IOV_DEVRESET))) {
2130 bcmerror = BCME_NOTREADY;
2131 goto exit;
2132 }
2133
2134 /* Handle sleep stuff before any clock mucking */
2135 if (vi->varid == IOV_SLEEP) {
2136 if (IOV_ISSET(actionid)) {
2137 bcmerror = dhdsdio_bussleep(bus, bool_val);
2138 } else {
2139 int_val = (s32) bus->sleeping;
2140 bcopy(&int_val, arg, val_size);
2141 }
2142 goto exit;
2143 }
2144
2145 /* Request clock to allow SDIO accesses */
2146 if (!bus->dhd->dongle_reset) {
2147 BUS_WAKE(bus);
2148 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2149 }
2150
2151 switch (actionid) {
2152 case IOV_GVAL(IOV_INTR):
2153 int_val = (s32) bus->intr;
2154 bcopy(&int_val, arg, val_size);
2155 break;
2156
2157 case IOV_SVAL(IOV_INTR):
2158 bus->intr = bool_val;
2159 bus->intdis = false;
2160 if (bus->dhd->up) {
2161 if (bus->intr) {
2162 DHD_INTR(("%s: enable SDIO device interrupts\n",
2163 __func__));
2164 bcmsdh_intr_enable(bus->sdh);
2165 } else {
2166 DHD_INTR(("%s: disable SDIO interrupts\n",
2167 __func__));
2168 bcmsdh_intr_disable(bus->sdh);
2169 }
2170 }
2171 break;
2172
2173 case IOV_GVAL(IOV_POLLRATE):
2174 int_val = (s32) bus->pollrate;
2175 bcopy(&int_val, arg, val_size);
2176 break;
2177
2178 case IOV_SVAL(IOV_POLLRATE):
2179 bus->pollrate = (uint) int_val;
2180 bus->poll = (bus->pollrate != 0);
2181 break;
2182
2183 case IOV_GVAL(IOV_IDLETIME):
2184 int_val = bus->idletime;
2185 bcopy(&int_val, arg, val_size);
2186 break;
2187
2188 case IOV_SVAL(IOV_IDLETIME):
2189 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2190 bcmerror = BCME_BADARG;
2191 else
2192 bus->idletime = int_val;
2193 break;
2194
2195 case IOV_GVAL(IOV_IDLECLOCK):
2196 int_val = (s32) bus->idleclock;
2197 bcopy(&int_val, arg, val_size);
2198 break;
2199
2200 case IOV_SVAL(IOV_IDLECLOCK):
2201 bus->idleclock = int_val;
2202 break;
2203
2204 case IOV_GVAL(IOV_SD1IDLE):
2205 int_val = (s32) sd1idle;
2206 bcopy(&int_val, arg, val_size);
2207 break;
2208
2209 case IOV_SVAL(IOV_SD1IDLE):
2210 sd1idle = bool_val;
2211 break;
2212
2213 case IOV_SVAL(IOV_MEMBYTES):
2214 case IOV_GVAL(IOV_MEMBYTES):
2215 {
2216 u32 address;
2217 uint size, dsize;
2218 u8 *data;
2219
2220 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2221
2222 ASSERT(plen >= 2 * sizeof(int));
2223
2224 address = (u32) int_val;
2225 bcopy((char *)params + sizeof(int_val), &int_val,
2226 sizeof(int_val));
2227 size = (uint) int_val;
2228
2229 /* Do some validation */
2230 dsize = set ? plen - (2 * sizeof(int)) : len;
2231 if (dsize < size) {
2232 DHD_ERROR(("%s: error on %s membytes, addr "
2233 "0x%08x size %d dsize %d\n",
2234 __func__, (set ? "set" : "get"),
2235 address, size, dsize));
2236 bcmerror = BCME_BADARG;
2237 break;
2238 }
2239
2240 DHD_INFO(("%s: Request to %s %d bytes at address "
2241 "0x%08x\n",
2242 __func__, (set ? "write" : "read"), size, address));
2243
2244 /* If we know about SOCRAM, check for a fit */
2245 if ((bus->orig_ramsize) &&
2246 ((address > bus->orig_ramsize)
2247 || (address + size > bus->orig_ramsize))) {
2248 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2249 "bytes at 0x%08x\n",
2250 __func__, bus->orig_ramsize, size, address));
2251 bcmerror = BCME_BADARG;
2252 break;
2253 }
2254
2255 /* Generate the actual data pointer */
2256 data =
2257 set ? (u8 *) params +
2258 2 * sizeof(int) : (u8 *) arg;
2259
2260 /* Call to do the transfer */
2261 bcmerror =
2262 dhdsdio_membytes(bus, set, address, data, size);
2263
2264 break;
2265 }
2266
2267 case IOV_GVAL(IOV_MEMSIZE):
2268 int_val = (s32) bus->ramsize;
2269 bcopy(&int_val, arg, val_size);
2270 break;
2271
2272 case IOV_GVAL(IOV_SDIOD_DRIVE):
2273 int_val = (s32) dhd_sdiod_drive_strength;
2274 bcopy(&int_val, arg, val_size);
2275 break;
2276
2277 case IOV_SVAL(IOV_SDIOD_DRIVE):
2278 dhd_sdiod_drive_strength = int_val;
2279 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
2280 dhd_sdiod_drive_strength);
2281 break;
2282
2283 case IOV_SVAL(IOV_DOWNLOAD):
2284 bcmerror = dhdsdio_download_state(bus, bool_val);
2285 break;
2286
2287 case IOV_SVAL(IOV_VARS):
2288 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2289 break;
2290
2291 case IOV_GVAL(IOV_READAHEAD):
2292 int_val = (s32) dhd_readahead;
2293 bcopy(&int_val, arg, val_size);
2294 break;
2295
2296 case IOV_SVAL(IOV_READAHEAD):
2297 if (bool_val && !dhd_readahead)
2298 bus->nextlen = 0;
2299 dhd_readahead = bool_val;
2300 break;
2301
2302 case IOV_GVAL(IOV_SDRXCHAIN):
2303 int_val = (s32) bus->use_rxchain;
2304 bcopy(&int_val, arg, val_size);
2305 break;
2306
2307 case IOV_SVAL(IOV_SDRXCHAIN):
2308 if (bool_val && !bus->sd_rxchain)
2309 bcmerror = BCME_UNSUPPORTED;
2310 else
2311 bus->use_rxchain = bool_val;
2312 break;
2313 case IOV_GVAL(IOV_ALIGNCTL):
2314 int_val = (s32) dhd_alignctl;
2315 bcopy(&int_val, arg, val_size);
2316 break;
2317
2318 case IOV_SVAL(IOV_ALIGNCTL):
2319 dhd_alignctl = bool_val;
2320 break;
2321
2322 case IOV_GVAL(IOV_SDALIGN):
2323 int_val = DHD_SDALIGN;
2324 bcopy(&int_val, arg, val_size);
2325 break;
2326
2327 #ifdef DHD_DEBUG
2328 case IOV_GVAL(IOV_VARS):
2329 if (bus->varsz < (uint) len)
2330 bcopy(bus->vars, arg, bus->varsz);
2331 else
2332 bcmerror = BCME_BUFTOOSHORT;
2333 break;
2334 #endif /* DHD_DEBUG */
2335
2336 #ifdef DHD_DEBUG
2337 case IOV_GVAL(IOV_SDREG):
2338 {
2339 sdreg_t *sd_ptr;
2340 u32 addr, size;
2341
2342 sd_ptr = (sdreg_t *) params;
2343
2344 addr = (unsigned long)bus->regs + sd_ptr->offset;
2345 size = sd_ptr->func;
2346 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2347 if (bcmsdh_regfail(bus->sdh))
2348 bcmerror = BCME_SDIO_ERROR;
2349 bcopy(&int_val, arg, sizeof(s32));
2350 break;
2351 }
2352
2353 case IOV_SVAL(IOV_SDREG):
2354 {
2355 sdreg_t *sd_ptr;
2356 u32 addr, size;
2357
2358 sd_ptr = (sdreg_t *) params;
2359
2360 addr = (unsigned long)bus->regs + sd_ptr->offset;
2361 size = sd_ptr->func;
2362 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2363 if (bcmsdh_regfail(bus->sdh))
2364 bcmerror = BCME_SDIO_ERROR;
2365 break;
2366 }
2367
2368 /* Same as above, but offset is not backplane
2369 (not SDIO core) */
2370 case IOV_GVAL(IOV_SBREG):
2371 {
2372 sdreg_t sdreg;
2373 u32 addr, size;
2374
2375 bcopy(params, &sdreg, sizeof(sdreg));
2376
2377 addr = SI_ENUM_BASE + sdreg.offset;
2378 size = sdreg.func;
2379 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2380 if (bcmsdh_regfail(bus->sdh))
2381 bcmerror = BCME_SDIO_ERROR;
2382 bcopy(&int_val, arg, sizeof(s32));
2383 break;
2384 }
2385
2386 case IOV_SVAL(IOV_SBREG):
2387 {
2388 sdreg_t sdreg;
2389 u32 addr, size;
2390
2391 bcopy(params, &sdreg, sizeof(sdreg));
2392
2393 addr = SI_ENUM_BASE + sdreg.offset;
2394 size = sdreg.func;
2395 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2396 if (bcmsdh_regfail(bus->sdh))
2397 bcmerror = BCME_SDIO_ERROR;
2398 break;
2399 }
2400
2401 case IOV_GVAL(IOV_SDCIS):
2402 {
2403 *(char *)arg = 0;
2404
2405 strcat(arg, "\nFunc 0\n");
2406 bcmsdh_cis_read(bus->sdh, 0x10,
2407 (u8 *) arg + strlen(arg),
2408 SBSDIO_CIS_SIZE_LIMIT);
2409 strcat(arg, "\nFunc 1\n");
2410 bcmsdh_cis_read(bus->sdh, 0x11,
2411 (u8 *) arg + strlen(arg),
2412 SBSDIO_CIS_SIZE_LIMIT);
2413 strcat(arg, "\nFunc 2\n");
2414 bcmsdh_cis_read(bus->sdh, 0x12,
2415 (u8 *) arg + strlen(arg),
2416 SBSDIO_CIS_SIZE_LIMIT);
2417 break;
2418 }
2419
2420 case IOV_GVAL(IOV_FORCEEVEN):
2421 int_val = (s32) forcealign;
2422 bcopy(&int_val, arg, val_size);
2423 break;
2424
2425 case IOV_SVAL(IOV_FORCEEVEN):
2426 forcealign = bool_val;
2427 break;
2428
2429 case IOV_GVAL(IOV_TXBOUND):
2430 int_val = (s32) dhd_txbound;
2431 bcopy(&int_val, arg, val_size);
2432 break;
2433
2434 case IOV_SVAL(IOV_TXBOUND):
2435 dhd_txbound = (uint) int_val;
2436 break;
2437
2438 case IOV_GVAL(IOV_RXBOUND):
2439 int_val = (s32) dhd_rxbound;
2440 bcopy(&int_val, arg, val_size);
2441 break;
2442
2443 case IOV_SVAL(IOV_RXBOUND):
2444 dhd_rxbound = (uint) int_val;
2445 break;
2446
2447 case IOV_GVAL(IOV_TXMINMAX):
2448 int_val = (s32) dhd_txminmax;
2449 bcopy(&int_val, arg, val_size);
2450 break;
2451
2452 case IOV_SVAL(IOV_TXMINMAX):
2453 dhd_txminmax = (uint) int_val;
2454 break;
2455 #endif /* DHD_DEBUG */
2456
2457 #ifdef SDTEST
2458 case IOV_GVAL(IOV_EXTLOOP):
2459 int_val = (s32) bus->ext_loop;
2460 bcopy(&int_val, arg, val_size);
2461 break;
2462
2463 case IOV_SVAL(IOV_EXTLOOP):
2464 bus->ext_loop = bool_val;
2465 break;
2466
2467 case IOV_GVAL(IOV_PKTGEN):
2468 bcmerror = dhdsdio_pktgen_get(bus, arg);
2469 break;
2470
2471 case IOV_SVAL(IOV_PKTGEN):
2472 bcmerror = dhdsdio_pktgen_set(bus, arg);
2473 break;
2474 #endif /* SDTEST */
2475
2476 case IOV_SVAL(IOV_DEVRESET):
2477 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2478 "busstate=%d\n",
2479 __func__, bool_val, bus->dhd->dongle_reset,
2480 bus->dhd->busstate));
2481
2482 ASSERT(bus->dhd->osh);
2483 /* ASSERT(bus->cl_devid); */
2484
2485 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2486
2487 break;
2488
2489 case IOV_GVAL(IOV_DEVRESET):
2490 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2491
2492 /* Get its status */
2493 int_val = (bool) bus->dhd->dongle_reset;
2494 bcopy(&int_val, arg, val_size);
2495
2496 break;
2497
2498 default:
2499 bcmerror = BCME_UNSUPPORTED;
2500 break;
2501 }
2502
2503 exit:
2504 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2505 bus->activity = false;
2506 dhdsdio_clkctl(bus, CLK_NONE, true);
2507 }
2508
2509 dhd_os_sdunlock(bus->dhd);
2510
2511 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2512 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2513
2514 return bcmerror;
2515 }
2516
2517 static int dhdsdio_write_vars(dhd_bus_t *bus)
2518 {
2519 int bcmerror = 0;
2520 u32 varsize;
2521 u32 varaddr;
2522 u8 *vbuffer;
2523 u32 varsizew;
2524 #ifdef DHD_DEBUG
2525 char *nvram_ularray;
2526 #endif /* DHD_DEBUG */
2527
2528 /* Even if there are no vars are to be written, we still
2529 need to set the ramsize. */
2530 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2531 varaddr = (bus->ramsize - 4) - varsize;
2532
2533 if (bus->vars) {
2534 vbuffer = kmalloc(varsize, GFP_ATOMIC);
2535 if (!vbuffer)
2536 return BCME_NOMEM;
2537
2538 memset(vbuffer, 0, varsize);
2539 bcopy(bus->vars, vbuffer, bus->varsz);
2540
2541 /* Write the vars list */
2542 bcmerror =
2543 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2544 #ifdef DHD_DEBUG
2545 /* Verify NVRAM bytes */
2546 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2547 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2548 if (!nvram_ularray)
2549 return BCME_NOMEM;
2550
2551 /* Upload image to verify downloaded contents. */
2552 memset(nvram_ularray, 0xaa, varsize);
2553
2554 /* Read the vars list to temp buffer for comparison */
2555 bcmerror =
2556 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2557 varsize);
2558 if (bcmerror) {
2559 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2560 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2561 }
2562 /* Compare the org NVRAM with the one read from RAM */
2563 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2564 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2565 __func__));
2566 } else
2567 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2568 __func__));
2569
2570 kfree(nvram_ularray);
2571 #endif /* DHD_DEBUG */
2572
2573 kfree(vbuffer);
2574 }
2575
2576 /* adjust to the user specified RAM */
2577 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2578 bus->orig_ramsize, bus->ramsize));
2579 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2580 varsize = ((bus->orig_ramsize - 4) - varaddr);
2581
2582 /*
2583 * Determine the length token:
2584 * Varsize, converted to words, in lower 16-bits, checksum
2585 * in upper 16-bits.
2586 */
2587 if (bcmerror) {
2588 varsizew = 0;
2589 } else {
2590 varsizew = varsize / 4;
2591 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2592 varsizew = htol32(varsizew);
2593 }
2594
2595 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2596 varsizew));
2597
2598 /* Write the length token to the last word */
2599 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2600 (u8 *)&varsizew, 4);
2601
2602 return bcmerror;
2603 }
2604
2605 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2606 {
2607 uint retries;
2608 int bcmerror = 0;
2609
2610 /* To enter download state, disable ARM and reset SOCRAM.
2611 * To exit download state, simply reset ARM (default is RAM boot).
2612 */
2613 if (enter) {
2614
2615 bus->alp_only = true;
2616
2617 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2618 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2619 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2620 bcmerror = BCME_ERROR;
2621 goto fail;
2622 }
2623
2624 si_core_disable(bus->sih, 0);
2625 if (bcmsdh_regfail(bus->sdh)) {
2626 bcmerror = BCME_SDIO_ERROR;
2627 goto fail;
2628 }
2629
2630 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2631 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2632 __func__));
2633 bcmerror = BCME_ERROR;
2634 goto fail;
2635 }
2636
2637 si_core_reset(bus->sih, 0, 0);
2638 if (bcmsdh_regfail(bus->sdh)) {
2639 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2640 __func__));
2641 bcmerror = BCME_SDIO_ERROR;
2642 goto fail;
2643 }
2644
2645 /* Clear the top bit of memory */
2646 if (bus->ramsize) {
2647 u32 zeros = 0;
2648 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2649 (u8 *)&zeros, 4);
2650 }
2651 } else {
2652 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2653 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2654 __func__));
2655 bcmerror = BCME_ERROR;
2656 goto fail;
2657 }
2658
2659 if (!si_iscoreup(bus->sih)) {
2660 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2661 __func__));
2662 bcmerror = BCME_ERROR;
2663 goto fail;
2664 }
2665
2666 bcmerror = dhdsdio_write_vars(bus);
2667 if (bcmerror) {
2668 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2669 bcmerror = 0;
2670 }
2671
2672 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2673 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2674 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2675 __func__));
2676 bcmerror = BCME_ERROR;
2677 goto fail;
2678 }
2679 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2680
2681 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2682 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2683 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2684 bcmerror = BCME_ERROR;
2685 goto fail;
2686 }
2687
2688 si_core_reset(bus->sih, 0, 0);
2689 if (bcmsdh_regfail(bus->sdh)) {
2690 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2691 __func__));
2692 bcmerror = BCME_SDIO_ERROR;
2693 goto fail;
2694 }
2695
2696 /* Allow HT Clock now that the ARM is running. */
2697 bus->alp_only = false;
2698
2699 bus->dhd->busstate = DHD_BUS_LOAD;
2700 }
2701
2702 fail:
2703 /* Always return to SDIOD core */
2704 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2705 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2706
2707 return bcmerror;
2708 }
2709
2710 int
2711 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2712 void *params, int plen, void *arg, int len, bool set)
2713 {
2714 dhd_bus_t *bus = dhdp->bus;
2715 const bcm_iovar_t *vi = NULL;
2716 int bcmerror = 0;
2717 int val_size;
2718 u32 actionid;
2719
2720 DHD_TRACE(("%s: Enter\n", __func__));
2721
2722 ASSERT(name);
2723 ASSERT(len >= 0);
2724
2725 /* Get MUST have return space */
2726 ASSERT(set || (arg && len));
2727
2728 /* Set does NOT take qualifiers */
2729 ASSERT(!set || (!params && !plen));
2730
2731 /* Look up var locally; if not found pass to host driver */
2732 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2733 if (vi == NULL) {
2734 dhd_os_sdlock(bus->dhd);
2735
2736 BUS_WAKE(bus);
2737
2738 /* Turn on clock in case SD command needs backplane */
2739 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2740
2741 bcmerror =
2742 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2743 set);
2744
2745 /* Check for bus configuration changes of interest */
2746
2747 /* If it was divisor change, read the new one */
2748 if (set && strcmp(name, "sd_divisor") == 0) {
2749 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2750 &bus->sd_divisor, sizeof(s32),
2751 false) != BCME_OK) {
2752 bus->sd_divisor = -1;
2753 DHD_ERROR(("%s: fail on %s get\n", __func__,
2754 name));
2755 } else {
2756 DHD_INFO(("%s: noted %s update, value now %d\n",
2757 __func__, name, bus->sd_divisor));
2758 }
2759 }
2760 /* If it was a mode change, read the new one */
2761 if (set && strcmp(name, "sd_mode") == 0) {
2762 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2763 &bus->sd_mode, sizeof(s32),
2764 false) != BCME_OK) {
2765 bus->sd_mode = -1;
2766 DHD_ERROR(("%s: fail on %s get\n", __func__,
2767 name));
2768 } else {
2769 DHD_INFO(("%s: noted %s update, value now %d\n",
2770 __func__, name, bus->sd_mode));
2771 }
2772 }
2773 /* Similar check for blocksize change */
2774 if (set && strcmp(name, "sd_blocksize") == 0) {
2775 s32 fnum = 2;
2776 if (bcmsdh_iovar_op
2777 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2778 &bus->blocksize, sizeof(s32),
2779 false) != BCME_OK) {
2780 bus->blocksize = 0;
2781 DHD_ERROR(("%s: fail on %s get\n", __func__,
2782 "sd_blocksize"));
2783 } else {
2784 DHD_INFO(("%s: noted %s update, value now %d\n",
2785 __func__, "sd_blocksize",
2786 bus->blocksize));
2787 }
2788 }
2789 bus->roundup = min(max_roundup, bus->blocksize);
2790
2791 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2792 bus->activity = false;
2793 dhdsdio_clkctl(bus, CLK_NONE, true);
2794 }
2795
2796 dhd_os_sdunlock(bus->dhd);
2797 goto exit;
2798 }
2799
2800 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2801 name, (set ? "set" : "get"), len, plen));
2802
2803 /* set up 'params' pointer in case this is a set command so that
2804 * the convenience int and bool code can be common to set and get
2805 */
2806 if (params == NULL) {
2807 params = arg;
2808 plen = len;
2809 }
2810
2811 if (vi->type == IOVT_VOID)
2812 val_size = 0;
2813 else if (vi->type == IOVT_BUFFER)
2814 val_size = len;
2815 else
2816 /* all other types are integer sized */
2817 val_size = sizeof(int);
2818
2819 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2820 bcmerror =
2821 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2822 val_size);
2823
2824 exit:
2825 return bcmerror;
2826 }
2827
2828 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2829 {
2830 struct osl_info *osh = bus->dhd->osh;
2831 u32 local_hostintmask;
2832 u8 saveclk;
2833 uint retries;
2834 int err;
2835
2836 DHD_TRACE(("%s: Enter\n", __func__));
2837
2838 if (enforce_mutex)
2839 dhd_os_sdlock(bus->dhd);
2840
2841 BUS_WAKE(bus);
2842
2843 /* Enable clock for device interrupts */
2844 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2845
2846 /* Disable and clear interrupts at the chip level also */
2847 W_SDREG(0, &bus->regs->hostintmask, retries);
2848 local_hostintmask = bus->hostintmask;
2849 bus->hostintmask = 0;
2850
2851 /* Change our idea of bus state */
2852 bus->dhd->busstate = DHD_BUS_DOWN;
2853
2854 /* Force clocks on backplane to be sure F2 interrupt propagates */
2855 saveclk =
2856 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2857 &err);
2858 if (!err) {
2859 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2860 (saveclk | SBSDIO_FORCE_HT), &err);
2861 }
2862 if (err) {
2863 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2864 __func__, err));
2865 }
2866
2867 /* Turn off the bus (F2), free any pending packets */
2868 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2869 bcmsdh_intr_disable(bus->sdh);
2870 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2871 SDIO_FUNC_ENABLE_1, NULL);
2872
2873 /* Clear any pending interrupts now that F2 is disabled */
2874 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2875
2876 /* Turn off the backplane clock (only) */
2877 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2878
2879 /* Clear the data packet queues */
2880 pktq_flush(osh, &bus->txq, true);
2881
2882 /* Clear any held glomming stuff */
2883 if (bus->glomd)
2884 pkt_buf_free_skb(osh, bus->glomd, false);
2885
2886 if (bus->glom)
2887 pkt_buf_free_skb(osh, bus->glom, false);
2888
2889 bus->glom = bus->glomd = NULL;
2890
2891 /* Clear rx control and wake any waiters */
2892 bus->rxlen = 0;
2893 dhd_os_ioctl_resp_wake(bus->dhd);
2894
2895 /* Reset some F2 state stuff */
2896 bus->rxskip = false;
2897 bus->tx_seq = bus->rx_seq = 0;
2898
2899 if (enforce_mutex)
2900 dhd_os_sdunlock(bus->dhd);
2901 }
2902
2903 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2904 {
2905 dhd_bus_t *bus = dhdp->bus;
2906 dhd_timeout_t tmo;
2907 uint retries = 0;
2908 u8 ready, enable;
2909 int err, ret = 0;
2910 u8 saveclk;
2911
2912 DHD_TRACE(("%s: Enter\n", __func__));
2913
2914 ASSERT(bus->dhd);
2915 if (!bus->dhd)
2916 return 0;
2917
2918 if (enforce_mutex)
2919 dhd_os_sdlock(bus->dhd);
2920
2921 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2922 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2923 if (bus->clkstate != CLK_AVAIL)
2924 goto exit;
2925
2926 /* Force clocks on backplane to be sure F2 interrupt propagates */
2927 saveclk =
2928 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2929 &err);
2930 if (!err) {
2931 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2932 (saveclk | SBSDIO_FORCE_HT), &err);
2933 }
2934 if (err) {
2935 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2936 __func__, err));
2937 goto exit;
2938 }
2939
2940 /* Enable function 2 (frame transfers) */
2941 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2942 &bus->regs->tosbmailboxdata, retries);
2943 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2944
2945 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2946
2947 /* Give the dongle some time to do its thing and set IOR2 */
2948 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2949
2950 ready = 0;
2951 while (ready != enable && !dhd_timeout_expired(&tmo))
2952 ready =
2953 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2954 NULL);
2955
2956 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2957 __func__, enable, ready, tmo.elapsed));
2958
2959 /* If F2 successfully enabled, set core and enable interrupts */
2960 if (ready == enable) {
2961 /* Make sure we're talking to the core. */
2962 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2963 if (!(bus->regs))
2964 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2965
2966 /* Set up the interrupt mask and enable interrupts */
2967 bus->hostintmask = HOSTINTMASK;
2968 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2969
2970 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2971 (u8) watermark, &err);
2972
2973 /* Set bus state according to enable result */
2974 dhdp->busstate = DHD_BUS_DATA;
2975
2976 /* bcmsdh_intr_unmask(bus->sdh); */
2977
2978 bus->intdis = false;
2979 if (bus->intr) {
2980 DHD_INTR(("%s: enable SDIO device interrupts\n",
2981 __func__));
2982 bcmsdh_intr_enable(bus->sdh);
2983 } else {
2984 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2985 bcmsdh_intr_disable(bus->sdh);
2986 }
2987
2988 }
2989
2990 else {
2991 /* Disable F2 again */
2992 enable = SDIO_FUNC_ENABLE_1;
2993 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2994 NULL);
2995 }
2996
2997 /* Restore previous clock setting */
2998 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2999 saveclk, &err);
3000
3001 /* If we didn't come up, turn off backplane clock */
3002 if (dhdp->busstate != DHD_BUS_DATA)
3003 dhdsdio_clkctl(bus, CLK_NONE, false);
3004
3005 exit:
3006 if (enforce_mutex)
3007 dhd_os_sdunlock(bus->dhd);
3008
3009 return ret;
3010 }
3011
3012 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3013 {
3014 bcmsdh_info_t *sdh = bus->sdh;
3015 sdpcmd_regs_t *regs = bus->regs;
3016 uint retries = 0;
3017 u16 lastrbc;
3018 u8 hi, lo;
3019 int err;
3020
3021 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3022 (abort ? "abort command, " : ""),
3023 (rtx ? ", send NAK" : "")));
3024
3025 if (abort)
3026 bcmsdh_abort(sdh, SDIO_FUNC_2);
3027
3028 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3029 &err);
3030 bus->f1regdata++;
3031
3032 /* Wait until the packet has been flushed (device/FIFO stable) */
3033 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3034 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3035 NULL);
3036 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3037 NULL);
3038 bus->f1regdata += 2;
3039
3040 if ((hi == 0) && (lo == 0))
3041 break;
3042
3043 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3044 DHD_ERROR(("%s: count growing: last 0x%04x now "
3045 "0x%04x\n",
3046 __func__, lastrbc, ((hi << 8) + lo)));
3047 }
3048 lastrbc = (hi << 8) + lo;
3049 }
3050
3051 if (!retries) {
3052 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3053 __func__, lastrbc));
3054 } else {
3055 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3056 (0xffff - retries)));
3057 }
3058
3059 if (rtx) {
3060 bus->rxrtx++;
3061 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3062 bus->f1regdata++;
3063 if (retries <= retry_limit)
3064 bus->rxskip = true;
3065 }
3066
3067 /* Clear partial in any case */
3068 bus->nextlen = 0;
3069
3070 /* If we can't reach the device, signal failure */
3071 if (err || bcmsdh_regfail(sdh))
3072 bus->dhd->busstate = DHD_BUS_DOWN;
3073 }
3074
3075 static void
3076 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3077 {
3078 bcmsdh_info_t *sdh = bus->sdh;
3079 uint rdlen, pad;
3080
3081 int sdret;
3082
3083 DHD_TRACE(("%s: Enter\n", __func__));
3084
3085 /* Control data already received in aligned rxctl */
3086 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3087 goto gotpkt;
3088
3089 ASSERT(bus->rxbuf);
3090 /* Set rxctl for frame (w/optional alignment) */
3091 bus->rxctl = bus->rxbuf;
3092 if (dhd_alignctl) {
3093 bus->rxctl += firstread;
3094 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3095 if (pad)
3096 bus->rxctl += (DHD_SDALIGN - pad);
3097 bus->rxctl -= firstread;
3098 }
3099 ASSERT(bus->rxctl >= bus->rxbuf);
3100
3101 /* Copy the already-read portion over */
3102 bcopy(hdr, bus->rxctl, firstread);
3103 if (len <= firstread)
3104 goto gotpkt;
3105
3106 /* Copy the full data pkt in gSPI case and process ioctl. */
3107 if (bus->bus == SPI_BUS) {
3108 bcopy(hdr, bus->rxctl, len);
3109 goto gotpkt;
3110 }
3111
3112 /* Raise rdlen to next SDIO block to avoid tail command */
3113 rdlen = len - firstread;
3114 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3115 pad = bus->blocksize - (rdlen % bus->blocksize);
3116 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3117 ((len + pad) < bus->dhd->maxctl))
3118 rdlen += pad;
3119 } else if (rdlen % DHD_SDALIGN) {
3120 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3121 }
3122
3123 /* Satisfy length-alignment requirements */
3124 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3125 rdlen = roundup(rdlen, ALIGNMENT);
3126
3127 /* Drop if the read is too big or it exceeds our maximum */
3128 if ((rdlen + firstread) > bus->dhd->maxctl) {
3129 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3130 __func__, rdlen, bus->dhd->maxctl));
3131 bus->dhd->rx_errors++;
3132 dhdsdio_rxfail(bus, false, false);
3133 goto done;
3134 }
3135
3136 if ((len - doff) > bus->dhd->maxctl) {
3137 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3138 "%d-byte limit\n",
3139 __func__, len, (len - doff), bus->dhd->maxctl));
3140 bus->dhd->rx_errors++;
3141 bus->rx_toolong++;
3142 dhdsdio_rxfail(bus, false, false);
3143 goto done;
3144 }
3145
3146 /* Read remainder of frame body into the rxctl buffer */
3147 sdret =
3148 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3149 (bus->rxctl + firstread), rdlen, NULL, NULL,
3150 NULL);
3151 bus->f2rxdata++;
3152 ASSERT(sdret != BCME_PENDING);
3153
3154 /* Control frame failures need retransmission */
3155 if (sdret < 0) {
3156 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3157 __func__, rdlen, sdret));
3158 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3159 dhdsdio_rxfail(bus, true, true);
3160 goto done;
3161 }
3162
3163 gotpkt:
3164
3165 #ifdef DHD_DEBUG
3166 if (DHD_BYTES_ON() && DHD_CTL_ON())
3167 prhex("RxCtrl", bus->rxctl, len);
3168 #endif
3169
3170 /* Point to valid data and indicate its length */
3171 bus->rxctl += doff;
3172 bus->rxlen = len - doff;
3173
3174 done:
3175 /* Awake any waiters */
3176 dhd_os_ioctl_resp_wake(bus->dhd);
3177 }
3178
3179 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3180 {
3181 u16 dlen, totlen;
3182 u8 *dptr, num = 0;
3183
3184 u16 sublen, check;
3185 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3186 struct osl_info *osh = bus->dhd->osh;
3187
3188 int errcode;
3189 u8 chan, seq, doff, sfdoff;
3190 u8 txmax;
3191
3192 int ifidx = 0;
3193 bool usechain = bus->use_rxchain;
3194
3195 /* If packets, issue read(s) and send up packet chain */
3196 /* Return sequence numbers consumed? */
3197
3198 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3199 bus->glom));
3200
3201 /* If there's a descriptor, generate the packet chain */
3202 if (bus->glomd) {
3203 dhd_os_sdlock_rxq(bus->dhd);
3204
3205 pfirst = plast = pnext = NULL;
3206 dlen = (u16) (bus->glomd->len);
3207 dptr = bus->glomd->data;
3208 if (!dlen || (dlen & 1)) {
3209 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3210 __func__, dlen));
3211 dlen = 0;
3212 }
3213
3214 for (totlen = num = 0; dlen; num++) {
3215 /* Get (and move past) next length */
3216 sublen = ltoh16_ua(dptr);
3217 dlen -= sizeof(u16);
3218 dptr += sizeof(u16);
3219 if ((sublen < SDPCM_HDRLEN) ||
3220 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3221 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3222 __func__, num, sublen));
3223 pnext = NULL;
3224 break;
3225 }
3226 if (sublen % DHD_SDALIGN) {
3227 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3228 __func__, sublen, DHD_SDALIGN));
3229 usechain = false;
3230 }
3231 totlen += sublen;
3232
3233 /* For last frame, adjust read len so total
3234 is a block multiple */
3235 if (!dlen) {
3236 sublen +=
3237 (roundup(totlen, bus->blocksize) - totlen);
3238 totlen = roundup(totlen, bus->blocksize);
3239 }
3240
3241 /* Allocate/chain packet for next subframe */
3242 pnext = pkt_buf_get_skb(osh, sublen + DHD_SDALIGN);
3243 if (pnext == NULL) {
3244 DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3245 __func__, num, sublen));
3246 break;
3247 }
3248 ASSERT(!(pnext->prev));
3249 if (!pfirst) {
3250 ASSERT(!plast);
3251 pfirst = plast = pnext;
3252 } else {
3253 ASSERT(plast);
3254 plast->next = pnext;
3255 plast = pnext;
3256 }
3257
3258 /* Adhere to start alignment requirements */
3259 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3260 }
3261
3262 /* If all allocations succeeded, save packet chain
3263 in bus structure */
3264 if (pnext) {
3265 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3266 "subframes\n", __func__, totlen, num));
3267 if (DHD_GLOM_ON() && bus->nextlen) {
3268 if (totlen != bus->nextlen) {
3269 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3270 __func__, bus->nextlen,
3271 totlen, rxseq));
3272 }
3273 }
3274 bus->glom = pfirst;
3275 pfirst = pnext = NULL;
3276 } else {
3277 if (pfirst)
3278 pkt_buf_free_skb(osh, pfirst, false);
3279 bus->glom = NULL;
3280 num = 0;
3281 }
3282
3283 /* Done with descriptor packet */
3284 pkt_buf_free_skb(osh, bus->glomd, false);
3285 bus->glomd = NULL;
3286 bus->nextlen = 0;
3287
3288 dhd_os_sdunlock_rxq(bus->dhd);
3289 }
3290
3291 /* Ok -- either we just generated a packet chain,
3292 or had one from before */
3293 if (bus->glom) {
3294 if (DHD_GLOM_ON()) {
3295 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3296 __func__));
3297 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3298 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3299 pnext, (u8 *) (pnext->data),
3300 pnext->len, pnext->len));
3301 }
3302 }
3303
3304 pfirst = bus->glom;
3305 dlen = (u16) pkttotlen(osh, pfirst);
3306
3307 /* Do an SDIO read for the superframe. Configurable iovar to
3308 * read directly into the chained packet, or allocate a large
3309 * packet and and copy into the chain.
3310 */
3311 if (usechain) {
3312 errcode = dhd_bcmsdh_recv_buf(bus,
3313 bcmsdh_cur_sbwad
3314 (bus->sdh), SDIO_FUNC_2,
3315 F2SYNC,
3316 (u8 *) pfirst->data,
3317 dlen, pfirst, NULL, NULL);
3318 } else if (bus->dataptr) {
3319 errcode = dhd_bcmsdh_recv_buf(bus,
3320 bcmsdh_cur_sbwad
3321 (bus->sdh), SDIO_FUNC_2,
3322 F2SYNC, bus->dataptr,
3323 dlen, NULL, NULL, NULL);
3324 sublen =
3325 (u16) pktfrombuf(osh, pfirst, 0, dlen,
3326 bus->dataptr);
3327 if (sublen != dlen) {
3328 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3329 __func__, dlen, sublen));
3330 errcode = -1;
3331 }
3332 pnext = NULL;
3333 } else {
3334 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3335 dlen));
3336 errcode = -1;
3337 }
3338 bus->f2rxdata++;
3339 ASSERT(errcode != BCME_PENDING);
3340
3341 /* On failure, kill the superframe, allow a couple retries */
3342 if (errcode < 0) {
3343 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3344 __func__, dlen, errcode));
3345 bus->dhd->rx_errors++;
3346
3347 if (bus->glomerr++ < 3) {
3348 dhdsdio_rxfail(bus, true, true);
3349 } else {
3350 bus->glomerr = 0;
3351 dhdsdio_rxfail(bus, true, false);
3352 dhd_os_sdlock_rxq(bus->dhd);
3353 pkt_buf_free_skb(osh, bus->glom, false);
3354 dhd_os_sdunlock_rxq(bus->dhd);
3355 bus->rxglomfail++;
3356 bus->glom = NULL;
3357 }
3358 return 0;
3359 }
3360 #ifdef DHD_DEBUG
3361 if (DHD_GLOM_ON()) {
3362 prhex("SUPERFRAME", pfirst->data,
3363 min_t(int, pfirst->len, 48));
3364 }
3365 #endif
3366
3367 /* Validate the superframe header */
3368 dptr = (u8 *) (pfirst->data);
3369 sublen = ltoh16_ua(dptr);
3370 check = ltoh16_ua(dptr + sizeof(u16));
3371
3372 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3373 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3374 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3375 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3376 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3377 __func__, bus->nextlen, seq));
3378 bus->nextlen = 0;
3379 }
3380 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3381 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3382
3383 errcode = 0;
3384 if ((u16)~(sublen ^ check)) {
3385 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3386 "0x%04x/0x%04x\n", __func__, sublen, check));
3387 errcode = -1;
3388 } else if (roundup(sublen, bus->blocksize) != dlen) {
3389 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3390 "0x%04x, expect 0x%04x\n",
3391 __func__, sublen,
3392 roundup(sublen, bus->blocksize), dlen));
3393 errcode = -1;
3394 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3395 SDPCM_GLOM_CHANNEL) {
3396 DHD_ERROR(("%s (superframe): bad channel %d\n",
3397 __func__,
3398 SDPCM_PACKET_CHANNEL(&dptr
3399 [SDPCM_FRAMETAG_LEN])));
3400 errcode = -1;
3401 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3402 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3403 __func__));
3404 errcode = -1;
3405 } else if ((doff < SDPCM_HDRLEN) ||
3406 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3407 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3408 "pkt %d min %d\n",
3409 __func__, doff, sublen,
3410 pfirst->len, SDPCM_HDRLEN));
3411 errcode = -1;
3412 }
3413
3414 /* Check sequence number of superframe SW header */
3415 if (rxseq != seq) {
3416 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3417 __func__, seq, rxseq));
3418 bus->rx_badseq++;
3419 rxseq = seq;
3420 }
3421
3422 /* Check window for sanity */
3423 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3424 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3425 __func__, txmax, bus->tx_seq));
3426 txmax = bus->tx_seq + 2;
3427 }
3428 bus->tx_max = txmax;
3429
3430 /* Remove superframe header, remember offset */
3431 skb_pull(pfirst, doff);
3432 sfdoff = doff;
3433
3434 /* Validate all the subframe headers */
3435 for (num = 0, pnext = pfirst; pnext && !errcode;
3436 num++, pnext = pnext->next) {
3437 dptr = (u8 *) (pnext->data);
3438 dlen = (u16) (pnext->len);
3439 sublen = ltoh16_ua(dptr);
3440 check = ltoh16_ua(dptr + sizeof(u16));
3441 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3442 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3443 #ifdef DHD_DEBUG
3444 if (DHD_GLOM_ON())
3445 prhex("subframe", dptr, 32);
3446 #endif
3447
3448 if ((u16)~(sublen ^ check)) {
3449 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3450 "len/check 0x%04x/0x%04x\n",
3451 __func__, num, sublen, check));
3452 errcode = -1;
3453 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3454 DHD_ERROR(("%s (subframe %d): length mismatch: "
3455 "len 0x%04x, expect 0x%04x\n",
3456 __func__, num, sublen, dlen));
3457 errcode = -1;
3458 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3459 (chan != SDPCM_EVENT_CHANNEL)) {
3460 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3461 __func__, num, chan));
3462 errcode = -1;
3463 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3464 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3465 __func__, num, doff, sublen,
3466 SDPCM_HDRLEN));
3467 errcode = -1;
3468 }
3469 }
3470
3471 if (errcode) {
3472 /* Terminate frame on error, request
3473 a couple retries */
3474 if (bus->glomerr++ < 3) {
3475 /* Restore superframe header space */
3476 skb_push(pfirst, sfdoff);
3477 dhdsdio_rxfail(bus, true, true);
3478 } else {
3479 bus->glomerr = 0;
3480 dhdsdio_rxfail(bus, true, false);
3481 dhd_os_sdlock_rxq(bus->dhd);
3482 pkt_buf_free_skb(osh, bus->glom, false);
3483 dhd_os_sdunlock_rxq(bus->dhd);
3484 bus->rxglomfail++;
3485 bus->glom = NULL;
3486 }
3487 bus->nextlen = 0;
3488 return 0;
3489 }
3490
3491 /* Basic SD framing looks ok - process each packet (header) */
3492 save_pfirst = pfirst;
3493 bus->glom = NULL;
3494 plast = NULL;
3495
3496 dhd_os_sdlock_rxq(bus->dhd);
3497 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3498 pnext = pfirst->next;
3499 pfirst->next = NULL;
3500
3501 dptr = (u8 *) (pfirst->data);
3502 sublen = ltoh16_ua(dptr);
3503 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3504 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3505 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3506
3507 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3508 "chan %d seq %d\n",
3509 __func__, num, pfirst, pfirst->data,
3510 pfirst->len, sublen, chan, seq));
3511
3512 ASSERT((chan == SDPCM_DATA_CHANNEL)
3513 || (chan == SDPCM_EVENT_CHANNEL));
3514
3515 if (rxseq != seq) {
3516 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3517 __func__, seq, rxseq));
3518 bus->rx_badseq++;
3519 rxseq = seq;
3520 }
3521 #ifdef DHD_DEBUG
3522 if (DHD_BYTES_ON() && DHD_DATA_ON())
3523 prhex("Rx Subframe Data", dptr, dlen);
3524 #endif
3525
3526 __skb_trim(pfirst, sublen);
3527 skb_pull(pfirst, doff);
3528
3529 if (pfirst->len == 0) {
3530 pkt_buf_free_skb(bus->dhd->osh, pfirst, false);
3531 if (plast) {
3532 plast->next = pnext;
3533 } else {
3534 ASSERT(save_pfirst == pfirst);
3535 save_pfirst = pnext;
3536 }
3537 continue;
3538 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3539 0) {
3540 DHD_ERROR(("%s: rx protocol error\n",
3541 __func__));
3542 bus->dhd->rx_errors++;
3543 pkt_buf_free_skb(osh, pfirst, false);
3544 if (plast) {
3545 plast->next = pnext;
3546 } else {
3547 ASSERT(save_pfirst == pfirst);
3548 save_pfirst = pnext;
3549 }
3550 continue;
3551 }
3552
3553 /* this packet will go up, link back into
3554 chain and count it */
3555 pfirst->next = pnext;
3556 plast = pfirst;
3557 num++;
3558
3559 #ifdef DHD_DEBUG
3560 if (DHD_GLOM_ON()) {
3561 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3562 "nxt/lnk %p/%p\n",
3563 __func__, num, pfirst, pfirst->data,
3564 pfirst->len, pfirst->next,
3565 pfirst->prev));
3566 prhex("", (u8 *) pfirst->data,
3567 min_t(int, pfirst->len, 32));
3568 }
3569 #endif /* DHD_DEBUG */
3570 }
3571 dhd_os_sdunlock_rxq(bus->dhd);
3572 if (num) {
3573 dhd_os_sdunlock(bus->dhd);
3574 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3575 dhd_os_sdlock(bus->dhd);
3576 }
3577
3578 bus->rxglomframes++;
3579 bus->rxglompkts += num;
3580 }
3581 return num;
3582 }
3583
3584 /* Return true if there may be more frames to read */
3585 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3586 {
3587 struct osl_info *osh = bus->dhd->osh;
3588 bcmsdh_info_t *sdh = bus->sdh;
3589
3590 u16 len, check; /* Extracted hardware header fields */
3591 u8 chan, seq, doff; /* Extracted software header fields */
3592 u8 fcbits; /* Extracted fcbits from software header */
3593 u8 delta;
3594
3595 struct sk_buff *pkt; /* Packet for event or data frames */
3596 u16 pad; /* Number of pad bytes to read */
3597 u16 rdlen; /* Total number of bytes to read */
3598 u8 rxseq; /* Next sequence number to expect */
3599 uint rxleft = 0; /* Remaining number of frames allowed */
3600 int sdret; /* Return code from bcmsdh calls */
3601 u8 txmax; /* Maximum tx sequence offered */
3602 bool len_consistent; /* Result of comparing readahead len and
3603 len from hw-hdr */
3604 u8 *rxbuf;
3605 int ifidx = 0;
3606 uint rxcount = 0; /* Total frames read */
3607
3608 #if defined(DHD_DEBUG) || defined(SDTEST)
3609 bool sdtest = false; /* To limit message spew from test mode */
3610 #endif
3611
3612 DHD_TRACE(("%s: Enter\n", __func__));
3613
3614 ASSERT(maxframes);
3615
3616 #ifdef SDTEST
3617 /* Allow pktgen to override maxframes */
3618 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3619 maxframes = bus->pktgen_count;
3620 sdtest = true;
3621 }
3622 #endif
3623
3624 /* Not finished unless we encounter no more frames indication */
3625 *finished = false;
3626
3627 for (rxseq = bus->rx_seq, rxleft = maxframes;
3628 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3629 rxseq++, rxleft--) {
3630
3631 /* Handle glomming separately */
3632 if (bus->glom || bus->glomd) {
3633 u8 cnt;
3634 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3635 __func__, bus->glomd, bus->glom));
3636 cnt = dhdsdio_rxglom(bus, rxseq);
3637 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3638 rxseq += cnt - 1;
3639 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3640 continue;
3641 }
3642
3643 /* Try doing single read if we can */
3644 if (dhd_readahead && bus->nextlen) {
3645 u16 nextlen = bus->nextlen;
3646 bus->nextlen = 0;
3647
3648 if (bus->bus == SPI_BUS) {
3649 rdlen = len = nextlen;
3650 } else {
3651 rdlen = len = nextlen << 4;
3652
3653 /* Pad read to blocksize for efficiency */
3654 if (bus->roundup && bus->blocksize
3655 && (rdlen > bus->blocksize)) {
3656 pad =
3657 bus->blocksize -
3658 (rdlen % bus->blocksize);
3659 if ((pad <= bus->roundup)
3660 && (pad < bus->blocksize)
3661 && ((rdlen + pad + firstread) <
3662 MAX_RX_DATASZ))
3663 rdlen += pad;
3664 } else if (rdlen % DHD_SDALIGN) {
3665 rdlen +=
3666 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3667 }
3668 }
3669
3670 /* We use bus->rxctl buffer in WinXP for initial
3671 * control pkt receives.
3672 * Later we use buffer-poll for data as well
3673 * as control packets.
3674 * This is required becuase dhd receives full
3675 * frame in gSPI unlike SDIO.
3676 * After the frame is received we have to
3677 * distinguish whether it is data
3678 * or non-data frame.
3679 */
3680 /* Allocate a packet buffer */
3681 dhd_os_sdlock_rxq(bus->dhd);
3682 pkt = pkt_buf_get_skb(osh, rdlen + DHD_SDALIGN);
3683 if (!pkt) {
3684 if (bus->bus == SPI_BUS) {
3685 bus->usebufpool = false;
3686 bus->rxctl = bus->rxbuf;
3687 if (dhd_alignctl) {
3688 bus->rxctl += firstread;
3689 pad = ((unsigned long)bus->rxctl %
3690 DHD_SDALIGN);
3691 if (pad)
3692 bus->rxctl +=
3693 (DHD_SDALIGN - pad);
3694 bus->rxctl -= firstread;
3695 }
3696 ASSERT(bus->rxctl >= bus->rxbuf);
3697 rxbuf = bus->rxctl;
3698 /* Read the entire frame */
3699 sdret = dhd_bcmsdh_recv_buf(bus,
3700 bcmsdh_cur_sbwad
3701 (sdh),
3702 SDIO_FUNC_2,
3703 F2SYNC,
3704 rxbuf,
3705 rdlen, NULL,
3706 NULL, NULL);
3707 bus->f2rxdata++;
3708 ASSERT(sdret != BCME_PENDING);
3709
3710 /* Control frame failures need
3711 retransmission */
3712 if (sdret < 0) {
3713 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3714 __func__,
3715 rdlen, sdret));
3716 /* dhd.rx_ctlerrs is higher */
3717 bus->rxc_errors++;
3718 dhd_os_sdunlock_rxq(bus->dhd);
3719 dhdsdio_rxfail(bus, true,
3720 (bus->bus ==
3721 SPI_BUS) ? false
3722 : true);
3723 continue;
3724 }
3725 } else {
3726 /* Give up on data,
3727 request rtx of events */
3728 DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3729 __func__, len, rdlen, rxseq));
3730 /* Just go try again w/normal
3731 header read */
3732 dhd_os_sdunlock_rxq(bus->dhd);
3733 continue;
3734 }
3735 } else {
3736 if (bus->bus == SPI_BUS)
3737 bus->usebufpool = true;
3738
3739 ASSERT(!(pkt->prev));
3740 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3741 rxbuf = (u8 *) (pkt->data);
3742 /* Read the entire frame */
3743 sdret =
3744 dhd_bcmsdh_recv_buf(bus,
3745 bcmsdh_cur_sbwad(sdh),
3746 SDIO_FUNC_2, F2SYNC,
3747 rxbuf, rdlen, pkt, NULL,
3748 NULL);
3749 bus->f2rxdata++;
3750 ASSERT(sdret != BCME_PENDING);
3751
3752 if (sdret < 0) {
3753 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3754 __func__, rdlen, sdret));
3755 pkt_buf_free_skb(bus->dhd->osh, pkt, false);
3756 bus->dhd->rx_errors++;
3757 dhd_os_sdunlock_rxq(bus->dhd);
3758 /* Force retry w/normal header read.
3759 * Don't attemp NAK for
3760 * gSPI
3761 */
3762 dhdsdio_rxfail(bus, true,
3763 (bus->bus ==
3764 SPI_BUS) ? false :
3765 true);
3766 continue;
3767 }
3768 }
3769 dhd_os_sdunlock_rxq(bus->dhd);
3770
3771 /* Now check the header */
3772 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3773
3774 /* Extract hardware header fields */
3775 len = ltoh16_ua(bus->rxhdr);
3776 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3777
3778 /* All zeros means readahead info was bad */
3779 if (!(len | check)) {
3780 DHD_INFO(("%s (nextlen): read zeros in HW "
3781 "header???\n", __func__));
3782 dhd_os_sdlock_rxq(bus->dhd);
3783 PKTFREE2();
3784 dhd_os_sdunlock_rxq(bus->dhd);
3785 GSPI_PR55150_BAILOUT;
3786 continue;
3787 }
3788
3789 /* Validate check bytes */
3790 if ((u16)~(len ^ check)) {
3791 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3792 __func__, nextlen, len, check));
3793 dhd_os_sdlock_rxq(bus->dhd);
3794 PKTFREE2();
3795 dhd_os_sdunlock_rxq(bus->dhd);
3796 bus->rx_badhdr++;
3797 dhdsdio_rxfail(bus, false, false);
3798 GSPI_PR55150_BAILOUT;
3799 continue;
3800 }
3801
3802 /* Validate frame length */
3803 if (len < SDPCM_HDRLEN) {
3804 DHD_ERROR(("%s (nextlen): HW hdr length "
3805 "invalid: %d\n", __func__, len));
3806 dhd_os_sdlock_rxq(bus->dhd);
3807 PKTFREE2();
3808 dhd_os_sdunlock_rxq(bus->dhd);
3809 GSPI_PR55150_BAILOUT;
3810 continue;
3811 }
3812
3813 /* Check for consistency withreadahead info */
3814 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3815 if (len_consistent) {
3816 /* Mismatch, force retry w/normal
3817 header (may be >4K) */
3818 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3819 __func__, nextlen,
3820 len, roundup(len, 16), rxseq));
3821 dhd_os_sdlock_rxq(bus->dhd);
3822 PKTFREE2();
3823 dhd_os_sdunlock_rxq(bus->dhd);
3824 dhdsdio_rxfail(bus, true,
3825 (bus->bus ==
3826 SPI_BUS) ? false : true);
3827 GSPI_PR55150_BAILOUT;
3828 continue;
3829 }
3830
3831 /* Extract software header fields */
3832 chan =
3833 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3834 [SDPCM_FRAMETAG_LEN]);
3835 seq =
3836 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3837 [SDPCM_FRAMETAG_LEN]);
3838 doff =
3839 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3840 [SDPCM_FRAMETAG_LEN]);
3841 txmax =
3842 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3843
3844 bus->nextlen =
3845 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3846 SDPCM_NEXTLEN_OFFSET];
3847 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3848 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3849 __func__, bus->nextlen, seq));
3850 bus->nextlen = 0;
3851 }
3852
3853 bus->dhd->rx_readahead_cnt++;
3854 /* Handle Flow Control */
3855 fcbits =
3856 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3857
3858 delta = 0;
3859 if (~bus->flowcontrol & fcbits) {
3860 bus->fc_xoff++;
3861 delta = 1;
3862 }
3863 if (bus->flowcontrol & ~fcbits) {
3864 bus->fc_xon++;
3865 delta = 1;
3866 }
3867
3868 if (delta) {
3869 bus->fc_rcvd++;
3870 bus->flowcontrol = fcbits;
3871 }
3872
3873 /* Check and update sequence number */
3874 if (rxseq != seq) {
3875 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3876 "%d\n", __func__, seq, rxseq));
3877 bus->rx_badseq++;
3878 rxseq = seq;
3879 }
3880
3881 /* Check window for sanity */
3882 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3883 DHD_ERROR(("%s: got unlikely tx max %d with "
3884 "tx_seq %d\n",
3885 __func__, txmax, bus->tx_seq));
3886 txmax = bus->tx_seq + 2;
3887 }
3888 bus->tx_max = txmax;
3889
3890 #ifdef DHD_DEBUG
3891 if (DHD_BYTES_ON() && DHD_DATA_ON())
3892 prhex("Rx Data", rxbuf, len);
3893 else if (DHD_HDRS_ON())
3894 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3895 #endif
3896
3897 if (chan == SDPCM_CONTROL_CHANNEL) {
3898 if (bus->bus == SPI_BUS) {
3899 dhdsdio_read_control(bus, rxbuf, len,
3900 doff);
3901 if (bus->usebufpool) {
3902 dhd_os_sdlock_rxq(bus->dhd);
3903 pkt_buf_free_skb(bus->dhd->osh, pkt,
3904 false);
3905 dhd_os_sdunlock_rxq(bus->dhd);
3906 }
3907 continue;
3908 } else {
3909 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3910 __func__, seq));
3911 /* Force retry w/normal header read */
3912 bus->nextlen = 0;
3913 dhdsdio_rxfail(bus, false, true);
3914 dhd_os_sdlock_rxq(bus->dhd);
3915 PKTFREE2();
3916 dhd_os_sdunlock_rxq(bus->dhd);
3917 continue;
3918 }
3919 }
3920
3921 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3922 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3923 len, chan));
3924 continue;
3925 }
3926
3927 /* Validate data offset */
3928 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3929 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3930 __func__, doff, len, SDPCM_HDRLEN));
3931 dhd_os_sdlock_rxq(bus->dhd);
3932 PKTFREE2();
3933 dhd_os_sdunlock_rxq(bus->dhd);
3934 ASSERT(0);
3935 dhdsdio_rxfail(bus, false, false);
3936 continue;
3937 }
3938
3939 /* All done with this one -- now deliver the packet */
3940 goto deliver;
3941 }
3942 /* gSPI frames should not be handled in fractions */
3943 if (bus->bus == SPI_BUS)
3944 break;
3945
3946 /* Read frame header (hardware and software) */
3947 sdret =
3948 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3949 F2SYNC, bus->rxhdr, firstread, NULL,
3950 NULL, NULL);
3951 bus->f2rxhdrs++;
3952 ASSERT(sdret != BCME_PENDING);
3953
3954 if (sdret < 0) {
3955 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3956 sdret));
3957 bus->rx_hdrfail++;
3958 dhdsdio_rxfail(bus, true, true);
3959 continue;
3960 }
3961 #ifdef DHD_DEBUG
3962 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3963 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3964 #endif
3965
3966 /* Extract hardware header fields */
3967 len = ltoh16_ua(bus->rxhdr);
3968 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3969
3970 /* All zeros means no more frames */
3971 if (!(len | check)) {
3972 *finished = true;
3973 break;
3974 }
3975
3976 /* Validate check bytes */
3977 if ((u16) ~(len ^ check)) {
3978 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3979 __func__, len, check));
3980 bus->rx_badhdr++;
3981 dhdsdio_rxfail(bus, false, false);
3982 continue;
3983 }
3984
3985 /* Validate frame length */
3986 if (len < SDPCM_HDRLEN) {
3987 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3988 __func__, len));
3989 continue;
3990 }
3991
3992 /* Extract software header fields */
3993 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3994 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3995 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3996 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3997
3998 /* Validate data offset */
3999 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4000 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4001 "seq %d\n",
4002 __func__, doff, len, SDPCM_HDRLEN, seq));
4003 bus->rx_badhdr++;
4004 ASSERT(0);
4005 dhdsdio_rxfail(bus, false, false);
4006 continue;
4007 }
4008
4009 /* Save the readahead length if there is one */
4010 bus->nextlen =
4011 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4012 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4013 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4014 "(%d), seq %d\n",
4015 __func__, bus->nextlen, seq));
4016 bus->nextlen = 0;
4017 }
4018
4019 /* Handle Flow Control */
4020 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4021
4022 delta = 0;
4023 if (~bus->flowcontrol & fcbits) {
4024 bus->fc_xoff++;
4025 delta = 1;
4026 }
4027 if (bus->flowcontrol & ~fcbits) {
4028 bus->fc_xon++;
4029 delta = 1;
4030 }
4031
4032 if (delta) {
4033 bus->fc_rcvd++;
4034 bus->flowcontrol = fcbits;
4035 }
4036
4037 /* Check and update sequence number */
4038 if (rxseq != seq) {
4039 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4040 seq, rxseq));
4041 bus->rx_badseq++;
4042 rxseq = seq;
4043 }
4044
4045 /* Check window for sanity */
4046 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4047 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4048 __func__, txmax, bus->tx_seq));
4049 txmax = bus->tx_seq + 2;
4050 }
4051 bus->tx_max = txmax;
4052
4053 /* Call a separate function for control frames */
4054 if (chan == SDPCM_CONTROL_CHANNEL) {
4055 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4056 continue;
4057 }
4058
4059 ASSERT((chan == SDPCM_DATA_CHANNEL)
4060 || (chan == SDPCM_EVENT_CHANNEL)
4061 || (chan == SDPCM_TEST_CHANNEL)
4062 || (chan == SDPCM_GLOM_CHANNEL));
4063
4064 /* Length to read */
4065 rdlen = (len > firstread) ? (len - firstread) : 0;
4066
4067 /* May pad read to blocksize for efficiency */
4068 if (bus->roundup && bus->blocksize &&
4069 (rdlen > bus->blocksize)) {
4070 pad = bus->blocksize - (rdlen % bus->blocksize);
4071 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4072 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4073 rdlen += pad;
4074 } else if (rdlen % DHD_SDALIGN) {
4075 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4076 }
4077
4078 /* Satisfy length-alignment requirements */
4079 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4080 rdlen = roundup(rdlen, ALIGNMENT);
4081
4082 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4083 /* Too long -- skip this frame */
4084 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4085 __func__, len, rdlen));
4086 bus->dhd->rx_errors++;
4087 bus->rx_toolong++;
4088 dhdsdio_rxfail(bus, false, false);
4089 continue;
4090 }
4091
4092 dhd_os_sdlock_rxq(bus->dhd);
4093 pkt = pkt_buf_get_skb(osh, (rdlen + firstread + DHD_SDALIGN));
4094 if (!pkt) {
4095 /* Give up on data, request rtx of events */
4096 DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4097 __func__, rdlen, chan));
4098 bus->dhd->rx_dropped++;
4099 dhd_os_sdunlock_rxq(bus->dhd);
4100 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4101 continue;
4102 }
4103 dhd_os_sdunlock_rxq(bus->dhd);
4104
4105 ASSERT(!(pkt->prev));
4106
4107 /* Leave room for what we already read, and align remainder */
4108 ASSERT(firstread < pkt->len);
4109 skb_pull(pkt, firstread);
4110 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4111
4112 /* Read the remaining frame data */
4113 sdret =
4114 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4115 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4116 pkt, NULL, NULL);
4117 bus->f2rxdata++;
4118 ASSERT(sdret != BCME_PENDING);
4119
4120 if (sdret < 0) {
4121 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4122 __func__, rdlen,
4123 ((chan ==
4124 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4125 SDPCM_DATA_CHANNEL)
4126 ? "data" : "test")),
4127 sdret));
4128 dhd_os_sdlock_rxq(bus->dhd);
4129 pkt_buf_free_skb(bus->dhd->osh, pkt, false);
4130 dhd_os_sdunlock_rxq(bus->dhd);
4131 bus->dhd->rx_errors++;
4132 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4133 continue;
4134 }
4135
4136 /* Copy the already-read portion */
4137 skb_push(pkt, firstread);
4138 bcopy(bus->rxhdr, pkt->data, firstread);
4139
4140 #ifdef DHD_DEBUG
4141 if (DHD_BYTES_ON() && DHD_DATA_ON())
4142 prhex("Rx Data", pkt->data, len);
4143 #endif
4144
4145 deliver:
4146 /* Save superframe descriptor and allocate packet frame */
4147 if (chan == SDPCM_GLOM_CHANNEL) {
4148 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4149 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4150 __func__, len));
4151 #ifdef DHD_DEBUG
4152 if (DHD_GLOM_ON()) {
4153 prhex("Glom Data", pkt->data, len);
4154 }
4155 #endif
4156 __skb_trim(pkt, len);
4157 ASSERT(doff == SDPCM_HDRLEN);
4158 skb_pull(pkt, SDPCM_HDRLEN);
4159 bus->glomd = pkt;
4160 } else {
4161 DHD_ERROR(("%s: glom superframe w/o "
4162 "descriptor!\n", __func__));
4163 dhdsdio_rxfail(bus, false, false);
4164 }
4165 continue;
4166 }
4167
4168 /* Fill in packet len and prio, deliver upward */
4169 __skb_trim(pkt, len);
4170 skb_pull(pkt, doff);
4171
4172 #ifdef SDTEST
4173 /* Test channel packets are processed separately */
4174 if (chan == SDPCM_TEST_CHANNEL) {
4175 dhdsdio_testrcv(bus, pkt, seq);
4176 continue;
4177 }
4178 #endif /* SDTEST */
4179
4180 if (pkt->len == 0) {
4181 dhd_os_sdlock_rxq(bus->dhd);
4182 pkt_buf_free_skb(bus->dhd->osh, pkt, false);
4183 dhd_os_sdunlock_rxq(bus->dhd);
4184 continue;
4185 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4186 DHD_ERROR(("%s: rx protocol error\n", __func__));
4187 dhd_os_sdlock_rxq(bus->dhd);
4188 pkt_buf_free_skb(bus->dhd->osh, pkt, false);
4189 dhd_os_sdunlock_rxq(bus->dhd);
4190 bus->dhd->rx_errors++;
4191 continue;
4192 }
4193
4194 /* Unlock during rx call */
4195 dhd_os_sdunlock(bus->dhd);
4196 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4197 dhd_os_sdlock(bus->dhd);
4198 }
4199 rxcount = maxframes - rxleft;
4200 #ifdef DHD_DEBUG
4201 /* Message if we hit the limit */
4202 if (!rxleft && !sdtest)
4203 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4204 maxframes));
4205 else
4206 #endif /* DHD_DEBUG */
4207 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4208 /* Back off rxseq if awaiting rtx, update rx_seq */
4209 if (bus->rxskip)
4210 rxseq--;
4211 bus->rx_seq = rxseq;
4212
4213 return rxcount;
4214 }
4215
4216 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4217 {
4218 sdpcmd_regs_t *regs = bus->regs;
4219 u32 intstatus = 0;
4220 u32 hmb_data;
4221 u8 fcbits;
4222 uint retries = 0;
4223
4224 DHD_TRACE(("%s: Enter\n", __func__));
4225
4226 /* Read mailbox data and ack that we did so */
4227 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4228 if (retries <= retry_limit)
4229 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4230 bus->f1regdata += 2;
4231
4232 /* Dongle recomposed rx frames, accept them again */
4233 if (hmb_data & HMB_DATA_NAKHANDLED) {
4234 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4235 bus->rx_seq));
4236 if (!bus->rxskip)
4237 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4238
4239 bus->rxskip = false;
4240 intstatus |= I_HMB_FRAME_IND;
4241 }
4242
4243 /*
4244 * DEVREADY does not occur with gSPI.
4245 */
4246 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4247 bus->sdpcm_ver =
4248 (hmb_data & HMB_DATA_VERSION_MASK) >>
4249 HMB_DATA_VERSION_SHIFT;
4250 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4251 DHD_ERROR(("Version mismatch, dongle reports %d, "
4252 "expecting %d\n",
4253 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4254 else
4255 DHD_INFO(("Dongle ready, protocol version %d\n",
4256 bus->sdpcm_ver));
4257 }
4258
4259 /*
4260 * Flow Control has been moved into the RX headers and this out of band
4261 * method isn't used any more. Leae this here for possibly
4262 * remaining backward
4263 * compatible with older dongles
4264 */
4265 if (hmb_data & HMB_DATA_FC) {
4266 fcbits =
4267 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4268
4269 if (fcbits & ~bus->flowcontrol)
4270 bus->fc_xoff++;
4271 if (bus->flowcontrol & ~fcbits)
4272 bus->fc_xon++;
4273
4274 bus->fc_rcvd++;
4275 bus->flowcontrol = fcbits;
4276 }
4277
4278 /* Shouldn't be any others */
4279 if (hmb_data & ~(HMB_DATA_DEVREADY |
4280 HMB_DATA_NAKHANDLED |
4281 HMB_DATA_FC |
4282 HMB_DATA_FWREADY |
4283 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4284 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4285 }
4286
4287 return intstatus;
4288 }
4289
4290 bool dhdsdio_dpc(dhd_bus_t *bus)
4291 {
4292 bcmsdh_info_t *sdh = bus->sdh;
4293 sdpcmd_regs_t *regs = bus->regs;
4294 u32 intstatus, newstatus = 0;
4295 uint retries = 0;
4296 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4297 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4298 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4299 bool rxdone = true; /* Flag for no more read data */
4300 bool resched = false; /* Flag indicating resched wanted */
4301
4302 DHD_TRACE(("%s: Enter\n", __func__));
4303
4304 /* Start with leftover status bits */
4305 intstatus = bus->intstatus;
4306
4307 dhd_os_sdlock(bus->dhd);
4308
4309 /* If waiting for HTAVAIL, check status */
4310 if (bus->clkstate == CLK_PENDING) {
4311 int err;
4312 u8 clkctl, devctl = 0;
4313
4314 #ifdef DHD_DEBUG
4315 /* Check for inconsistent device control */
4316 devctl =
4317 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4318 if (err) {
4319 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4320 __func__, err));
4321 bus->dhd->busstate = DHD_BUS_DOWN;
4322 } else {
4323 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4324 }
4325 #endif /* DHD_DEBUG */
4326
4327 /* Read CSR, if clock on switch to AVAIL, else ignore */
4328 clkctl =
4329 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4330 &err);
4331 if (err) {
4332 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4333 err));
4334 bus->dhd->busstate = DHD_BUS_DOWN;
4335 }
4336
4337 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4338 clkctl));
4339
4340 if (SBSDIO_HTAV(clkctl)) {
4341 devctl =
4342 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4343 &err);
4344 if (err) {
4345 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4346 __func__, err));
4347 bus->dhd->busstate = DHD_BUS_DOWN;
4348 }
4349 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4350 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4351 devctl, &err);
4352 if (err) {
4353 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4354 __func__, err));
4355 bus->dhd->busstate = DHD_BUS_DOWN;
4356 }
4357 bus->clkstate = CLK_AVAIL;
4358 } else {
4359 goto clkwait;
4360 }
4361 }
4362
4363 BUS_WAKE(bus);
4364
4365 /* Make sure backplane clock is on */
4366 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4367 if (bus->clkstate == CLK_PENDING)
4368 goto clkwait;
4369
4370 /* Pending interrupt indicates new device status */
4371 if (bus->ipend) {
4372 bus->ipend = false;
4373 R_SDREG(newstatus, &regs->intstatus, retries);
4374 bus->f1regdata++;
4375 if (bcmsdh_regfail(bus->sdh))
4376 newstatus = 0;
4377 newstatus &= bus->hostintmask;
4378 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4379 if (newstatus) {
4380 W_SDREG(newstatus, &regs->intstatus, retries);
4381 bus->f1regdata++;
4382 }
4383 }
4384
4385 /* Merge new bits with previous */
4386 intstatus |= newstatus;
4387 bus->intstatus = 0;
4388
4389 /* Handle flow-control change: read new state in case our ack
4390 * crossed another change interrupt. If change still set, assume
4391 * FC ON for safety, let next loop through do the debounce.
4392 */
4393 if (intstatus & I_HMB_FC_CHANGE) {
4394 intstatus &= ~I_HMB_FC_CHANGE;
4395 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4396 R_SDREG(newstatus, &regs->intstatus, retries);
4397 bus->f1regdata += 2;
4398 bus->fcstate =
4399 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4400 intstatus |= (newstatus & bus->hostintmask);
4401 }
4402
4403 /* Handle host mailbox indication */
4404 if (intstatus & I_HMB_HOST_INT) {
4405 intstatus &= ~I_HMB_HOST_INT;
4406 intstatus |= dhdsdio_hostmail(bus);
4407 }
4408
4409 /* Generally don't ask for these, can get CRC errors... */
4410 if (intstatus & I_WR_OOSYNC) {
4411 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4412 intstatus &= ~I_WR_OOSYNC;
4413 }
4414
4415 if (intstatus & I_RD_OOSYNC) {
4416 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4417 intstatus &= ~I_RD_OOSYNC;
4418 }
4419
4420 if (intstatus & I_SBINT) {
4421 DHD_ERROR(("Dongle reports SBINT\n"));
4422 intstatus &= ~I_SBINT;
4423 }
4424
4425 /* Would be active due to wake-wlan in gSPI */
4426 if (intstatus & I_CHIPACTIVE) {
4427 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4428 intstatus &= ~I_CHIPACTIVE;
4429 }
4430
4431 /* Ignore frame indications if rxskip is set */
4432 if (bus->rxskip)
4433 intstatus &= ~I_HMB_FRAME_IND;
4434
4435 /* On frame indication, read available frames */
4436 if (PKT_AVAILABLE()) {
4437 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4438 if (rxdone || bus->rxskip)
4439 intstatus &= ~I_HMB_FRAME_IND;
4440 rxlimit -= min(framecnt, rxlimit);
4441 }
4442
4443 /* Keep still-pending events for next scheduling */
4444 bus->intstatus = intstatus;
4445
4446 clkwait:
4447 #if defined(OOB_INTR_ONLY)
4448 bcmsdh_oob_intr_set(1);
4449 #endif /* (OOB_INTR_ONLY) */
4450 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4451 * or clock availability. (Allows tx loop to check ipend if desired.)
4452 * (Unless register access seems hosed, as we may not be able to ACK...)
4453 */
4454 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4455 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4456 __func__, rxdone, framecnt));
4457 bus->intdis = false;
4458 bcmsdh_intr_enable(sdh);
4459 }
4460
4461 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4462 (bus->clkstate == CLK_AVAIL)) {
4463 int ret, i;
4464
4465 ret =
4466 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4467 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4468 (u32) bus->ctrl_frame_len, NULL,
4469 NULL, NULL);
4470 ASSERT(ret != BCME_PENDING);
4471
4472 if (ret < 0) {
4473 /* On failure, abort the command and
4474 terminate the frame */
4475 DHD_INFO(("%s: sdio error %d, abort command and "
4476 "terminate frame.\n", __func__, ret));
4477 bus->tx_sderrs++;
4478
4479 bcmsdh_abort(sdh, SDIO_FUNC_2);
4480
4481 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4482 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4483 NULL);
4484 bus->f1regdata++;
4485
4486 for (i = 0; i < 3; i++) {
4487 u8 hi, lo;
4488 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4489 SBSDIO_FUNC1_WFRAMEBCHI,
4490 NULL);
4491 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4492 SBSDIO_FUNC1_WFRAMEBCLO,
4493 NULL);
4494 bus->f1regdata += 2;
4495 if ((hi == 0) && (lo == 0))
4496 break;
4497 }
4498
4499 }
4500 if (ret == 0)
4501 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4502
4503 DHD_INFO(("Return_dpc value is : %d\n", ret));
4504 bus->ctrl_frame_stat = false;
4505 dhd_wait_event_wakeup(bus->dhd);
4506 }
4507 /* Send queued frames (limit 1 if rx may still be pending) */
4508 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4509 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4510 && DATAOK(bus)) {
4511 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4512 framecnt = dhdsdio_sendfromq(bus, framecnt);
4513 txlimit -= framecnt;
4514 }
4515
4516 /* Resched if events or tx frames are pending,
4517 else await next interrupt */
4518 /* On failed register access, all bets are off:
4519 no resched or interrupts */
4520 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4521 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4522 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4523 bus->dhd->busstate = DHD_BUS_DOWN;
4524 bus->intstatus = 0;
4525 } else if (bus->clkstate == CLK_PENDING) {
4526 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4527 "I_CHIPACTIVE interrupt\n", __func__));
4528 resched = true;
4529 } else if (bus->intstatus || bus->ipend ||
4530 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4531 DATAOK(bus)) || PKT_AVAILABLE()) {
4532 resched = true;
4533 }
4534
4535 bus->dpc_sched = resched;
4536
4537 /* If we're done for now, turn off clock request. */
4538 if ((bus->clkstate != CLK_PENDING)
4539 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4540 bus->activity = false;
4541 dhdsdio_clkctl(bus, CLK_NONE, false);
4542 }
4543
4544 dhd_os_sdunlock(bus->dhd);
4545
4546 return resched;
4547 }
4548
4549 bool dhd_bus_dpc(struct dhd_bus *bus)
4550 {
4551 bool resched;
4552
4553 /* Call the DPC directly. */
4554 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4555 resched = dhdsdio_dpc(bus);
4556
4557 return resched;
4558 }
4559
4560 void dhdsdio_isr(void *arg)
4561 {
4562 dhd_bus_t *bus = (dhd_bus_t *) arg;
4563 bcmsdh_info_t *sdh;
4564
4565 DHD_TRACE(("%s: Enter\n", __func__));
4566
4567 if (!bus) {
4568 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4569 return;
4570 }
4571 sdh = bus->sdh;
4572
4573 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4574 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4575 __func__));
4576 return;
4577 }
4578 /* Count the interrupt call */
4579 bus->intrcount++;
4580 bus->ipend = true;
4581
4582 /* Shouldn't get this interrupt if we're sleeping? */
4583 if (bus->sleeping) {
4584 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4585 return;
4586 }
4587
4588 /* Disable additional interrupts (is this needed now)? */
4589 if (bus->intr)
4590 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4591 else
4592 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4593
4594 bcmsdh_intr_disable(sdh);
4595 bus->intdis = true;
4596
4597 #if defined(SDIO_ISR_THREAD)
4598 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4599 while (dhdsdio_dpc(bus))
4600 ;
4601 #else
4602 bus->dpc_sched = true;
4603 dhd_sched_dpc(bus->dhd);
4604 #endif
4605
4606 }
4607
4608 #ifdef SDTEST
4609 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4610 {
4611 /* Default to specified length, or full range */
4612 if (dhd_pktgen_len) {
4613 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4614 bus->pktgen_minlen = bus->pktgen_maxlen;
4615 } else {
4616 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4617 bus->pktgen_minlen = 0;
4618 }
4619 bus->pktgen_len = (u16) bus->pktgen_minlen;
4620
4621 /* Default to per-watchdog burst with 10s print time */
4622 bus->pktgen_freq = 1;
4623 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4624 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4625
4626 /* Default to echo mode */
4627 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4628 bus->pktgen_stop = 1;
4629 }
4630
4631 static void dhdsdio_pktgen(dhd_bus_t *bus)
4632 {
4633 struct sk_buff *pkt;
4634 u8 *data;
4635 uint pktcount;
4636 uint fillbyte;
4637 struct osl_info *osh = bus->dhd->osh;
4638 u16 len;
4639
4640 /* Display current count if appropriate */
4641 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4642 bus->pktgen_ptick = 0;
4643 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4644 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4645 }
4646
4647 /* For recv mode, just make sure dongle has started sending */
4648 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4649 if (!bus->pktgen_rcvd)
4650 dhdsdio_sdtest_set(bus, true);
4651 return;
4652 }
4653
4654 /* Otherwise, generate or request the specified number of packets */
4655 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4656 /* Stop if total has been reached */
4657 if (bus->pktgen_total
4658 && (bus->pktgen_sent >= bus->pktgen_total)) {
4659 bus->pktgen_count = 0;
4660 break;
4661 }
4662
4663 /* Allocate an appropriate-sized packet */
4664 len = bus->pktgen_len;
4665 pkt = pkt_buf_get_skb(osh,
4666 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4667 true);
4668 if (!pkt) {
4669 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4670 break;
4671 }
4672 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4673 DHD_SDALIGN);
4674 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4675
4676 /* Write test header cmd and extra based on mode */
4677 switch (bus->pktgen_mode) {
4678 case DHD_PKTGEN_ECHO:
4679 *data++ = SDPCM_TEST_ECHOREQ;
4680 *data++ = (u8) bus->pktgen_sent;
4681 break;
4682
4683 case DHD_PKTGEN_SEND:
4684 *data++ = SDPCM_TEST_DISCARD;
4685 *data++ = (u8) bus->pktgen_sent;
4686 break;
4687
4688 case DHD_PKTGEN_RXBURST:
4689 *data++ = SDPCM_TEST_BURST;
4690 *data++ = (u8) bus->pktgen_count;
4691 break;
4692
4693 default:
4694 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4695 bus->pktgen_mode));
4696 pkt_buf_free_skb(osh, pkt, true);
4697 bus->pktgen_count = 0;
4698 return;
4699 }
4700
4701 /* Write test header length field */
4702 *data++ = (len >> 0);
4703 *data++ = (len >> 8);
4704
4705 /* Then fill in the remainder -- N/A for burst,
4706 but who cares... */
4707 for (fillbyte = 0; fillbyte < len; fillbyte++)
4708 *data++ =
4709 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4710
4711 #ifdef DHD_DEBUG
4712 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4713 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4714 prhex("dhdsdio_pktgen: Tx Data", data,
4715 pkt->len - SDPCM_HDRLEN);
4716 }
4717 #endif
4718
4719 /* Send it */
4720 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4721 bus->pktgen_fail++;
4722 if (bus->pktgen_stop
4723 && bus->pktgen_stop == bus->pktgen_fail)
4724 bus->pktgen_count = 0;
4725 }
4726 bus->pktgen_sent++;
4727
4728 /* Bump length if not fixed, wrap at max */
4729 if (++bus->pktgen_len > bus->pktgen_maxlen)
4730 bus->pktgen_len = (u16) bus->pktgen_minlen;
4731
4732 /* Special case for burst mode: just send one request! */
4733 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4734 break;
4735 }
4736 }
4737
4738 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4739 {
4740 struct sk_buff *pkt;
4741 u8 *data;
4742 struct osl_info *osh = bus->dhd->osh;
4743
4744 /* Allocate the packet */
4745 pkt = pkt_buf_get_skb(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4746 true);
4747 if (!pkt) {
4748 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4749 return;
4750 }
4751 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4752 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4753
4754 /* Fill in the test header */
4755 *data++ = SDPCM_TEST_SEND;
4756 *data++ = start;
4757 *data++ = (bus->pktgen_maxlen >> 0);
4758 *data++ = (bus->pktgen_maxlen >> 8);
4759
4760 /* Send it */
4761 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4762 bus->pktgen_fail++;
4763 }
4764
4765 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4766 {
4767 struct osl_info *osh = bus->dhd->osh;
4768 u8 *data;
4769 uint pktlen;
4770
4771 u8 cmd;
4772 u8 extra;
4773 u16 len;
4774 u16 offset;
4775
4776 /* Check for min length */
4777 pktlen = pkt->len;
4778 if (pktlen < SDPCM_TEST_HDRLEN) {
4779 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4780 pktlen));
4781 pkt_buf_free_skb(osh, pkt, false);
4782 return;
4783 }
4784
4785 /* Extract header fields */
4786 data = pkt->data;
4787 cmd = *data++;
4788 extra = *data++;
4789 len = *data++;
4790 len += *data++ << 8;
4791
4792 /* Check length for relevant commands */
4793 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4794 || cmd == SDPCM_TEST_ECHORSP) {
4795 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4796 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4797 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4798 pktlen, seq, cmd, extra, len));
4799 pkt_buf_free_skb(osh, pkt, false);
4800 return;
4801 }
4802 }
4803
4804 /* Process as per command */
4805 switch (cmd) {
4806 case SDPCM_TEST_ECHOREQ:
4807 /* Rx->Tx turnaround ok (even on NDIS w/current
4808 implementation) */
4809 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4810 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4811 bus->pktgen_sent++;
4812 } else {
4813 bus->pktgen_fail++;
4814 pkt_buf_free_skb(osh, pkt, false);
4815 }
4816 bus->pktgen_rcvd++;
4817 break;
4818
4819 case SDPCM_TEST_ECHORSP:
4820 if (bus->ext_loop) {
4821 pkt_buf_free_skb(osh, pkt, false);
4822 bus->pktgen_rcvd++;
4823 break;
4824 }
4825
4826 for (offset = 0; offset < len; offset++, data++) {
4827 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4828 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4829 offset, len,
4830 SDPCM_TEST_FILL(offset, extra), *data));
4831 break;
4832 }
4833 }
4834 pkt_buf_free_skb(osh, pkt, false);
4835 bus->pktgen_rcvd++;
4836 break;
4837
4838 case SDPCM_TEST_DISCARD:
4839 pkt_buf_free_skb(osh, pkt, false);
4840 bus->pktgen_rcvd++;
4841 break;
4842
4843 case SDPCM_TEST_BURST:
4844 case SDPCM_TEST_SEND:
4845 default:
4846 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4847 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4848 pktlen, seq, cmd, extra, len));
4849 pkt_buf_free_skb(osh, pkt, false);
4850 break;
4851 }
4852
4853 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4854 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4855 if (bus->pktgen_total
4856 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4857 bus->pktgen_count = 0;
4858 dhdsdio_sdtest_set(bus, false);
4859 }
4860 }
4861 }
4862 #endif /* SDTEST */
4863
4864 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4865 {
4866 dhd_bus_t *bus;
4867
4868 DHD_TIMER(("%s: Enter\n", __func__));
4869
4870 bus = dhdp->bus;
4871
4872 if (bus->dhd->dongle_reset)
4873 return false;
4874
4875 /* Ignore the timer if simulating bus down */
4876 if (bus->sleeping)
4877 return false;
4878
4879 dhd_os_sdlock(bus->dhd);
4880
4881 /* Poll period: check device if appropriate. */
4882 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4883 u32 intstatus = 0;
4884
4885 /* Reset poll tick */
4886 bus->polltick = 0;
4887
4888 /* Check device if no interrupts */
4889 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4890
4891 if (!bus->dpc_sched) {
4892 u8 devpend;
4893 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4894 SDIOD_CCCR_INTPEND,
4895 NULL);
4896 intstatus =
4897 devpend & (INTR_STATUS_FUNC1 |
4898 INTR_STATUS_FUNC2);
4899 }
4900
4901 /* If there is something, make like the ISR and
4902 schedule the DPC */
4903 if (intstatus) {
4904 bus->pollcnt++;
4905 bus->ipend = true;
4906 if (bus->intr)
4907 bcmsdh_intr_disable(bus->sdh);
4908
4909 bus->dpc_sched = true;
4910 dhd_sched_dpc(bus->dhd);
4911
4912 }
4913 }
4914
4915 /* Update interrupt tracking */
4916 bus->lastintrs = bus->intrcount;
4917 }
4918 #ifdef DHD_DEBUG
4919 /* Poll for console output periodically */
4920 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4921 bus->console.count += dhd_watchdog_ms;
4922 if (bus->console.count >= dhd_console_ms) {
4923 bus->console.count -= dhd_console_ms;
4924 /* Make sure backplane clock is on */
4925 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4926 if (dhdsdio_readconsole(bus) < 0)
4927 dhd_console_ms = 0; /* On error,
4928 stop trying */
4929 }
4930 }
4931 #endif /* DHD_DEBUG */
4932
4933 #ifdef SDTEST
4934 /* Generate packets if configured */
4935 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4936 /* Make sure backplane clock is on */
4937 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4938 bus->pktgen_tick = 0;
4939 dhdsdio_pktgen(bus);
4940 }
4941 #endif
4942
4943 /* On idle timeout clear activity flag and/or turn off clock */
4944 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4945 if (++bus->idlecount >= bus->idletime) {
4946 bus->idlecount = 0;
4947 if (bus->activity) {
4948 bus->activity = false;
4949 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4950 } else {
4951 dhdsdio_clkctl(bus, CLK_NONE, false);
4952 }
4953 }
4954 }
4955
4956 dhd_os_sdunlock(bus->dhd);
4957
4958 return bus->ipend;
4959 }
4960
4961 #ifdef DHD_DEBUG
4962 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4963 {
4964 dhd_bus_t *bus = dhdp->bus;
4965 u32 addr, val;
4966 int rv;
4967 struct sk_buff *pkt;
4968
4969 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4970 if (bus->console_addr == 0)
4971 return BCME_UNSUPPORTED;
4972
4973 /* Exclusive bus access */
4974 dhd_os_sdlock(bus->dhd);
4975
4976 /* Don't allow input if dongle is in reset */
4977 if (bus->dhd->dongle_reset) {
4978 dhd_os_sdunlock(bus->dhd);
4979 return BCME_NOTREADY;
4980 }
4981
4982 /* Request clock to allow SDIO accesses */
4983 BUS_WAKE(bus);
4984 /* No pend allowed since txpkt is called later, ht clk has to be on */
4985 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4986
4987 /* Zero cbuf_index */
4988 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4989 val = htol32(0);
4990 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4991 if (rv < 0)
4992 goto done;
4993
4994 /* Write message into cbuf */
4995 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4996 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4997 if (rv < 0)
4998 goto done;
4999
5000 /* Write length into vcons_in */
5001 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
5002 val = htol32(msglen);
5003 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5004 if (rv < 0)
5005 goto done;
5006
5007 /* Bump dongle by sending an empty event pkt.
5008 * sdpcm_sendup (RX) checks for virtual console input.
5009 */
5010 pkt = pkt_buf_get_skb(bus->dhd->osh, 4 + SDPCM_RESERVE);
5011 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5012 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5013
5014 done:
5015 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5016 bus->activity = false;
5017 dhdsdio_clkctl(bus, CLK_NONE, true);
5018 }
5019
5020 dhd_os_sdunlock(bus->dhd);
5021
5022 return rv;
5023 }
5024 #endif /* DHD_DEBUG */
5025
5026 #ifdef DHD_DEBUG
5027 static void dhd_dump_cis(uint fn, u8 *cis)
5028 {
5029 uint byte, tag, tdata;
5030 DHD_INFO(("Function %d CIS:\n", fn));
5031
5032 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5033 if ((byte % 16) == 0)
5034 DHD_INFO((" "));
5035 DHD_INFO(("%02x ", cis[byte]));
5036 if ((byte % 16) == 15)
5037 DHD_INFO(("\n"));
5038 if (!tdata--) {
5039 tag = cis[byte];
5040 if (tag == 0xff)
5041 break;
5042 else if (!tag)
5043 tdata = 0;
5044 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5045 tdata = cis[byte + 1] + 1;
5046 else
5047 DHD_INFO(("]"));
5048 }
5049 }
5050 if ((byte % 16) != 15)
5051 DHD_INFO(("\n"));
5052 }
5053 #endif /* DHD_DEBUG */
5054
5055 static bool dhdsdio_chipmatch(u16 chipid)
5056 {
5057 if (chipid == BCM4325_CHIP_ID)
5058 return true;
5059 if (chipid == BCM4329_CHIP_ID)
5060 return true;
5061 if (chipid == BCM4319_CHIP_ID)
5062 return true;
5063 return false;
5064 }
5065
5066 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5067 u16 slot, u16 func, uint bustype, void *regsva,
5068 struct osl_info *osh, void *sdh)
5069 {
5070 int ret;
5071 dhd_bus_t *bus;
5072
5073 /* Init global variables at run-time, not as part of the declaration.
5074 * This is required to support init/de-init of the driver.
5075 * Initialization
5076 * of globals as part of the declaration results in non-deterministic
5077 * behavior since the value of the globals may be different on the
5078 * first time that the driver is initialized vs subsequent
5079 * initializations.
5080 */
5081 dhd_txbound = DHD_TXBOUND;
5082 dhd_rxbound = DHD_RXBOUND;
5083 dhd_alignctl = true;
5084 sd1idle = true;
5085 dhd_readahead = true;
5086 retrydata = false;
5087 dhd_doflow = false;
5088 dhd_dongle_memsize = 0;
5089 dhd_txminmax = DHD_TXMINMAX;
5090
5091 forcealign = true;
5092
5093 dhd_common_init();
5094
5095 DHD_TRACE(("%s: Enter\n", __func__));
5096 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5097
5098 /* We make assumptions about address window mappings */
5099 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5100
5101 /* BCMSDH passes venid and devid based on CIS parsing -- but
5102 * low-power start
5103 * means early parse could fail, so here we should get either an ID
5104 * we recognize OR (-1) indicating we must request power first.
5105 */
5106 /* Check the Vendor ID */
5107 switch (venid) {
5108 case 0x0000:
5109 case VENDOR_BROADCOM:
5110 break;
5111 default:
5112 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5113 return NULL;
5114 }
5115
5116 /* Check the Device ID and make sure it's one that we support */
5117 switch (devid) {
5118 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5119 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5120 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5121 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5122 break;
5123 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5124 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5125 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5126 case 0x4329:
5127 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5128 break;
5129 case BCM4319_D11N_ID: /* 4319 802.11n id */
5130 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5131 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5132 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5133 break;
5134 case 0:
5135 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5136 __func__));
5137 break;
5138
5139 default:
5140 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5141 __func__, venid, devid));
5142 return NULL;
5143 }
5144
5145 if (osh == NULL) {
5146 /* Ask the OS interface part for an OSL handle */
5147 osh = dhd_osl_attach(sdh, DHD_BUS);
5148 if (!osh) {
5149 DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5150 return NULL;
5151 }
5152 }
5153
5154 /* Allocate private bus interface state */
5155 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5156 if (!bus) {
5157 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5158 goto fail;
5159 }
5160 bus->sdh = sdh;
5161 bus->cl_devid = (u16) devid;
5162 bus->bus = DHD_BUS;
5163 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5164 bus->usebufpool = false; /* Use bufpool if allocated,
5165 else use locally malloced rxbuf */
5166
5167 /* attempt to attach to the dongle */
5168 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5169 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5170 goto fail;
5171 }
5172
5173 /* Attach to the dhd/OS/network interface */
5174 bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
5175 if (!bus->dhd) {
5176 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5177 goto fail;
5178 }
5179
5180 /* Allocate buffers */
5181 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5182 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5183 goto fail;
5184 }
5185
5186 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5187 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5188 goto fail;
5189 }
5190
5191 /* Register interrupt callback, but mask it (not operational yet). */
5192 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5193 __func__));
5194 bcmsdh_intr_disable(sdh);
5195 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5196 if (ret != 0) {
5197 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5198 __func__, ret));
5199 goto fail;
5200 }
5201 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5202
5203 DHD_INFO(("%s: completed!!\n", __func__));
5204
5205 /* if firmware path present try to download and bring up bus */
5206 ret = dhd_bus_start(bus->dhd);
5207 if (ret != 0) {
5208 if (ret == BCME_NOTUP) {
5209 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5210 goto fail;
5211 }
5212 }
5213 /* Ok, have the per-port tell the stack we're open for business */
5214 if (dhd_net_attach(bus->dhd, 0) != 0) {
5215 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5216 goto fail;
5217 }
5218
5219 return bus;
5220
5221 fail:
5222 dhdsdio_release(bus, osh);
5223 return NULL;
5224 }
5225
5226 static bool
5227 dhdsdio_probe_attach(struct dhd_bus *bus, struct osl_info *osh, void *sdh,
5228 void *regsva, u16 devid)
5229 {
5230 u8 clkctl = 0;
5231 int err = 0;
5232
5233 bus->alp_only = true;
5234
5235 /* Return the window to backplane enumeration space for core access */
5236 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5237 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5238
5239 #ifdef DHD_DEBUG
5240 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5241 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5242
5243 #endif /* DHD_DEBUG */
5244
5245 /* Force PLL off until si_attach() programs PLL control regs */
5246
5247 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5248 DHD_INIT_CLKCTL1, &err);
5249 if (!err)
5250 clkctl =
5251 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5252 &err);
5253
5254 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5255 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5256 "0x%02x read 0x%02x\n",
5257 err, DHD_INIT_CLKCTL1, clkctl));
5258 goto fail;
5259 }
5260 #ifdef DHD_DEBUG
5261 if (DHD_INFO_ON()) {
5262 uint fn, numfn;
5263 u8 *cis[SDIOD_MAX_IOFUNCS];
5264 int err = 0;
5265
5266 numfn = bcmsdh_query_iofnum(sdh);
5267 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5268
5269 /* Make sure ALP is available before trying to read CIS */
5270 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5271 SBSDIO_FUNC1_CHIPCLKCSR,
5272 NULL)),
5273 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5274
5275 /* Now request ALP be put on the bus */
5276 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5277 DHD_INIT_CLKCTL2, &err);
5278 udelay(65);
5279
5280 for (fn = 0; fn <= numfn; fn++) {
5281 cis[fn] = kmalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5282 if (!cis[fn]) {
5283 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5284 "failed\n", fn));
5285 break;
5286 }
5287 memset(cis[fn], 0, SBSDIO_CIS_SIZE_LIMIT);
5288
5289 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5290 SBSDIO_CIS_SIZE_LIMIT);
5291 if (err) {
5292 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5293 "err %d\n", fn, err));
5294 kfree(cis[fn]);
5295 break;
5296 }
5297 dhd_dump_cis(fn, cis[fn]);
5298 }
5299
5300 while (fn-- > 0) {
5301 ASSERT(cis[fn]);
5302 kfree(cis[fn]);
5303 }
5304
5305 if (err) {
5306 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5307 goto fail;
5308 }
5309 }
5310 #endif /* DHD_DEBUG */
5311
5312 /* si_attach() will provide an SI handle and scan the backplane */
5313 bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5314 &bus->vars, &bus->varsz);
5315 if (!(bus->sih)) {
5316 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5317 goto fail;
5318 }
5319
5320 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5321
5322 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5323 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5324 __func__, bus->sih->chip));
5325 goto fail;
5326 }
5327
5328 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5329
5330 /* Get info on the ARM and SOCRAM cores... */
5331 if (!DHD_NOPMU(bus)) {
5332 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5333 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5334 bus->armrev = si_corerev(bus->sih);
5335 } else {
5336 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5337 goto fail;
5338 }
5339 bus->orig_ramsize = si_socram_size(bus->sih);
5340 if (!(bus->orig_ramsize)) {
5341 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5342 __func__));
5343 goto fail;
5344 }
5345 bus->ramsize = bus->orig_ramsize;
5346 if (dhd_dongle_memsize)
5347 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5348
5349 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5350 bus->ramsize, bus->orig_ramsize));
5351 }
5352
5353 /* ...but normally deal with the SDPCMDEV core */
5354 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5355 if (!bus->regs) {
5356 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5357 if (!bus->regs) {
5358 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5359 __func__));
5360 goto fail;
5361 }
5362 }
5363 bus->sdpcmrev = si_corerev(bus->sih);
5364
5365 /* Set core control so an SDIO reset does a backplane reset */
5366 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5367
5368 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5369
5370 /* Locate an appropriately-aligned portion of hdrbuf */
5371 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5372
5373 /* Set the poll and/or interrupt flags */
5374 bus->intr = (bool) dhd_intr;
5375 bus->poll = (bool) dhd_poll;
5376 if (bus->poll)
5377 bus->pollrate = 1;
5378
5379 return true;
5380
5381 fail:
5382 return false;
5383 }
5384
5385 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, struct osl_info *osh,
5386 void *sdh)
5387 {
5388 DHD_TRACE(("%s: Enter\n", __func__));
5389
5390 if (bus->dhd->maxctl) {
5391 bus->rxblen =
5392 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5393 ALIGNMENT) + DHD_SDALIGN;
5394 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5395 if (!(bus->rxbuf)) {
5396 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5397 __func__, bus->rxblen));
5398 goto fail;
5399 }
5400 }
5401
5402 /* Allocate buffer to receive glomed packet */
5403 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5404 if (!(bus->databuf)) {
5405 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5406 __func__, MAX_DATA_BUF));
5407 /* release rxbuf which was already located as above */
5408 if (!bus->rxblen)
5409 kfree(bus->rxbuf);
5410 goto fail;
5411 }
5412
5413 /* Align the buffer */
5414 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5415 bus->dataptr =
5416 bus->databuf + (DHD_SDALIGN -
5417 ((unsigned long)bus->databuf % DHD_SDALIGN));
5418 else
5419 bus->dataptr = bus->databuf;
5420
5421 return true;
5422
5423 fail:
5424 return false;
5425 }
5426
5427 static bool dhdsdio_probe_init(dhd_bus_t *bus, struct osl_info *osh, void *sdh)
5428 {
5429 s32 fnum;
5430
5431 DHD_TRACE(("%s: Enter\n", __func__));
5432
5433 #ifdef SDTEST
5434 dhdsdio_pktgen_init(bus);
5435 #endif /* SDTEST */
5436
5437 /* Disable F2 to clear any intermediate frame state on the dongle */
5438 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5439 NULL);
5440
5441 bus->dhd->busstate = DHD_BUS_DOWN;
5442 bus->sleeping = false;
5443 bus->rxflow = false;
5444 bus->prev_rxlim_hit = 0;
5445
5446 /* Done with backplane-dependent accesses, can drop clock... */
5447 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5448
5449 /* ...and initialize clock/power states */
5450 bus->clkstate = CLK_SDONLY;
5451 bus->idletime = (s32) dhd_idletime;
5452 bus->idleclock = DHD_IDLE_ACTIVE;
5453
5454 /* Query the SD clock speed */
5455 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5456 &bus->sd_divisor, sizeof(s32),
5457 false) != BCME_OK) {
5458 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5459 bus->sd_divisor = -1;
5460 } else {
5461 DHD_INFO(("%s: Initial value for %s is %d\n",
5462 __func__, "sd_divisor", bus->sd_divisor));
5463 }
5464
5465 /* Query the SD bus mode */
5466 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5467 &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
5468 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5469 bus->sd_mode = -1;
5470 } else {
5471 DHD_INFO(("%s: Initial value for %s is %d\n",
5472 __func__, "sd_mode", bus->sd_mode));
5473 }
5474
5475 /* Query the F2 block size, set roundup accordingly */
5476 fnum = 2;
5477 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5478 &bus->blocksize, sizeof(s32), false) != BCME_OK) {
5479 bus->blocksize = 0;
5480 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5481 } else {
5482 DHD_INFO(("%s: Initial value for %s is %d\n",
5483 __func__, "sd_blocksize", bus->blocksize));
5484 }
5485 bus->roundup = min(max_roundup, bus->blocksize);
5486
5487 /* Query if bus module supports packet chaining,
5488 default to use if supported */
5489 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5490 &bus->sd_rxchain, sizeof(s32),
5491 false) != BCME_OK) {
5492 bus->sd_rxchain = false;
5493 } else {
5494 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5495 __func__,
5496 (bus->sd_rxchain ? "supports" : "does not support")));
5497 }
5498 bus->use_rxchain = (bool) bus->sd_rxchain;
5499
5500 return true;
5501 }
5502
5503 bool
5504 dhd_bus_download_firmware(struct dhd_bus *bus, struct osl_info *osh,
5505 char *fw_path, char *nv_path)
5506 {
5507 bool ret;
5508 bus->fw_path = fw_path;
5509 bus->nv_path = nv_path;
5510
5511 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5512
5513 return ret;
5514 }
5515
5516 static bool
5517 dhdsdio_download_firmware(struct dhd_bus *bus, struct osl_info *osh, void *sdh)
5518 {
5519 bool ret;
5520
5521 /* Download the firmware */
5522 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5523
5524 ret = _dhdsdio_download_firmware(bus) == 0;
5525
5526 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5527
5528 return ret;
5529 }
5530
5531 /* Detach and free everything */
5532 static void dhdsdio_release(dhd_bus_t *bus, struct osl_info *osh)
5533 {
5534 DHD_TRACE(("%s: Enter\n", __func__));
5535
5536 if (bus) {
5537 ASSERT(osh);
5538
5539 /* De-register interrupt handler */
5540 bcmsdh_intr_disable(bus->sdh);
5541 bcmsdh_intr_dereg(bus->sdh);
5542
5543 if (bus->dhd) {
5544
5545 dhdsdio_release_dongle(bus, osh);
5546
5547 dhd_detach(bus->dhd);
5548 bus->dhd = NULL;
5549 }
5550
5551 dhdsdio_release_malloc(bus, osh);
5552
5553 kfree(bus);
5554 }
5555
5556 if (osh)
5557 dhd_osl_detach(osh);
5558
5559 DHD_TRACE(("%s: Disconnected\n", __func__));
5560 }
5561
5562 static void dhdsdio_release_malloc(dhd_bus_t *bus, struct osl_info *osh)
5563 {
5564 DHD_TRACE(("%s: Enter\n", __func__));
5565
5566 if (bus->dhd && bus->dhd->dongle_reset)
5567 return;
5568
5569 if (bus->rxbuf) {
5570 kfree(bus->rxbuf);
5571 bus->rxctl = bus->rxbuf = NULL;
5572 bus->rxlen = 0;
5573 }
5574
5575 if (bus->databuf) {
5576 kfree(bus->databuf);
5577 bus->databuf = NULL;
5578 }
5579 }
5580
5581 static void dhdsdio_release_dongle(dhd_bus_t *bus, struct osl_info *osh)
5582 {
5583 DHD_TRACE(("%s: Enter\n", __func__));
5584
5585 if (bus->dhd && bus->dhd->dongle_reset)
5586 return;
5587
5588 if (bus->sih) {
5589 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5590 #if !defined(BCMLXSDMMC)
5591 si_watchdog(bus->sih, 4);
5592 #endif /* !defined(BCMLXSDMMC) */
5593 dhdsdio_clkctl(bus, CLK_NONE, false);
5594 si_detach(bus->sih);
5595 if (bus->vars && bus->varsz)
5596 kfree(bus->vars);
5597 bus->vars = NULL;
5598 }
5599
5600 DHD_TRACE(("%s: Disconnected\n", __func__));
5601 }
5602
5603 static void dhdsdio_disconnect(void *ptr)
5604 {
5605 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5606
5607 DHD_TRACE(("%s: Enter\n", __func__));
5608
5609 if (bus) {
5610 ASSERT(bus->dhd);
5611 dhdsdio_release(bus, bus->dhd->osh);
5612 }
5613
5614 DHD_TRACE(("%s: Disconnected\n", __func__));
5615 }
5616
5617 /* Register/Unregister functions are called by the main DHD entry
5618 * point (e.g. module insertion) to link with the bus driver, in
5619 * order to look for or await the device.
5620 */
5621
5622 static bcmsdh_driver_t dhd_sdio = {
5623 dhdsdio_probe,
5624 dhdsdio_disconnect
5625 };
5626
5627 int dhd_bus_register(void)
5628 {
5629 DHD_TRACE(("%s: Enter\n", __func__));
5630
5631 return bcmsdh_register(&dhd_sdio);
5632 }
5633
5634 void dhd_bus_unregister(void)
5635 {
5636 DHD_TRACE(("%s: Enter\n", __func__));
5637
5638 bcmsdh_unregister();
5639 }
5640
5641 #ifdef BCMEMBEDIMAGE
5642 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5643 {
5644 int bcmerror = -1;
5645 int offset = 0;
5646
5647 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5648
5649 /* Download image */
5650 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5651 bcmerror =
5652 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5653 MEMBLOCK);
5654 if (bcmerror) {
5655 DHD_ERROR(("%s: error %d on writing %d membytes at "
5656 "0x%08x\n",
5657 __func__, bcmerror, MEMBLOCK, offset));
5658 goto err;
5659 }
5660
5661 offset += MEMBLOCK;
5662 }
5663
5664 if (offset < sizeof(dlarray)) {
5665 bcmerror = dhdsdio_membytes(bus, true, offset,
5666 dlarray + offset,
5667 sizeof(dlarray) - offset);
5668 if (bcmerror) {
5669 DHD_ERROR(("%s: error %d on writing %d membytes at "
5670 "0x%08x\n", __func__, bcmerror,
5671 sizeof(dlarray) - offset, offset));
5672 goto err;
5673 }
5674 }
5675 #ifdef DHD_DEBUG
5676 /* Upload and compare the downloaded code */
5677 {
5678 unsigned char *ularray;
5679
5680 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5681 /* Upload image to verify downloaded contents. */
5682 offset = 0;
5683 memset(ularray, 0xaa, bus->ramsize);
5684 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5685 bcmerror =
5686 dhdsdio_membytes(bus, false, offset,
5687 ularray + offset, MEMBLOCK);
5688 if (bcmerror) {
5689 DHD_ERROR(("%s: error %d on reading %d membytes"
5690 " at 0x%08x\n",
5691 __func__, bcmerror, MEMBLOCK, offset));
5692 goto err;
5693 }
5694
5695 offset += MEMBLOCK;
5696 }
5697
5698 if (offset < sizeof(dlarray)) {
5699 bcmerror = dhdsdio_membytes(bus, false, offset,
5700 ularray + offset,
5701 sizeof(dlarray) - offset);
5702 if (bcmerror) {
5703 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5704 __func__, bcmerror,
5705 sizeof(dlarray) - offset, offset));
5706 goto err;
5707 }
5708 }
5709
5710 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5711 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5712 __func__));
5713 ASSERT(0);
5714 goto err;
5715 } else
5716 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5717 __func__));
5718
5719 kfree(ularray);
5720 }
5721 #endif /* DHD_DEBUG */
5722
5723 err:
5724 return bcmerror;
5725 }
5726 #endif /* BCMEMBEDIMAGE */
5727
5728 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5729 {
5730 int bcmerror = -1;
5731 int offset = 0;
5732 uint len;
5733 void *image = NULL;
5734 u8 *memblock = NULL, *memptr;
5735
5736 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5737
5738 image = dhd_os_open_image(fw_path);
5739 if (image == NULL)
5740 goto err;
5741
5742 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5743 if (memblock == NULL) {
5744 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5745 __func__, MEMBLOCK));
5746 goto err;
5747 }
5748 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5749 memptr +=
5750 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5751
5752 /* Download image */
5753 while ((len =
5754 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5755 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5756 if (bcmerror) {
5757 DHD_ERROR(("%s: error %d on writing %d membytes at "
5758 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5759 goto err;
5760 }
5761
5762 offset += MEMBLOCK;
5763 }
5764
5765 err:
5766 if (memblock)
5767 kfree(memblock);
5768
5769 if (image)
5770 dhd_os_close_image(image);
5771
5772 return bcmerror;
5773 }
5774
5775 /*
5776 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5777 * and ending in a NUL.
5778 * Removes carriage returns, empty lines, comment lines, and converts
5779 * newlines to NULs.
5780 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5781 * by two NULs.
5782 */
5783
5784 static uint process_nvram_vars(char *varbuf, uint len)
5785 {
5786 char *dp;
5787 bool findNewline;
5788 int column;
5789 uint buf_len, n;
5790
5791 dp = varbuf;
5792
5793 findNewline = false;
5794 column = 0;
5795
5796 for (n = 0; n < len; n++) {
5797 if (varbuf[n] == 0)
5798 break;
5799 if (varbuf[n] == '\r')
5800 continue;
5801 if (findNewline && varbuf[n] != '\n')
5802 continue;
5803 findNewline = false;
5804 if (varbuf[n] == '#') {
5805 findNewline = true;
5806 continue;
5807 }
5808 if (varbuf[n] == '\n') {
5809 if (column == 0)
5810 continue;
5811 *dp++ = 0;
5812 column = 0;
5813 continue;
5814 }
5815 *dp++ = varbuf[n];
5816 column++;
5817 }
5818 buf_len = dp - varbuf;
5819
5820 while (dp < varbuf + n)
5821 *dp++ = 0;
5822
5823 return buf_len;
5824 }
5825
5826 /*
5827 EXAMPLE: nvram_array
5828 nvram_arry format:
5829 name=value
5830 Use carriage return at the end of each assignment,
5831 and an empty string with
5832 carriage return at the end of array.
5833
5834 For example:
5835 unsigned char nvram_array[] = {"name1=value1\n",
5836 "name2=value2\n", "\n"};
5837 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5838
5839 Search "EXAMPLE: nvram_array" to see how the array is activated.
5840 */
5841
5842 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5843 {
5844 bus->nvram_params = nvram_params;
5845 }
5846
5847 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5848 {
5849 int bcmerror = -1;
5850 uint len;
5851 void *image = NULL;
5852 char *memblock = NULL;
5853 char *bufp;
5854 char *nv_path;
5855 bool nvram_file_exists;
5856
5857 nv_path = bus->nv_path;
5858
5859 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5860 if (!nvram_file_exists && (bus->nvram_params == NULL))
5861 return 0;
5862
5863 if (nvram_file_exists) {
5864 image = dhd_os_open_image(nv_path);
5865 if (image == NULL)
5866 goto err;
5867 }
5868
5869 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5870 if (memblock == NULL) {
5871 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5872 __func__, MEMBLOCK));
5873 goto err;
5874 }
5875
5876 /* Download variables */
5877 if (nvram_file_exists) {
5878 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5879 } else {
5880 len = strlen(bus->nvram_params);
5881 ASSERT(len <= MEMBLOCK);
5882 if (len > MEMBLOCK)
5883 len = MEMBLOCK;
5884 memcpy(memblock, bus->nvram_params, len);
5885 }
5886
5887 if (len > 0 && len < MEMBLOCK) {
5888 bufp = (char *)memblock;
5889 bufp[len] = 0;
5890 len = process_nvram_vars(bufp, len);
5891 bufp += len;
5892 *bufp++ = 0;
5893 if (len)
5894 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5895 if (bcmerror) {
5896 DHD_ERROR(("%s: error downloading vars: %d\n",
5897 __func__, bcmerror));
5898 }
5899 } else {
5900 DHD_ERROR(("%s: error reading nvram file: %d\n",
5901 __func__, len));
5902 bcmerror = BCME_SDIO_ERROR;
5903 }
5904
5905 err:
5906 if (memblock)
5907 kfree(memblock);
5908
5909 if (image)
5910 dhd_os_close_image(image);
5911
5912 return bcmerror;
5913 }
5914
5915 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5916 {
5917 int bcmerror = -1;
5918
5919 bool embed = false; /* download embedded firmware */
5920 bool dlok = false; /* download firmware succeeded */
5921
5922 /* Out immediately if no image to download */
5923 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5924 #ifdef BCMEMBEDIMAGE
5925 embed = true;
5926 #else
5927 return bcmerror;
5928 #endif
5929 }
5930
5931 /* Keep arm in reset */
5932 if (dhdsdio_download_state(bus, true)) {
5933 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5934 goto err;
5935 }
5936
5937 /* External image takes precedence if specified */
5938 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5939 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5940 DHD_ERROR(("%s: dongle image file download failed\n",
5941 __func__));
5942 #ifdef BCMEMBEDIMAGE
5943 embed = true;
5944 #else
5945 goto err;
5946 #endif
5947 } else {
5948 embed = false;
5949 dlok = true;
5950 }
5951 }
5952 #ifdef BCMEMBEDIMAGE
5953 if (embed) {
5954 if (dhdsdio_download_code_array(bus)) {
5955 DHD_ERROR(("%s: dongle image array download failed\n",
5956 __func__));
5957 goto err;
5958 } else {
5959 dlok = true;
5960 }
5961 }
5962 #endif
5963 if (!dlok) {
5964 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5965 goto err;
5966 }
5967
5968 /* EXAMPLE: nvram_array */
5969 /* If a valid nvram_arry is specified as above, it can be passed
5970 down to dongle */
5971 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5972
5973 /* External nvram takes precedence if specified */
5974 if (dhdsdio_download_nvram(bus)) {
5975 DHD_ERROR(("%s: dongle nvram file download failed\n",
5976 __func__));
5977 }
5978
5979 /* Take arm out of reset */
5980 if (dhdsdio_download_state(bus, false)) {
5981 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5982 __func__));
5983 goto err;
5984 }
5985
5986 bcmerror = 0;
5987
5988 err:
5989 return bcmerror;
5990 }
5991
5992 static int
5993 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5994 u8 *buf, uint nbytes, struct sk_buff *pkt,
5995 bcmsdh_cmplt_fn_t complete, void *handle)
5996 {
5997 int status;
5998
5999 /* 4329: GSPI check */
6000 status =
6001 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6002 complete, handle);
6003 return status;
6004 }
6005
6006 static int
6007 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6008 u8 *buf, uint nbytes, struct sk_buff *pkt,
6009 bcmsdh_cmplt_fn_t complete, void *handle)
6010 {
6011 return bcmsdh_send_buf
6012 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
6013 handle);
6014 }
6015
6016 uint dhd_bus_chip(struct dhd_bus *bus)
6017 {
6018 ASSERT(bus->sih != NULL);
6019 return bus->sih->chip;
6020 }
6021
6022 void *dhd_bus_pub(struct dhd_bus *bus)
6023 {
6024 return bus->dhd;
6025 }
6026
6027 void *dhd_bus_txq(struct dhd_bus *bus)
6028 {
6029 return &bus->txq;
6030 }
6031
6032 uint dhd_bus_hdrlen(struct dhd_bus *bus)
6033 {
6034 return SDPCM_HDRLEN;
6035 }
6036
6037 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6038 {
6039 int bcmerror = 0;
6040 dhd_bus_t *bus;
6041
6042 bus = dhdp->bus;
6043
6044 if (flag == true) {
6045 if (!bus->dhd->dongle_reset) {
6046 /* Expect app to have torn down any
6047 connection before calling */
6048 /* Stop the bus, disable F2 */
6049 dhd_bus_stop(bus, false);
6050
6051 /* Clean tx/rx buffer pointers,
6052 detach from the dongle */
6053 dhdsdio_release_dongle(bus, bus->dhd->osh);
6054
6055 bus->dhd->dongle_reset = true;
6056 bus->dhd->up = false;
6057
6058 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6059 /* App can now remove power from device */
6060 } else
6061 bcmerror = BCME_SDIO_ERROR;
6062 } else {
6063 /* App must have restored power to device before calling */
6064
6065 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6066
6067 if (bus->dhd->dongle_reset) {
6068 /* Turn on WLAN */
6069 /* Reset SD client */
6070 bcmsdh_reset(bus->sdh);
6071
6072 /* Attempt to re-attach & download */
6073 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6074 (u32 *) SI_ENUM_BASE,
6075 bus->cl_devid)) {
6076 /* Attempt to download binary to the dongle */
6077 if (dhdsdio_probe_init
6078 (bus, bus->dhd->osh, bus->sdh)
6079 && dhdsdio_download_firmware(bus,
6080 bus->dhd->osh,
6081 bus->sdh)) {
6082
6083 /* Re-init bus, enable F2 transfer */
6084 dhd_bus_init((dhd_pub_t *) bus->dhd,
6085 false);
6086
6087 #if defined(OOB_INTR_ONLY)
6088 dhd_enable_oob_intr(bus, true);
6089 #endif /* defined(OOB_INTR_ONLY) */
6090
6091 bus->dhd->dongle_reset = false;
6092 bus->dhd->up = true;
6093
6094 DHD_TRACE(("%s: WLAN ON DONE\n",
6095 __func__));
6096 } else
6097 bcmerror = BCME_SDIO_ERROR;
6098 } else
6099 bcmerror = BCME_SDIO_ERROR;
6100 } else {
6101 bcmerror = BCME_NOTDOWN;
6102 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6103 "is on\n", __func__));
6104 bcmerror = BCME_SDIO_ERROR;
6105 }
6106 }
6107 return bcmerror;
6108 }
Linux kernel - Deliverables
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