staging: brcm80211: fix 'ERROR: "foo * bar" should be "foo *bar"'
[deliverable/linux.git] / drivers / staging / brcm80211 / sys / wlc_phy_shim.h
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef _wlc_phy_shim_h_
18 #define _wlc_phy_shim_h_
19
20 #define RADAR_TYPE_NONE 0 /* Radar type None */
21 #define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
22 #define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
23 #define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */
24 #define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */
25 #define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */
26 #define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */
27 #define RADAR_TYPE_BIN5 7 /* long pulse radar type */
28 #define RADAR_TYPE_STG2 8 /* staggered-2 radar */
29 #define RADAR_TYPE_STG3 9 /* staggered-3 radar */
30 #define RADAR_TYPE_FRA 10 /* French radar */
31
32 /* French radar pulse widths */
33 #define FRA_T1_20MHZ 52770
34 #define FRA_T2_20MHZ 61538
35 #define FRA_T3_20MHZ 66002
36 #define FRA_T1_40MHZ 105541
37 #define FRA_T2_40MHZ 123077
38 #define FRA_T3_40MHZ 132004
39 #define FRA_ERR_20MHZ 60
40 #define FRA_ERR_40MHZ 120
41
42 #define ANTSEL_NA 0 /* No boardlevel selection available */
43 #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
44 #define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
45
46 /* Rx Antenna diversity control values */
47 #define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
48 #define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
49 #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
50 #define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
51 #define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
52 #define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
53
54 /* Forward declarations */
55 struct wlc_hw_info;
56 typedef struct wlc_phy_shim_info wlc_phy_shim_info_t;
57
58 extern wlc_phy_shim_info_t *wlc_phy_shim_attach(struct wlc_hw_info *wlc_hw,
59 void *wl, void *wlc);
60 extern void wlc_phy_shim_detach(wlc_phy_shim_info_t *physhim);
61
62 /* PHY to WL utility functions */
63 struct wlapi_timer;
64 extern struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
65 void (*fn) (void *arg), void *arg,
66 const char *name);
67 extern void wlapi_free_timer(wlc_phy_shim_info_t *physhim,
68 struct wlapi_timer *t);
69 extern void wlapi_add_timer(wlc_phy_shim_info_t *physhim,
70 struct wlapi_timer *t, uint ms, int periodic);
71 extern bool wlapi_del_timer(wlc_phy_shim_info_t *physhim,
72 struct wlapi_timer *t);
73 extern void wlapi_intrson(wlc_phy_shim_info_t *physhim);
74 extern uint32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim);
75 extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim,
76 uint32 macintmask);
77
78 extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset,
79 uint16 v);
80 extern uint16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset);
81 extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, uint8 idx,
82 uint16 mask, uint16 val, int bands);
83 extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, uint32 flags);
84 extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim);
85 extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, uint8 spurmode);
86 extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim);
87 extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, uint32 mask,
88 uint32 val);
89 extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim);
90 extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, uint16 bw);
91 extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk);
92 extern void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk);
93 extern void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on);
94 extern void wlapi_bmac_core_phypll_reset(wlc_phy_shim_info_t *physhim);
95 extern void wlapi_bmac_ucode_wake_override_phyreg_set(wlc_phy_shim_info_t *
96 physhim);
97 extern void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t *
98 physhim);
99 extern void wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int o,
100 int len, void *buf);
101 extern uint16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim,
102 uint8 rate);
103 extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim);
104 extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint,
105 void *buf, int, uint32 sel);
106 extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint,
107 const void *buf, int, uint32);
108
109 extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim,
110 uint32 phy_mode);
111 extern void wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim,
112 wl_pkteng_t *pkteng, uint8 rate,
113 struct ether_addr *sa, uint32 wait_delay);
114 extern uint16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim);
115 #endif /* _wlc_phy_shim_h_ */
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